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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. Hitachi SuperHTM RISC engine SH7750 Series SH7750, SH7750S, SH7750R Hardware Manual ADE-602-124E Rev. 6.0 7/10/2002 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Preface The SH-4 (SH7750 Series: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7750 Series is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and smart card interface. This series can be used in a wide range of multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA, as well as 64-bit synchronous DRAM 4-bank system and 64-bit data bus. Target Readers: This manual is designed for use by people who design application systems using the SH7750, SH7750S, or SH7750R. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7750, SH7750S, and SH7750R. The SH-4 Programming Manual contains detailed information of executable instructions. Please read the Programming Manual together with this manual. How to Use the Book: * To understand general functions Read the manual from the beginning. The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order. * To understanding CPU functions Refer to the separate SH-4 Programming Manual. Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.hitachisemiconductor.com/) * User manuals for SH7750, SH7750S, and SH7750R Name of Document SH7750 Series Hardware Manual SH-4 Programming Manual Document No. This manual ADE-602-156 Rev. 6.0, 07/02, page iii of I * User manuals for development tools Name of Document C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Simulator/Debugger User's Manual Hitachi Embedded Workshop User's Manual Document No. ADE-702-246 ADE-702-186 ADE-702-201 Rev. 6.0, 07/02, page iv of I List of Items Revised or Added for This Version Section Page Item Description Description amended and added Table 1.1 SH7750 Series Features Description added for LSI, and description and Note added for Clock pulse generator (CPG) SH7750 and SH7750S added to cache memory Cache memory [SH7750R] added to table Description added for Direct memory access controller (DMAC) and Timer unit (TMU) SH7750R table added to Product lineup Notes 1, 2, 3 added 1.2 Block Diagram 9 Figure 1.1 Block Diagram of SH7750 Series Functions Figure 1.2 to 1.4 Table 1.2 to 1.4 I cache 8 KB and 0 cache 16 KB deleted from table SH7750R added, and description amended Table and note amended Description deleted Figure 3.2 MMU-Related Registers 3. Page table entry assistance register (PTEA) 1. Page table entry high register (PTEH), 6. MMU control register (MMUCR) Amended SH7750R added after SH7750S Description added 1.1 SH7750 Series (SH7750, 1 SH7750S, SH7750R) Features 4 to 8 1.3 Pin Arrangement 1.4 Pin Functions 2.7 Processor Modes 3.2 Register Descriptions 10 to 12 13 to 40 55 61 62 62 3.3.1 Physical Address Space 64 to 67 Description added Rev. 6.0, 07/02, page v of I Section 3.3.3 Virtual Address Space 3.3.4 On-Chip RAM Space 3.3.7 Address Space Identifier (ASID) 4.1.1 Features Page 68, 69 69 70 Item Description Description changed Description changed Note added Completely revised 95 95 96 4.2 Register Descriptions 97 97 4.3.1 Configuration 101 4.3.6 RAM Mode 4.3.7 OC Index Mode 4.4.1 Configuration 106 to 107 107 109 Table 4.1 Cache Features (SH7750, SH7750S) Table 4.2 Cache Features (SH7750R) Table 4.3 Features of Store Queues Figure 4.1 Cache and Store Queue Control Registers (1) Cache Control Register (CCR) Figure 4.3 Configuration of Operand Cache (SH7750R) Completely revised Newly added Description added Figure changed and Note added Description added and amended Description added Newly added Description amended and added Description added Figure 4.5 amended to figure 4.6, description added and amended 110 4.6 Memory-Mapped Cache Configuration (SH7750R) 4.7 Store Queues 4.7.3 Transfer to External Memory 4.7.4 SQ Protection 4.7.5 Reading the SQs (SH7750R Only) 4.7.6 SQ Usage Notes 5.2 Register Descriptions 5.4 Exception Types and Priorities 116 122 122, 123 124 124 125 128 130 to 132 Figure 4.7 Configuration of Newly added Instruction Cache (SH7750R) Newly added Description amended and added Description added Description added Newly added Newly added Description amended Table 5.2 Exceptions Description and note added Rev. 6.0, 07/02, page vi of I Section 5.6.3 Interrupts 7.3 Instruction Set 8.3 Execution Cycles and Pipeline Stalling 9.1.1 Types of Power-Down Modes Page 157 186 204 to 206 222 Item (3) Peripheral Module Interrupts Description Description changed Table 7.7 Branch Instructions Description added Description amended Note changed Table 9.1 Status of CPU and Hardware standby Peripheral Modules in Power- (SH7750S, SH7750R) Down Modes added to table, description amended Table 9.2 Power-Down Mode Description and Note Registers added to table Table 9.3 Power-Down Mode Description added to Pins Function in table and amended Other information Other Information Bit table Description amended Added Bit 6 amended to STHZ and bit 1 to MSTP6, note added Description added Newly added Added 9.1.2 Register Configuration 9.1.3 Pin Configuration 223 223 9.2.2 Peripheral Module Pin High Impedance Control 9.2.3 Peripheral Module Pin Pull-Up Control 9.2.4 Standby Control Register 2 (STBCR2) 226 226 227 227 9.2.5 Clock-Stop Register 00 228, 229 (CLKSTP00) (SH7750R Only) 9.2.6 Clock-Stop Clear 229 Register 00 (CLKSTPCLR00) (SH7750R Only) 9.4.1 Transition to Deep Sleep Mode 9.5.2 Exit from Standby Mode 9.6.1 Transition to Module Standby Function 9.6.2 Exit from Module Standby Function 230 232 234 Bit 6, Bits 1 and 0 Description amended, Note added Exit by Interrupt Note added Text amended Table description and note added 234 Description amended Note deleted SH7750R added 9.7 Hardware Standby Mode 235 (SH7750S, SH7750R Only) Rev. 6.0, 07/02, page vii of I Section 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) 10.2.1 Block Diagram of CPG Page 244 to 246 249 Item Figures 9.12, 9.13, 9.15 Description Figures changed Notes added Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) Figure 10.1 (2) Block Diagram of CPG (SH7750R) Table 10.1 CPG Pins Table 10.2 CPG Register Amended 250 10.2.2 CPG Pin Configuration 10.2.3 CPG Register Configuration 10.3 Clock Operating Modes 253 252 252 Newly added Table and Note amended Description added Description added and amended Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S) Table amended and Note amended and added 253 254 Table 10.3 (2) Clock Newly added Operating Modes (SH7750R) Table 10.4 FRQCR Settings and Internal Clock Frequencies Table and Note amended Description amended 10.8.2 Watchdog Timer Control/Status Register (WTCSR) 10.10 Notes on Board Design 261 265 266 When Using a PLL Oscillator Circuit Figure 10.5 Points for Attention when Using PLL Oscillator Circuit Description amended Amended 11.1.1 Features 11.1.2 Block Diagram 11.1.3 Pin Configuration 267 268 269 Figure 11.1 Block Diagram of RTC Table 11.1 RTC Pins Table 11.2 RTC Registers Description added for Alarm interrupts Figure amended and Note added Table amended RTC control register 3 and Year alarm register added to table, and Note added 11.1.4 Register Configuration 270 Rev. 6.0, 07/02, page viii of I Section 11.2.2 Second Counter (RSECCNT) Page 271 Item Description Description amended Newly added 11.2.17 RTC Control 283 Register 3 (RCR3) and YearAlarm Register (RYRAR) (SH7750R Only) 11.3.3 Alarm Function 11.5.2 Carry Flag and Interrupt Flag in Standby Mode 11.5.3 Crystal Oscillator Circuit 12.1.1 Features 12.1.2 Block Diagram 288 289 Description added Added 290 Figure 11.5 Example of Crystal Oscillator Circuit Connection Note amended 291 292 Figure 12.1 Table 12.2 TMU Registers Description amended and added Block Diagram of TMU, amended Description and Note added Added Description amended and added Description amended and added Description amended and added Description added Description amended and added Table 12.3 TMU Interrupt Sources Burst ROM interface Channels 3 and 4 added to table Note added Description amended and added, and Note added Figure amended and add Note added 12.1.4 Register Configuration 293, 294 12.2.3 Timer Start Register 2 (TSTR2) 12.2.4 Timer Constant Registers (TCOR) 12.2.5 Timer Counters (TCNT) 12.2.6 Timer Control Registers (TCR) 12.3.1 Counter Operation 12.4 Interrupts 297 298 298, 299 299 304 308 309 13.1.1 Features 312 13.1.2 Block Diagram 313 Figure 13.1 Block Diagram of BSC Rev. 6.0, 07/02, page ix of I Section Page Item Table 13.2 BSC Registers Description Bus control register 3 and 4 added to table, and Note added 64* added to Area 0, 5, 6 Settable Bus Widths, and Note 7 added Description amended Table amended, and Notes amended and added Description added Bit 18 amended and note added Description added Description and notes added Description amended Table amended and note added 7 13.1.4 Register Configuration 318 13.1.5 Overview of Areas 320 Table 13.3 External Memory Space Map Space Divisions Table 13.3 External Memory Space Map Memory Bus Width Bit table Bit 31, Bit 30, Bit 29 Bit 26 Bit 16 Bit 15, Bit 14 Bits 13 to 11 Bits 10 to 8 Bits 7 to 5 Bit 0 Bits 15, 14 319 320 321, 322 13.2.1 Bus Control Register 1 (BCR1) 326 327 328 330 330 331 332 333 334 13.2.2 Bus Control Register 2 (BCR2) 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) 13.2.4 Bus Control Register 4 (BCR4) 13.2.5 Wait Control Register 1 (WCR1) 13.2.6 Wait Control Register 2 (WCR2) 335 337 338 338, 339 342 344 to 349 Description amended Description added Newly added Bits 12 to 1--Reserved Description added Newly added Note amended Bits 31 to 29, Bits 25 to 23, Bits 19 to 17, Bits 15 to 13, Bits 11 to 9, Bits 8 to 6, Bits 5 to 3, and Bits 2 to 0 Bit table Description added and amended 13.2.7 Wait Control Register 3 (WCR3) 351 351 Bits 19 and 7 changed, and Note added Description added Rev. 6.0, 07/02, page x of I Section 13.2.8 Memory Control Register (MCR) Page 355 Item Bits 15 to 13--Write Precharge Delay (TRWL2- TRWL0) For Synchronous DRAM Interface Description Description added 358 13.2.10 Synchronous DRAM 362 to Mode Register (SDMR) 364 13.3.1 Endian/Access Size and Data Alignment 13.3.2 Areas 13.3.3 SRAM Interface 370 371 382 387 387 388, 393 to 395 395 AMX6 description and Notes amended Description amended, and Note added Description amended Data Configuration Area 0, Area 1 Quadword partially amended Description added and amended Basic interface changed to SRAM interface Basic Timing Figures 13.6, 13.11 to 13.13 Read-Strobe Negate Timing (Setting Only Possible in the SH7750R) Connection of Synchronous DRAM Address Multiplexing Figure 13.28 to 13.37 Power-On Sequence Notes on Changing the Burst Length (Variation Only Possible in the SH7750R) Description amended Notes added Description added and amended Notes added Description added Description amended Note added Newly added Newly added 13.3.4 DRAM Interface 13.3.5 Synchronous DRAM Interface 400 to 408 Figures 13.17 to 13.22 413 415 417 to 428 435 438 440 Connecting a 128-Mbit/256Newly added Mbit Synchronous DRAM with 64-bit Bus Width Description amended Notes added 13.3.6 Burst ROM Interface 441, 442 442 to 444 Figure 13.46 to 13.48 Rev. 6.0, 07/02, page xi of I Section 13.3.7 PCMCIA Interface Page 444, 445 446 Item Description Description amended and added Table 13.18 Relationship between Address and CE when Using PCMCIA Interface Table amended 449, 452 to 454 450 Figures 13.50, 13.53 to 13.55 Notes added Figure 13.51 Wait Timing for SH7750R added to PCMCIA Memory Card Note Interface Figure 13.52 PCMCIA Space Amended Allocation Description added and amended Figure 13.71 MPX Interface Timing 7 Amended Notes added Description amended Notes added Replaced Description added and amended Refresh, Bus Arbitration Synchronous DRAM Mode Register Setting (SH7750, SH7750R Only) Description amended Newly added Figure 13.77 Waits between Access Cycles 451 13.3.8 MPX Interface 455 471 457 to 472 Figures 13.57 to 13.72 13.3.9 Byte Control SRAM Interface 13.3.10 Waits between Access Cycles 13.3.11 Bus Arbitration 13.3.16 Notes on Usage 473 475 to 477 Figures 13.74 to 13.76 479 480, 481 487 487 14.1 Overview 14.1.1 Features 14.1.2 Block Diagram (SH7750, SH7750S) 14.2 Register Descriptions (SH7750, SH7750S) 489 489 to 491 492 492 496 Figure 14.1 Block Diagram of DMAC Description added and amended Description amended Title amended Amended Title amended Rev. 6.0, 07/02, page xii of I Section Page Item Description Description amended Description amended 14.2.1 DMA Source Address 496 Registers 0-3 (SAR0-SAR3) 14.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) 14.2.3 DMA Transfer Count Registers 0-3 (DMATCR0- DMATCR3) 497 498 Description amended 14.2.4 DMA Channel Control 499 Registers 0-3 (CHCR0- CHCR3) 502, 503 503 505 14.2.5 DMA Operation Register (DMAOR) 14.3.2 DMA Transfer Requests 14.3.4 Types of DMA Transfer 508 513 526 Description of DDT mode added Bits 19 to 16 Bits 15, 14 and Bits 13, 12 Bits 6 to 4 Bit 4 * External Request Acceptance Conditions Initial value changed Description amended Description added Description amended Description added Table 14.9 External Request Usable DMAC channels Transfer Sources and changed Destinations in DDT Mode (a) Normal DMA Mode Figure 14.15 to 14.17 Description amendment Figure description added Description amendments %$9/: Data bus D63-D0 release signal Figures 14.26, 14.27 Figure 14.28 Figure 14.29 Figure 14.30, 14.31 c. of 3. Handshake protocol using the data bus (valid on channel 0 only) b. of 8. Data transfer end request 12. Confirming DMA transfer requests and number of transfers executed Description added Title amended Newly added Amended Errors corrected Description amended 525 14.3.5 Number of Bus Cycle States and '5(4 Pin Sampling Timing 14.5 On-Demand Data Transfer Mode (DDT Mode) 14.5.2 Pins in DDT Mode 533 to 535 545 547 14.5.3 Transfer Request 551, 552 Acceptance on Each Channel 553 554 554, 555 14.5.4 Notes on Use of DDT Module 572 573 573 Added Description amended Rev. 6.0, 07/02, page xiii of I Section 14.6 Configuration of the DMAC (SH7750R) 14.7 Register Descriptions (SH7750R) 14.8 Operation (SH7750R) 14.9 Usage Notes 15.2.8 Serial Port Register (SCSPTR1) 16.1.2 Block Diagram 16.1.3 Pin Configuration 16.2.6 Serial Control Register (SCSCR2) Page 574 579 586 591 592 609 659 660 667 Item Description Newly added Newly added Added 4. 9. Bit 7 Figure 16.1 Block Diagram of SCIF Table 16.1 SCIF Pins Bit 1 Bit 7--Receive Error (ER) Bit 3--Framing Error (FER) Bit 2--Parity Error (PER) Bits 10 to 8 Figure 16.6 MRESET/SCK2 Pin Description amended Newly added Description amended Amended Note changed Description amended Note description changed Description changed Description changed SH7750R added Deleted Amended Description added to 5. Description amended Description deleted 16.2.7 Serial Status Register 669 (SCFSR2) 672 672 16.2.9 FIFO Control Register 676 (SCFCR2) 16.2.11 Serial Port Register (SCSPTR2) 16.3.2 Serial Operation 689 696 17.1 Overview 17.3.2 Pin Connections 18.1.3 Pin Configuration 19.1.2 Block Diagram 703 711 740 752 Figure 16.6 Sample SCIF Initialization Flowchart Serial Data Reception Table 18.3 SCIF I/O Port Pins Figure 19.1 Block Diagram of INTC Table 19.2 INTC Registers Amended Amended Description added to table, Notes added and amended Description added and amended 19.1.4 Register Configuration 753 19.2.3 On-Chip Peripheral Module Interrupts 757, 758 Rev. 6.0, 07/02, page xiv of I Section 19.2.4 Interrupt Exception Handling and Priority Page 758 759 to 761 762 Item Description Description added Table 19.5 Interrupt Exception Handling Sources and Priority Order Description added to table, Notes added and amended 19.3.1 Interrupt Priority Registers A to D (IPRA- IPRD) Table 19.6 Interrupt Request SH7750R added to Sources and IPRA-IPRD Note 3 Registers Newly added 19.3.3 Interrupt-Priority-Level 764 Setting Register 00 (INTPRI00) 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only) 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) 765 Newly added 766 Newly added 19.3.6 Interrupt Mask Clear 767 Register 00 (INTMSKCLR00) (SH7750R Only) 19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only) 19.4.1 Interrupt Operation Sequence 19.5 Interrupt Response Time 20.2.4 Break Address Mask Register (BAMRA) 20.2.10 Break Data Mask Register B (BDMRB) 20.3.7 Program Counter (PC) Value Saved 20.4 User Break Debug Support Function 21.1.1 Features 21.1.2 Block Diagram 767 Newly added 19.3.4 moved to 19.3.7 768 771 778, 779 783 791 794 Bit 2, and Bits 3, 1, and 0 Bits 31 to 0 20.3.7 Program Counter (PC) Value Saved Figure 20.2 User Break Debug Support Function Flowchart Figure 21.1 Block Diagram of H-UDI Circuit Note 3 added Note amended Description added Description added 4. Description added Amended 799 800 Description amended Figure changed and Note added Rev. 6.0, 07/02, page xv of I Section 21.1.3 Pin Configuration Page 801 Item Table 21.1 H-UDI Pins Table 21.2 H-UDI Registers Description Table amended and Note 3 added Description added to table and Notes 3 and 4 added [SH7750R] description added Newly added Newly added 21.1.4 Register Configuration 802 21.2.1 Instruction Register (SDIR) 21.2.4 Interrupt Source Register (SDINT) 21.2.5 Boundary Scan Register (SDBSR) 804 806 806 808, 809 Table 21.3 Configuration of the Boundary Scan Register (2), (3) Newly added 21.3.3 H-UDI Interrupt 21.3.4 BYPASS 21.3.4 Boundary Scan (EXTEST, SAMPLE/ PRELOAD, BYPASS) 21.4 Usage Notes 22.1 Absolute Maximum Ratings 22.2 DC Characteristics 811 812 Description changed Deleted Newly added 812 813 814, 815 5. Table 22.1 Absolute Maximum Ratings Table 22.2 DC Characteristics (HD6417750RBP240) Table 22.3 DC Characteristics (HD6417750RF240) Table 22.4 DC Characteristics (HD6417750RBP200) Table 22.5 DC Characteristics (HD6417750RF200) Table 22.6 DC Characteristics (HD6417750SBP200) Table 22.8 DC Characteristics (HD6417750BP200M) Description added Table amended and notes amended Newly added 816, 817 Newly added 818, 819 Newly added 820, 821 Newly added 822, 823 Amended 826, 827 Amended Rev. 6.0, 07/02, page xvi of I Section 22.2 DC Characteristics Page 836, 837 Item Table 22.13 DC Characteristics (HD6417750SVF133) Table 22.14 DC Characteristics (HD6417750SVBT133) Table 22.15 DC Characteristics (HD6417750VF128) Table 22.17 Clock Timing (HD6417750RBP240) Table 22.18 Clock Timing (HD6417750RF240) Table 22.19 Clock Timing (HD6417750BP200M, HD6417750SBP200, HD6417750RBP200) Table 22.20 Clock Timing (HD6417750RF200) Table 22.21 Clock Timing (HD6417750SF200) Table 22.22 Clock Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I) Table 22.23 Clock Timing (HD6417750SVF133, HD6417750SVBT133) Table 22.24 Clock Timing (HD6417750VF128) Table 22.25 Clock and Control Signal Timing (HD6417750RBP240) Table 22.26 Clock and Control Signal Timing (HD6417750RF240) Table 22.27 Clock and Control Signal Timing (HD6417750RBP200) Description Amended 838, 839 Amended 840, 841 Amended 22.3 AC Characteristics 842 842 842 Newly added Newly added HD6417750RBP200 clock timing added 842 842 843 Newly added Amended Amended 843 Amended 843 22.3.1 Clock and Control Signal Timing 844, 845 Amended Newly added 846, 847 Newly added 848, 849 Newly added Rev. 6.0, 07/02, page xvii of I Section 22.3.1 Clock and Control Signal Timing Page 850, 851 Item Table 22.28 Clock and Control Signal Timing (HD6417750RF200) Table 22.29 Clock and Control Signal Timing (HD6417750BP200M, HD6417750SBP200) Table 22.30 Clock and Control Signal Timing (HD6417750SF200) Table 22.31 Clock and Control Signal Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I) Table 22.32 Clock and Control Signal Timing (HD6417750SVF133, HD6417750SVBT133) Table 22.33 Clock and Control Signal Timing (HD6417750VF128) Figure 22.6 Standby Return Oscillation Settling Time (Return by 5(6(7) Figure 22.8 Standby Return Oscillation Settling Time (Return by ,5/6-,5/3) Description Newly added 852, 853 Newly added 854, 855 Amended 856, 857 Amended 858, 859 Amended 860, 861 Amended 864 Amended 865 Amended 866 Figure 22.10 PLL Amended Synchronization Settling Time in Case of IRL Interrupt Table 22.34 Control Signal Timing (1) Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Figure 22.19 Burst ROM Bus Cycle (No Wait) Table 22.35 Bus Timing (1) Table newly added Figure changed and Note added 22.3.2 Control Signal Timing 868 22.3.3 Bus Timing 880 881 871, 872 Amended Table newly added Rev. 6.0, 07/02, page xviii of I Section 22.3.4 Peripheral Module Signal Timing Page 924, 925 900 to 921, 923 930 932 Item Table 22.36 Peripheral Module Signal Timing (1) Figures 22.37 to 22.58, Figure 22.60 Description Table newly added Titles amended Figure 22.62 RTC Oscillation Amended Settling Time at Power-On Figure 22.66(b) '%5(4/75 Input Timing and %$9/ Output Timing Table A.1 Address List Newly added Appendix A Address List 937 to 942 BCR4, RCR3, RYRAR, SDINT and Notes added BCR3 area 7 address amended DMAC, INTC, CPG, TMU table added Appendix B Package Dimensions 943, 944 Figure B.1 Package Dimensions (256-Pin BGA) Figure B.2 Package Dimensions (208-Pin QFP) Amended Appendix C Mode Pin Settings 946 947 Clock Modes Area 0 Bus Width Table 10.3 (1), (2) inserted Area 0 memory type deleted and data integrated into area 0 bus width table Amended Sleep row deleted D40-D51 deleted Notes added Newly added Appendix D &.,25(1% Pin Configuration Appendix E Pin Functions 948 950 to 952 Figure D.1 &.,25(1% Pin Configuration Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State (17) BUS 64 (128M: 4M x 8b x 4) x 8 (SH7750R only) (18) BUS 64 (256M: 4M x 16b x 4) x 4 (SH7750R only) Appendix F Synchronous DRAM Address Multiplexing Tables 970, 971 Rev. 6.0, 07/02, page xix of I Section Appendix F Synchronous DRAM Address Multiplexing Tables Page 972, 973 Item (19) BUS 32 (128M: 4M x 8b x 4) x 4 (SH7750S and SH7750R only) (20) BUS 32 (256M: 4M x 16b x 4) x 2 (SH7750S and SH7750R only) Description SH7750R added Appendix H Power-On and Power-Off Procedures Appendix I Product Code Lineup 977 to 979 980 Table I.1 SH7750 Series Product Code Lineup Newly added SH7750R added Rev. 6.0, 07/02, page xx of I Contents Section 1 1.1 1.2 1.3 1.4 Overview........................................................................................................... SH7750 Series (SH7750, SH7750S, SH7750R) Features ................................................. Block Diagram .................................................................................................................. Pin Arrangement ............................................................................................................... Pin Functions..................................................................................................................... 1.4.1 Pin Functions (256-Pin BGA) .............................................................................. 1.4.2 Pin Functions (208-Pin QFP) ............................................................................... 1.4.3 Pin Functions (264-Pin CSP) ............................................................................... 1 1 9 10 13 13 23 31 Section 2 2.1 2.2 Programming Model...................................................................................... 41 41 42 42 45 47 49 50 52 53 53 54 55 2.3 2.4 2.5 2.6 2.7 Data Formats ..................................................................................................................... Register Configuration ...................................................................................................... 2.2.1 Privileged Mode and Banks ................................................................................. 2.2.2 General Registers ................................................................................................. 2.2.3 Floating-Point Registers ....................................................................................... 2.2.4 Control Registers.................................................................................................. 2.2.5 System Registers .................................................................................................. Memory-Mapped Registers ............................................................................................... Data Format in Registers ................................................................................................... Data Formats in Memory .................................................................................................. Processor States................................................................................................................. Processor Modes ............................................................................................................... Section 3 3.1 Memory Management Unit (MMU) ......................................................... 57 57 57 57 60 60 61 64 64 67 68 69 69 70 70 71 3.2 3.3 3.4 Overview ........................................................................................................................... 3.1.1 Features ................................................................................................................ 3.1.2 Role of the MMU ................................................................................................. 3.1.3 Register Configuration ......................................................................................... 3.1.4 Caution ................................................................................................................. Register Descriptions ........................................................................................................ Address Space ................................................................................................................... 3.3.1 Physical Address Space........................................................................................ 3.3.2 External Memory Space ....................................................................................... 3.3.3 Virtual Address Space.......................................................................................... 3.3.4 On-Chip RAM Space ........................................................................................... 3.3.5 Address Translation.............................................................................................. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode.................... 3.3.7 Address Space Identifier (ASID) ......................................................................... TLB Functions................................................................................................................... Rev. 6.0, 07/02, page xxi of I 3.5 3.6 3.7 3.4.1 Unified TLB (UTLB) Configuration.................................................................... 3.4.2 Instruction TLB (ITLB) Configuration ................................................................ 3.4.3 Address Translation Method ................................................................................ MMU Functions ................................................................................................................ 3.5.1 MMU Hardware Management ............................................................................. 3.5.2 MMU Software Management............................................................................... 3.5.3 MMU Instruction (LDTLB) ................................................................................. 3.5.4 Hardware ITLB Miss Handling............................................................................ 3.5.5 Avoiding Synonym Problems .............................................................................. MMU Exceptions .............................................................................................................. 3.6.1 Instruction TLB Multiple Hit Exception .............................................................. 3.6.2 Instruction TLB Miss Exception .......................................................................... 3.6.3 Instruction TLB Protection Violation Exception.................................................. 3.6.4 Data TLB Multiple Hit Exception........................................................................ 3.6.5 Data TLB Miss Exception.................................................................................... 3.6.6 Data TLB Protection Violation Exception ........................................................... 3.6.7 Initial Page Write Exception ................................................................................ Memory-Mapped TLB Configuration ............................................................................... 3.7.1 ITLB Address Array............................................................................................. 3.7.2 ITLB Data Array 1 ............................................................................................... 3.7.3 ITLB Data Array 2 ............................................................................................... 3.7.4 UTLB Address Array ........................................................................................... 3.7.5 UTLB Data Array 1.............................................................................................. 3.7.6 UTLB Data Array 2.............................................................................................. 71 75 75 78 78 78 78 79 80 81 81 82 83 84 84 85 86 87 88 89 90 90 92 93 Section 4 4.1 4.2 4.3 4.4 Caches................................................................................................................ 95 Overview ........................................................................................................................... 95 4.1.1 Features ................................................................................................................ 95 4.1.2 Register Configuration ......................................................................................... 96 Register Descriptions ........................................................................................................ 97 Operand Cache (OC) ......................................................................................................... 99 4.3.1 Configuration ....................................................................................................... 99 4.3.2 Read Operation..................................................................................................... 103 4.3.3 Write Operation.................................................................................................... 104 4.3.4 Write-Back Buffer................................................................................................ 105 4.3.5 Write-Through Buffer .......................................................................................... 105 4.3.6 RAM Mode .......................................................................................................... 106 4.3.7 OC Index Mode.................................................................................................... 107 4.3.8 Coherency between Cache and External Memory ............................................... 107 4.3.9 Prefetch Operation ............................................................................................... 108 Instruction Cache (IC) ....................................................................................................... 108 4.4.1 Configuration ....................................................................................................... 108 4.4.2 Read Operation..................................................................................................... 111 Rev. 6.0, 07/02, page xxii of I 4.5 4.6 4.7 4.4.3 IC Index Mode ..................................................................................................... 111 Memory-Mapped Cache Configuration (SH7750, SH7750S)........................................... 112 4.5.1 IC Address Array ................................................................................................. 112 4.5.2 IC Data Array ....................................................................................................... 113 4.5.3 OC Address Array................................................................................................ 114 4.5.4 OC Data Array ..................................................................................................... 115 Memory-Mapped Cache Configuration (SH7750R) ......................................................... 116 4.6.1 IC Address Array ................................................................................................. 117 4.6.2 IC Data Array ....................................................................................................... 118 4.6.3 OC Address Array................................................................................................ 119 4.6.4 OC Data Array ..................................................................................................... 120 4.6.5 Summary of the Memory-Mapping of the OC ..................................................... 121 Store Queues ..................................................................................................................... 122 4.7.1 SQ Configuration ................................................................................................. 122 4.7.2 SQ Writes ............................................................................................................. 122 4.7.3 Transfer to External Memory ............................................................................... 122 4.7.4 SQ Protection ....................................................................................................... 124 4.7.5 Reading the SQs (SH7750R Only)....................................................................... 124 4.7.6 SQ Usage Notes ................................................................................................... 125 Section 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Exceptions ........................................................................................................ 127 Overview ........................................................................................................................... 127 5.1.1 Features ................................................................................................................ 127 5.1.2 Register Configuration ......................................................................................... 127 Register Descriptions ........................................................................................................ 128 Exception Handling Functions .......................................................................................... 129 5.3.1 Exception Handling Flow..................................................................................... 129 5.3.2 Exception Handling Vector Addresses................................................................. 129 Exception Types and Priorities.......................................................................................... 130 Exception Flow ................................................................................................................. 132 5.5.1 Exception Flow .................................................................................................... 132 5.5.2 Exception Source Acceptance .............................................................................. 133 5.5.3 Exception Requests and BL Bit............................................................................ 135 5.5.4 Return from Exception Handling ......................................................................... 135 Description of Exceptions ................................................................................................. 135 5.6.1 Resets ................................................................................................................... 136 5.6.2 General Exceptions .............................................................................................. 141 5.6.3 Interrupts .............................................................................................................. 155 5.6.4 Priority Order with Multiple Exceptions.............................................................. 158 Usage Notes....................................................................................................................... 159 Restrictions........................................................................................................................ 160 Rev. 6.0, 07/02, page xxiii of I Section 6 6.1 6.2 6.3 6.4 6.5 6.6 Floating-Point Unit ........................................................................................ 161 Overview ........................................................................................................................... 161 Data Formats ..................................................................................................................... 161 6.2.1 Floating-Point Format .......................................................................................... 161 6.2.2 Non-Numbers (NaN)............................................................................................ 163 6.2.3 Denormalized Numbers........................................................................................ 164 Registers ............................................................................................................................ 165 6.3.1 Floating-Point Registers ....................................................................................... 165 6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................. 167 6.3.3 Floating-Point Communication Register (FPUL)................................................. 168 Rounding ........................................................................................................................... 168 Floating-Point Exceptions ................................................................................................. 169 Graphics Support Functions .............................................................................................. 170 6.6.1 Geometric Operation Instructions ........................................................................ 170 6.6.2 Pair Single-Precision Data Transfer ..................................................................... 172 Section 7 7.1 7.2 7.3 Instruction Set.................................................................................................. 173 Execution Environment..................................................................................................... 173 Addressing Modes............................................................................................................. 175 Instruction Set ................................................................................................................... 179 Pipelining .......................................................................................................... 193 Pipelines ............................................................................................................................ 193 Parallel-Executability ........................................................................................................ 200 Execution Cycles and Pipeline Stalling............................................................................. 204 Section 8 8.1 8.2 8.3 Section 9 9.1 9.2 9.3 9.4 Power-Down Modes ...................................................................................... 221 Overview ........................................................................................................................... 221 9.1.1 Types of Power-Down Modes.............................................................................. 221 9.1.2 Register Configuration ......................................................................................... 223 9.1.3 Pin Configuration ................................................................................................. 223 Register Descriptions ........................................................................................................ 224 9.2.1 Standby Control Register (STBCR) ..................................................................... 224 9.2.2 Peripheral Module Pin High Impedance Control ................................................. 226 9.2.3 Peripheral Module Pin Pull-Up Control ............................................................... 226 9.2.4 Standby Control Register 2 (STBCR2) ................................................................ 227 9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)...................................... 228 9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only) .................... 229 Sleep Mode........................................................................................................................ 230 9.3.1 Transition to Sleep Mode ..................................................................................... 230 9.3.2 Exit from Sleep Mode .......................................................................................... 230 Deep Sleep Mode .............................................................................................................. 230 9.4.1 Transition to Deep Sleep Mode............................................................................ 230 Rev. 6.0, 07/02, page xxiv of I 9.5 9.6 9.7 9.8 9.4.2 Exit from Deep Sleep Mode................................................................................. 231 Standby Mode ................................................................................................................... 231 9.5.1 Transition to Standby Mode................................................................................. 231 9.5.2 Exit from Standby Mode ...................................................................................... 232 9.5.3 Clock Pause Function........................................................................................... 232 Module Standby Function ................................................................................................. 233 9.6.1 Transition to Module Standby Function............................................................... 233 9.6.2 Exit from Module Standby Function.................................................................... 234 Hardware Standby Mode (SH7750S, SH7750R Only) ..................................................... 235 9.7.1 Transition to Hardware Standby Mode ................................................................ 235 9.7.2 Exit from Hardware Standby Mode ..................................................................... 235 9.7.3 Usage Notes ......................................................................................................... 235 STATUS Pin Change Timing............................................................................................ 236 9.8.1 In Reset................................................................................................................. 237 9.8.2 In Exit from Standby Mode.................................................................................. 238 9.8.3 In Exit from Sleep Mode...................................................................................... 240 9.8.4 In Exit from Deep Sleep Mode............................................................................. 242 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only)............................ 244 Section 10 Clock Oscillation Circuits............................................................................ 247 10.1 Overview ........................................................................................................................... 247 10.1.1 Features ................................................................................................................ 247 10.2 Overview of CPG .............................................................................................................. 249 10.2.1 Block Diagram of CPG ........................................................................................ 249 10.2.2 CPG Pin Configuration ........................................................................................ 252 10.2.3 CPG Register Configuration ................................................................................ 252 10.3 Clock Operating Modes..................................................................................................... 253 10.4 CPG Register Description ................................................................................................. 254 10.4.1 Frequency Control Register (FRQCR) ................................................................. 254 10.5 Changing the Frequency.................................................................................................... 257 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off)............ 257 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On) ............ 257 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On)....................... 258 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off) ...................... 258 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio................................ 258 10.6 Output Clock Control ........................................................................................................ 258 10.7 Overview of Watchdog Timer........................................................................................... 259 10.7.1 Block Diagram ..................................................................................................... 259 10.7.2 Register Configuration ......................................................................................... 260 10.8 WDT Register Descriptions .............................................................................................. 260 10.8.1 Watchdog Timer Counter (WTCNT) ................................................................... 260 10.8.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 261 10.8.3 Notes on Register Access ..................................................................................... 263 Rev. 6.0, 07/02, page xxv of I 10.9 Using the WDT ................................................................................................................. 263 10.9.1 Standby Clearing Procedure................................................................................. 263 10.9.2 Frequency Changing Procedure ........................................................................... 264 10.9.3 Using Watchdog Timer Mode.............................................................................. 264 10.9.4 Using Interval Timer Mode.................................................................................. 265 10.10 Notes on Board Design...................................................................................................... 265 Section 11 Realtime Clock (RTC) .................................................................................. 267 11.1 Overview ........................................................................................................................... 267 11.1.1 Features ................................................................................................................ 267 11.1.2 Block Diagram ..................................................................................................... 268 11.1.3 Pin Configuration ................................................................................................. 269 11.1.4 Register Configuration ......................................................................................... 269 11.2 Register Descriptions ........................................................................................................ 271 11.2.1 64 Hz Counter (R64CNT) .................................................................................... 271 11.2.2 Second Counter (RSECCNT)............................................................................... 271 11.2.3 Minute Counter (RMINCNT) .............................................................................. 272 11.2.4 Hour Counter (RHRCNT) .................................................................................... 272 11.2.5 Day-of-Week Counter (RWKCNT) ..................................................................... 273 11.2.6 Day Counter (RDAYCNT) .................................................................................. 274 11.2.7 Month Counter (RMONCNT).............................................................................. 274 11.2.8 Year Counter (RYRCNT) .................................................................................... 275 11.2.9 Second Alarm Register (RSECAR)...................................................................... 276 11.2.10 Minute Alarm Register (RMINAR) ..................................................................... 276 11.2.11 Hour Alarm Register (RHRAR)........................................................................... 277 11.2.12 Day-of-Week Alarm Register (RWKAR) ............................................................ 277 11.2.13 Day Alarm Register (RDAYAR) ......................................................................... 278 11.2.14 Month Alarm Register (RMONAR)..................................................................... 279 11.2.15 RTC Control Register 1 (RCR1) .......................................................................... 279 11.2.16 RTC Control Register 2 (RCR2) .......................................................................... 281 11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR) (SH7750R Only) .................................................................................................. 283 11.3 Operation........................................................................................................................... 285 11.3.1 Time Setting Procedures ...................................................................................... 285 11.3.2 Time Reading Procedures .................................................................................... 286 11.3.3 Alarm Function .................................................................................................... 288 11.4 Interrupts ........................................................................................................................... 289 11.5 Usage Notes....................................................................................................................... 289 11.5.1 Register Initialization ........................................................................................... 289 11.5.2 Carry Flag and Interrupt Flag in Standby Mode................................................... 289 11.5.3 Crystal Oscillator Circuit...................................................................................... 289 Rev. 6.0, 07/02, page xxvi of I Section 12 Timer Unit (TMU) ......................................................................................... 291 12.1 Overview ........................................................................................................................... 291 12.1.1 Features ................................................................................................................ 291 12.1.2 Block Diagram ..................................................................................................... 292 12.1.3 Pin Configuration ................................................................................................. 292 12.1.4 Register Configuration ......................................................................................... 293 12.2 Register Descriptions ........................................................................................................ 295 12.2.1 Timer Output Control Register (TOCR) .............................................................. 295 12.2.2 Timer Start Register (TSTR) ................................................................................ 296 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only)............................................... 297 12.2.4 Timer Constant Registers (TCOR)....................................................................... 298 12.2.5 Timer Counters (TCNT)....................................................................................... 298 12.2.6 Timer Control Registers (TCR)............................................................................ 299 12.2.7 Input Capture Register (TCPR2) .......................................................................... 303 12.3 Operation........................................................................................................................... 304 12.3.1 Counter Operation ................................................................................................ 304 12.3.2 Input Capture Function......................................................................................... 307 12.4 Interrupts ........................................................................................................................... 308 12.5 Usage Notes....................................................................................................................... 309 12.5.1 Register Writes..................................................................................................... 309 12.5.2 TCNT Register Reads .......................................................................................... 309 12.5.3 Resetting the RTC Frequency Divider ................................................................. 309 12.5.4 External Clock Frequency .................................................................................... 309 Section 13 Bus State Controller (BSC) ......................................................................... 311 13.1 Overview ........................................................................................................................... 311 13.1.1 Features ................................................................................................................ 311 13.1.2 Block Diagram ..................................................................................................... 313 13.1.3 Pin Configuration ................................................................................................. 314 13.1.4 Register Configuration ......................................................................................... 318 13.1.5 Overview of Areas ............................................................................................... 319 13.1.6 PCMCIA Support................................................................................................. 322 13.2 Register Descriptions ........................................................................................................ 326 13.2.1 Bus Control Register 1 (BCR1)............................................................................ 326 13.2.2 Bus Control Register 2 (BCR2)............................................................................ 335 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) ............................................... 337 13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only) ............................................... 338 13.2.5 Wait Control Register 1 (WCR1) ......................................................................... 340 13.2.6 Wait Control Register 2 (WCR2) ......................................................................... 343 13.2.7 Wait Control Register 3 (WCR3) ......................................................................... 351 13.2.8 Memory Control Register (MCR) ........................................................................ 352 13.2.9 PCMCIA Control Register (PCR) ........................................................................ 359 13.2.10 Synchronous DRAM Mode Register (SDMR)..................................................... 362 Rev. 6.0, 07/02, page xxvii of I 13.2.11 Refresh Timer Control/Status Register (RTCSR) ................................................ 364 13.2.12 Refresh Timer Counter (RTCNT) ........................................................................ 367 13.2.13 Refresh Time Constant Register (RTCOR).......................................................... 368 13.2.14 Refresh Count Register (RFCR)........................................................................... 369 13.2.15 Notes on Accessing Refresh Control Registers.................................................... 369 13.3 Operation........................................................................................................................... 370 13.3.1 Endian/Access Size and Data Alignment ............................................................. 370 13.3.2 Areas .................................................................................................................... 382 13.3.3 SRAM Interface ................................................................................................... 387 13.3.4 DRAM Interface................................................................................................... 395 13.3.5 Synchronous DRAM Interface............................................................................. 413 13.3.6 Burst ROM Interface............................................................................................ 441 13.3.7 PCMCIA Interface ............................................................................................... 444 13.3.8 MPX Interface...................................................................................................... 455 13.3.9 Byte Control SRAM Interface.............................................................................. 473 13.3.10 Waits between Access Cycles .............................................................................. 478 13.3.11 Bus Arbitration..................................................................................................... 480 13.3.12 Master Mode ........................................................................................................ 483 13.3.13 Slave Mode........................................................................................................... 484 13.3.14 Partial-Sharing Master Mode ............................................................................... 485 13.3.15 Cooperation between Master and Slave ............................................................... 486 13.3.16 Notes on Usage .................................................................................................... 487 Section 14 Direct Memory Access Controller (DMAC).......................................... 489 14.1 Overview ........................................................................................................................... 489 14.1.1 Features ................................................................................................................ 489 14.1.2 Block Diagram (SH7750, SH7750S) ................................................................... 492 14.1.3 Pin Configuration (SH7750, SH7750S) ............................................................... 493 14.1.4 Register Configuration (SH7750, SH7750S) ....................................................... 494 14.2 Register Descriptions (SH7750, SH7750S)....................................................................... 496 14.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3)........................................... 496 14.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) .................................. 497 14.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3) ......................... 498 14.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) ................................... 499 14.2.5 DMA Operation Register (DMAOR) ................................................................... 507 14.3 Operation........................................................................................................................... 510 14.3.1 DMA Transfer Procedure..................................................................................... 510 14.3.2 DMA Transfer Requests....................................................................................... 512 14.3.3 Channel Priorities................................................................................................. 515 14.3.4 Types of DMA Transfer ....................................................................................... 518 14.3.5 Number of Bus Cycle States and '5(4 Pin Sampling Timing........................... 527 14.3.6 Ending DMA Transfer ......................................................................................... 541 14.4 Examples of Use................................................................................................................ 544 Rev. 6.0, 07/02, page xxviii of I 14.5 14.6 14.7 14.8 14.9 14.4.1 Examples of Transfer between External Memory and an External Device with DACK .......................................................................................................... 544 On-Demand Data Transfer Mode (DDT Mode)................................................................ 545 14.5.1 Operation.............................................................................................................. 545 14.5.2 Pins in DDT Mode ............................................................................................... 547 14.5.3 Transfer Request Acceptance on Each Channel................................................... 550 14.5.4 Notes on Use of DDT Module ............................................................................. 571 Configuration of the DMAC (SH7750R) .......................................................................... 574 14.6.1 Block Diagram of the DMAC .............................................................................. 574 14.6.2 Pin Configuration (SH7750R).............................................................................. 575 14.6.3 Register Configuration (SH7750R)...................................................................... 576 Register Descriptions (SH7750R) ..................................................................................... 579 14.7.1 DMA Source Address Registers 0-7 (SAR0-SAR7)........................................... 579 14.7.2 DMA Destination Address Registers 0-7 (DAR0-DAR7) .................................. 579 14.7.3 DMA Transfer Count Registers 0-7 (DMATCR0-DMATCR7) ......................... 580 14.7.4 DMA Channel Control Registers 0-7 (CHCR0-CHCR7) ................................... 580 14.7.5 DMA Operation Register (DMAOR) ................................................................... 583 Operation (SH7750R)........................................................................................................ 586 14.8.1 Channel Specification for a Normal DMA Transfer ............................................ 586 14.8.2 Channel Specification for DDT-Mode DMA Transfer ........................................ 586 14.8.3 Transfer Channel Notification in DDT Mode ...................................................... 586 14.8.4 Clearing Request Queues by DTR Format........................................................... 587 14.8.5 Interrupt-Request Codes....................................................................................... 588 Usage Notes....................................................................................................................... 591 Section 15 Serial Communication Interface (SCI)..................................................... 593 15.1 Overview ........................................................................................................................... 593 15.1.1 Features ................................................................................................................ 593 15.1.2 Block Diagram ..................................................................................................... 595 15.1.3 Pin Configuration ................................................................................................. 596 15.1.4 Register Configuration ......................................................................................... 596 15.2 Register Descriptions ........................................................................................................ 597 15.2.1 Receive Shift Register (SCRSR1) ........................................................................ 597 15.2.2 Receive Data Register (SCRDR1)........................................................................ 597 15.2.3 Transmit Shift Register (SCTSR1)....................................................................... 598 15.2.4 Transmit Data Register (SCTDR1) ...................................................................... 598 15.2.5 Serial Mode Register (SCSMR1) ......................................................................... 599 15.2.6 Serial Control Register (SCSCR1) ....................................................................... 601 15.2.7 Serial Status Register (SCSSR1) .......................................................................... 605 15.2.8 Serial Port Register (SCSPTR1)........................................................................... 609 15.2.9 Bit Rate Register (SCBRR1) ................................................................................ 613 15.3 Operation........................................................................................................................... 621 15.3.1 Overview .............................................................................................................. 621 Rev. 6.0, 07/02, page xxix of I 15.3.2 Operation in Asynchronous Mode ....................................................................... 623 15.3.3 Multiprocessor Communication Function............................................................ 634 15.3.4 Operation in Synchronous Mode.......................................................................... 642 15.4 SCI Interrupt Sources and DMAC .................................................................................... 651 15.5 Usage Notes....................................................................................................................... 652 Section 16 Serial Communication Interface with FIFO (SCIF)............................. 657 16.1 Overview ........................................................................................................................... 657 16.1.1 Features ................................................................................................................ 657 16.1.2 Block Diagram ..................................................................................................... 659 16.1.3 Pin Configuration ................................................................................................. 660 16.1.4 Register Configuration ......................................................................................... 661 16.2 Register Descriptions ........................................................................................................ 661 16.2.1 Receive Shift Register (SCRSR2) ........................................................................ 661 16.2.2 Receive FIFO Data Register (SCFRDR2)............................................................ 662 16.2.3 Transmit Shift Register (SCTSR2)....................................................................... 662 16.2.4 Transmit FIFO Data Register (SCFTDR2) .......................................................... 663 16.2.5 Serial Mode Register (SCSMR2) ......................................................................... 663 16.2.6 Serial Control Register (SCSCR2) ....................................................................... 665 16.2.7 Serial Status Register (SCFSR2) .......................................................................... 668 16.2.8 Bit Rate Register (SCBRR2) ................................................................................ 674 16.2.9 FIFO Control Register (SCFCR2)........................................................................ 675 16.2.10 FIFO Data Count Register (SCFDR2) ................................................................. 678 16.2.11 Serial Port Register (SCSPTR2)........................................................................... 679 16.2.12 Line Status Register (SCLSR2)............................................................................ 684 16.3 Operation........................................................................................................................... 685 16.3.1 Overview .............................................................................................................. 685 16.3.2 Serial Operation ................................................................................................... 686 16.4 SCIF Interrupt Sources and the DMAC ............................................................................ 697 16.5 Usage Notes....................................................................................................................... 698 Section 17 Smart Card Interface...................................................................................... 703 17.1 Overview ........................................................................................................................... 703 17.1.1 Features ................................................................................................................ 703 17.1.2 Block Diagram ..................................................................................................... 704 17.1.3 Pin Configuration ................................................................................................. 705 17.1.4 Register Configuration ......................................................................................... 705 17.2 Register Descriptions ........................................................................................................ 706 17.2.1 Smart Card Mode Register (SCSCMR1) ............................................................. 706 17.2.2 Serial Mode Register (SCSMR1) ......................................................................... 707 17.2.3 Serial Control Register (SCSCR1) ....................................................................... 708 17.2.4 Serial Status Register (SCSSR1) .......................................................................... 709 17.3 Operation........................................................................................................................... 710 Rev. 6.0, 07/02, page xxx of I 17.3.1 Overview .............................................................................................................. 710 17.3.2 Pin Connections ................................................................................................... 711 17.3.3 Data Format.......................................................................................................... 712 17.3.4 Register Settings................................................................................................... 713 17.3.5 Clock .................................................................................................................... 715 17.3.6 Data Transmit/Receive Operations....................................................................... 718 17.4 Usage Notes....................................................................................................................... 725 Section 18 I/O Ports ............................................................................................................ 731 18.1 Overview ........................................................................................................................... 731 18.1.1 Features ................................................................................................................ 731 18.1.2 Block Diagrams.................................................................................................... 732 18.1.3 Pin Configuration ................................................................................................. 739 18.1.4 Register Configuration ......................................................................................... 741 18.2 Register Descriptions ........................................................................................................ 742 18.2.1 Port Control Register A (PCTRA) ....................................................................... 742 18.2.2 Port Data Register A (PDTRA)............................................................................ 743 18.2.3 Port Control Register B (PCTRB)........................................................................ 744 18.2.4 Port Data Register B (PDTRB) ............................................................................ 745 18.2.5 GPIO Interrupt Control Register (GPIOIC) ......................................................... 745 18.2.6 Serial Port Register (SCSPTR1)........................................................................... 746 18.2.7 Serial Port Register (SCSPTR2)........................................................................... 748 Section 19 Interrupt Controller (INTC)......................................................................... 751 19.1 Overview ........................................................................................................................... 751 19.1.1 Features ................................................................................................................ 751 19.1.2 Block Diagram ..................................................................................................... 751 19.1.3 Pin Configuration ................................................................................................. 753 19.1.4 Register Configuration ......................................................................................... 753 19.2 Interrupt Sources ............................................................................................................... 754 19.2.1 NMI Interrupt ....................................................................................................... 754 19.2.2 IRL Interrupts....................................................................................................... 755 19.2.3 On-Chip Peripheral Module Interrupts................................................................. 757 19.2.4 Interrupt Exception Handling and Priority ........................................................... 758 19.3 Register Descriptions ........................................................................................................ 761 19.3.1 Interrupt Priority Registers A to D (IPRA-IPRD) ............................................... 761 19.3.2 Interrupt Control Register (ICR) .......................................................................... 762 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)........ 764 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only) .............................. 765 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only)................................ 766 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) .............. 767 19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only) ..................................................................................................767 Rev. 6.0, 07/02, page xxxi of I 19.4 INTC Operation................................................................................................................. 768 19.4.1 Interrupt Operation Sequence............................................................................... 768 19.4.2 Multiple Interrupts................................................................................................ 770 19.4.3 Interrupt Masking with MAI Bit .......................................................................... 770 19.5 Interrupt Response Time ................................................................................................... 771 Section 20 User Break Controller (UBC) ..................................................................... 773 20.1 Overview ........................................................................................................................... 773 20.1.1 Features ................................................................................................................ 773 20.1.2 Block Diagram ..................................................................................................... 774 20.2 Register Descriptions ........................................................................................................ 776 20.2.1 Access to UBC Control Registers ........................................................................ 776 20.2.2 Break Address Register A (BARA) ..................................................................... 777 20.2.3 Break ASID Register A (BASRA) ....................................................................... 778 20.2.4 Break Address Mask Register A (BAMRA) ........................................................ 778 20.2.5 Break Bus Cycle Register A (BBRA) .................................................................. 779 20.2.6 Break Address Register B (BARB) ...................................................................... 781 20.2.7 Break ASID Register B (BASRB) ....................................................................... 781 20.2.8 Break Address Mask Register B (BAMRB)......................................................... 781 20.2.9 Break Data Register B (BDRB) ........................................................................... 781 20.2.10 Break Data Mask Register B (BDMRB) .............................................................. 782 20.2.11 Break Bus Cycle Register B (BBRB)................................................................... 783 20.2.12 Break Control Register (BRCR)........................................................................... 783 20.3 Operation........................................................................................................................... 785 20.3.1 Explanation of Terms Relating to Accesses ......................................................... 785 20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 786 20.3.3 User Break Operation Sequence........................................................................... 787 20.3.4 Instruction Access Cycle Break ........................................................................... 788 20.3.5 Operand Access Cycle Break ............................................................................... 789 20.3.6 Condition Match Flag Setting .............................................................................. 790 20.3.7 Program Counter (PC) Value Saved .................................................................... 790 20.3.8 Contiguous A and B Settings for Sequential Conditions...................................... 791 20.3.9 Usage Notes ......................................................................................................... 792 20.4 User Break Debug Support Function ................................................................................ 793 20.5 Examples of Use................................................................................................................ 795 20.6 User Break Controller Stop Function ................................................................................ 797 20.6.1 Transition to User Break Controller Stopped State .............................................. 797 20.6.2 Cancelling the User Break Controller Stopped State ........................................... 797 20.6.3 Examples of Stopping and Restarting the User Break Controller ........................ 798 Section 21 Hitachi User Debug Interface (H-UDI).................................................... 799 21.1 Overview ........................................................................................................................... 799 21.1.1 Features ................................................................................................................ 799 Rev. 6.0, 07/02, page xxxii of I 21.1.2 Block Diagram ..................................................................................................... 799 21.1.3 Pin Configuration ................................................................................................. 801 21.1.4 Register Configuration ......................................................................................... 802 21.2 Register Descriptions ........................................................................................................ 803 21.2.1 Instruction Register (SDIR).................................................................................. 803 21.2.2 Data Register (SDDR).......................................................................................... 805 21.2.3 Bypass Register (SDBPR).................................................................................... 805 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only) .......................................... 806 21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only)........................................... 806 21.3 Operation........................................................................................................................... 810 21.3.1 TAP Control ......................................................................................................... 810 21.3.2 H-UDI Reset......................................................................................................... 811 21.3.3 H-UDI Interrupt ................................................................................................... 811 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only). 812 21.4 Usage Notes....................................................................................................................... 812 Section 22 Electrical Characteristics.............................................................................. 813 22.1 Absolute Maximum Ratings.............................................................................................. 813 22.2 DC Characteristics............................................................................................................. 814 22.3 AC Characteristics............................................................................................................. 842 22.3.1 Clock and Control Signal Timing ........................................................................ 844 22.3.2 Control Signal Timing.......................................................................................... 868 22.3.3 Bus Timing........................................................................................................... 871 22.3.4 Peripheral Module Signal Timing ........................................................................ 924 22.3.5 AC Characteristic Test Conditions....................................................................... 934 22.3.6 Delay Time Variation Due to Load Capacitance.................................................. 935 Appendix A Address List.................................................................................................. 937 Appendix B Package Dimensions .................................................................................. 943 Appendix C Mode Pin Settings....................................................................................... 947 Appendix D &.,25(1% Pin Configuration ............................................................... 949 Appendix E Pin Functions................................................................................................ 951 E.1 E.2 Pin States ........................................................................................................................... 951 Handling of Unused Pins................................................................................................... 954 Appendix F Synchronous DRAM Address Multiplexing Tables........................ 955 Appendix G Prefetching of Instructions and its Side Effects ................................. 977 Rev. 6.0, 07/02, page xxxiii of I Appendix H Power-On and Power-Off Procedures................................................... 978 Appendix I Product Code Lineup ................................................................................. 979 Index........................................................................................................................................... 981 Figures Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Figure 3.16 Figure 3.17 Figure 3.18 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Block Diagram of SH7750 Series Functions.................................................... 9 Pin Arrangement (256-Pin BGA)..................................................................... 10 Pin Arrangement (208-Pin QFP) ...................................................................... 11 Pin Arrangement (264-Pin CSP) ...................................................................... 12 Data Formats .................................................................................................... 41 CPU Register Configuration in Each Processor Mode..................................... 44 General Registers ............................................................................................. 46 Floating-Point Registers ................................................................................... 48 Data Formats In Memory ................................................................................. 53 Processor State Transitions .............................................................................. 55 Role of the MMU ............................................................................................. 59 MMU-Related Registers................................................................................... 61 Physical Address Space (MMUCR.AT = 0) .................................................... 65 P4 Area............................................................................................................. 66 External Memory Space ................................................................................... 67 Virtual Address Space (MMUCR.AT = 1)....................................................... 68 UTLB Configuration ........................................................................................ 71 Relationship between Page Size and Address Format...................................... 72 ITLB Configuration.......................................................................................... 75 Flowchart of Memory Access Using UTLB..................................................... 76 Flowchart of Memory Access Using ITLB ...................................................... 77 Operation of LDTLB Instruction ..................................................................... 79 Memory-Mapped ITLB Address Array............................................................ 88 Memory-Mapped ITLB Data Array 1 .............................................................. 89 Memory-Mapped ITLB Data Array 2 .............................................................. 90 Memory-Mapped UTLB Address Array .......................................................... 91 Memory-Mapped UTLB Data Array 1............................................................. 92 Memory-Mapped UTLB Data Array 2............................................................. 93 Cache and Store Queue Control Registers ....................................................... 97 Configuration of Operand Cache(SH7750, SH7750S)..................................... 100 Configuration of Operand Cache (SH7750R) .................................................. 101 Configuration of Write-Back Buffer ................................................................ 105 Configuration of Write-Through Buffer........................................................... 105 Configuration of Instruction Cache (SH7750, SH7750S) ................................ 109 Configuration of Instruction Cache (SH7750R)............................................... 110 Rev. 6.0, 07/02, page xxxiv of I Figure 4.8 Figure 4.9 Figure 4.10 Figure 4.11 Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Figure 4.16 Figure 5.1 Figure 5.2 Figure 5.3 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 8.1 Figure 8.2 Figure 8.3 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 Figure 10.1 (1) Figure 10.1 (2) Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 11.1 Figure 11.2 Figure 11.3 Memory-Mapped IC Address Array ................................................................ 113 Memory-Mapped IC Data Array ...................................................................... 114 Memory-Mapped OC Address Array............................................................... 115 Memory-Mapped OC Data Array .................................................................... 116 Memory-Mapped IC Address Array ................................................................ 118 Memory-Mapped IC Data Array ...................................................................... 119 Memory-Mapped OC Address Array............................................................... 120 Memory-Mapped OC Data Array .................................................................... 121 Store Queue Configuration............................................................................... 122 Register Bit Configurations.............................................................................. 128 Instruction Execution and Exception Handling................................................ 133 Example of General Exception Acceptance Order........................................... 134 Format of Single-Precision Floating-Point Number......................................... 161 Format of Double-Precision Floating-Point Number ....................................... 162 Single-Precision NaN Bit Pattern ..................................................................... 164 Floating-Point Registers ................................................................................... 166 Basic Pipelines ................................................................................................. 194 Instruction Execution Patterns.......................................................................... 195 Examples of Pipelined Execution..................................................................... 207 STATUS Output in Power-On Reset ............................................................... 237 STATUS Output in Manual Reset.................................................................... 237 STATUS Output in Standby Interrupt Sequence......................................... 238 STATUS Output in Standby Power-On Reset Sequence ............................ 238 STATUS Output in Standby Manual Reset Sequence................................. 239 STATUS Output in Sleep Interrupt Sequence............................................. 240 STATUS Output in Sleep Power-On Reset Sequence................................. 240 STATUS Output in Sleep Manual Reset Sequence..................................... 241 STATUS Output in Deep Sleep Interrupt Sequence ................................... 242 STATUS Output in Deep Sleep Power-On Reset Sequence ....................... 242 STATUS Output in Deep Sleep Manual Reset Sequence ........................... 243 Hardware Standby Mode Timing (When CA = Low in Normal Operation).... 244 Hardware Standby Mode Timing (When CA = Low in WDT Operation) ....... 245 Timing When Power Other than VDD-RTC is Off.......................................... 246 Timing When VDD-RTC Power is Off On................................................. 246 Block Diagram of CPG (SH7750, SH7750S) .................................................. 249 Block Diagram of CPG (SH7750R) ................................................................. 250 Block Diagram of WDT ................................................................................... 259 Writing to WTCNT and WTCSR..................................................................... 263 Points for Attention when Using Crystal Resonator......................................... 265 Points for Attention when Using PLL Oscillator Circuit ................................. 266 Block Diagram of RTC .................................................................................... 268 Examples of Time Setting Procedures ............................................................. 285 Examples of Time Reading Procedures ........................................................... 287 Rev. 6.0, 07/02, page xxxv of I Figure 11.4 Figure 11.5 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Figure 13.10 Figure 13.11 Figure 13.12 Figure 13.13 Figure 13.14 Figure 13.15 Figure 13.16 Figure 13.17 Figure 13.18 Figure 13.19 Figure 13.20 Figure 13.21 Figure 13.22 (1) Figure 13.22 (2) Figure 13.22 (3) Figure 13.22 (4) Figure 13.23 Figure 13.24 Figure 13.25 Example of Use of Alarm Function.................................................................. 288 Example of Crystal Oscillator Circuit Connection........................................... 290 Block Diagram of TMU ................................................................................... 292 Example of Count Operation Setting Procedure .............................................. 305 TCNT Auto-Reload Operation ......................................................................... 305 Count Timing when Operating on Internal Clock ............................................ 306 Count Timing when Operating on External Clock ........................................... 306 Count Timing when Operating on On-Chip RTC Output Clock...................... 307 Operation Timing when Using Input Capture Function ................................... 308 Block Diagram of BSC..................................................................................... 313 Correspondence between Virtual Address Space and External Memory Space ................................................................................................................ 319 External Memory Space Allocation ................................................................. 321 Example of 5'< Sampling Timing at which BCR4 is Set (Two Wait Cycles are Inserted by WCR2)....................................................... 338 Writing to RTCSR, RTCNT, RTCOR, and RFCR........................................... 370 Basic Timing of SRAM Interface..................................................................... 388 Example of 64-Bit Data Width SRAM Connection ......................................... 389 Example of 32-Bit Data Width SRAM Connection ......................................... 390 Example of 16-Bit Data Width SRAM Connection ......................................... 391 Example of 8-Bit Data Width SRAM Connection ........................................... 392 SRAM Interface Wait Timing (Software Wait Only) ...................................... 393 SRAM Interface Wait State Timing (Wait State Insertion by 5'< Signal) .... 394 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) 395 Example of DRAM Connection (64-Bit Data Width, Area 3) ......................... 396 Example of DRAM Connection (32-Bit Data Width, Area 3) ......................... 397 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) .............. 398 Basic DRAM Access Timing ........................................................................... 400 DRAM Wait State Timing ............................................................................... 401 DRAM Burst Access Timing ........................................................................... 402 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)...................... 403 Burst Access Timing in DRAM EDO Mode.................................................... 404 DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0) ............................................................ 405 DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) ............................................................ 406 DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0) ................................................................... 407 DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) ................................................................... 408 CAS-Before-RAS Refresh Operation............................................................... 409 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)........ 410 DRAM Self-Refresh Cycle Timing.................................................................. 412 Rev. 6.0, 07/02, page xxxvi of I Figure 13.26 Figure 13.27 Figure 13.28 Figure 13.29 Figure 13.30 Figure 13.31 Figure 13.32 Figure 13.33 Figure 13.34 Figure 13.35 Figure 13.36 Figure 13.37 Figure 13.38 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) .... 414 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .... 415 Basic Timing for Synchronous DRAM Burst Read ......................................... 417 Basic Timing for Synchronous DRAM Single Read........................................ 418 Basic Timing for Synchronous DRAM Burst Write ........................................ 419 Basic Timing for Synchronous DRAM Single Write....................................... 421 Burst Read Timing ........................................................................................... 423 Burst Read Timing (RAS Down, Same Row Address) .................................... 424 Burst Read Timing (RAS Down, Different Row Addresses)........................... 425 Burst Write Timing .......................................................................................... 426 Burst Write Timing (Same Row Address) ....................................................... 427 Burst Write Timing (Different Row Addresses) .............................................. 428 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle............................................................................. 430 Figure 13.39 Auto-Refresh Operation ................................................................................... 432 Figure 13.40 Synchronous DRAM Auto-Refresh Timing..................................................... 432 Figure 13.41 Synchronous DRAM Self-Refresh Timing ...................................................... 434 Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) ......................................... 436 Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) ...................... 437 Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4)............ 438 Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM................................... 440 Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width (256 Mbits)....................................................................................................... 441 Figure 13.46 Burst ROM Basic Access Timing .................................................................... 442 Figure 13.47 Burst ROM Wait Access Timing ..................................................................... 443 Figure 13.48 Burst ROM Wait Access Timing ..................................................................... 444 Figure 13.49 Example of PCMCIA Interface ........................................................................ 448 Figure 13.50 Basic Timing for PCMCIA Memory Card Interface........................................ 449 Figure 13.51 Wait Timing for PCMCIA Memory Card Interface ......................................... 450 Figure 13.52 PCMCIA Space Allocation .............................................................................. 451 Figure 13.53 Basic Timing for PCMCIA I/O Card Interface ................................................ 452 Figure 13.54 Wait Timing for PCMCIA I/O Card Interface ................................................. 453 Figure 13.55 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ........................ 454 Figure 13.56 Example of 64-Bit Data Width MPX Connection............................................ 456 Figure 13.57 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits) .......... 457 Figure 13.58 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) ..... 458 Figure 13.59 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits)........................ 459 Figure 13.60 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) .... 460 Rev. 6.0, 07/02, page xxxvii of I Figure 13.61 Figure 13.62 Figure 13.63 Figure 13.64 Figure 13.65 Figure 13.66 Figure 13.67 Figure 13.68 Figure 13.69 Figure 13.70 Figure 13.71 Figure 13.72 Figure 13.73 Figure 13.74 Figure 13.75 Figure 13.76 Figure 13.77 Figure 13.78 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 461 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 462 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 463 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 464 MPX Interface Timing 1 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) .......................................................................... 465 MPX Interface Timing 2 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) .......................................................................... 466 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) .......................................................................... 467 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) .......................................................................... 468 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 469 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 470 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 471 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 472 Example of 64-Bit Data Width Byte Control SRAM....................................... 474 Byte Control SRAM Basic Read Cycle (No Wait) .......................................... 475 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ................. 476 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) ........................................................ 477 Waits between Access Cycles .......................................................................... 479 Arbitration Sequence........................................................................................ 482 Rev. 6.0, 07/02, page xxxviii of I Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Figure 14.9 Figure 14.10 Figure 14.11 Figure 14.12 Figure 14.13 Figure 14.14 Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Figure 14.25 Figure 14.26 Figure 14.27 Block Diagram of DMAC ................................................................................ 492 DMAC Transfer Flowchart .............................................................................. 511 Round Robin Mode .......................................................................................... 516 Example of Changes in Priority Order in Round Robin Mode......................... 517 Data Flow in Single Address Mode.................................................................. 519 DMA Transfer Timing in Single Address Mode.............................................. 520 Operation in Dual Address Mode..................................................................... 521 Example of Transfer Timing in Dual Address Mode ....................................... 522 Example of DMA Transfer in Cycle Steal Mode ............................................. 523 Example of DMA Transfer in Burst Mode....................................................... 523 Bus Handling with Two DMAC Channels Operating...................................... 527 Dual Address Mode/Cycle Steal Mode External Bus External Bus/ '5(4 (Level Detection), DACK (Read Cycle)............................................... 530 Dual Address Mode/Cycle Steal Mode External Bus External Bus/ '5(4 (Edge Detection), DACK (Read Cycle) ............................................... 531 Dual Address Mode/Burst Mode External Bus External Bus/ '5(4 (Level Detection), DACK (Read Cycle)............................................... 532 Dual Address Mode/Burst Mode External Bus External Bus/ '5(4 (Edge Detection), DACK (Read Cycle) ............................................... 533 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) External Bus ..................................................................................................... 534 Dual Address Mode/Cycle Steal Mode External Bus On-Chip SCI (Level Detection).............................................................................................. 535 Single Address Mode/Cycle Steal Mode External Bus External Bus/ '5(4 (Level Detection).................................................................................. 536 Single Address Mode/Cycle Steal Mode External Bus External Bus/ '5(4 (Edge Detection)................................................................................... 537 Single Address Mode/Burst Mode External Bus External Bus/ '5(4 (Level Detection).................................................................................. 538 Single Address Mode/Burst Mode External Bus External Bus/ '5(4 (Edge Detection)................................................................................... 539 Single Address Mode/Burst Mode External Bus External Bus/ '5(4 (Level Detection)/32-Byte Block Transfer (Bus Width: 64 Bits, SDRAM: Row Hit Write)............................................... 540 On-Demand Transfer Mode Block Diagram .................................................... 545 System Configuration in On-Demand Data Transfer Mode............................. 547 Data Transfer Request Format ......................................................................... 548 Single Address Mode: Synchronous DRAM External Device Longword Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01, CAS latency = 3, TPC[2:0] = 001)....................................................................... 551 Single Address Mode: External Device Synchronous DRAM Longword Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01, TRWL[2:0] = 101, TPC[2:0] = 001).................................................................... 552 Rev. 6.0, 07/02, page xxxix of I Figure 14.28 Figure 14.29 Figure 14.30 Figure 14.31 Figure 14.32 Figure 14.33 Figure 14.34 Figure 14.35 Figure 14.36 Figure 14.37 Figure 14.38 Figure 14.39 Figure 14.40 Figure 14.41 Figure 14.42 Figure 14.43 Figure 14.44 Figure 14.45 Figure 14.46 Figure 14.47 Figure 14.48 Figure 14.49 Figure 14.50 Figure 14.51 Figure 14.52 Figure 14.53 Dual Address Mode/Synchronous DRAM SRAM Longword Transfer...... 553 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer..................................... 554 Single Address Mode/Burst Mode/External Device External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer..................................... 554 Single Address Mode/Burst Mode/External Bus External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer ............................................... 555 Single Address Mode/Burst Mode/External Device External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer ............................................... 556 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) 557 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer)........................................................................................................... 558 Read from Synchronous DRAM Precharge Bank ............................................ 559 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ................ 559 Read from Synchronous DRAM (Row Hit) ..................................................... 560 Write to Synchronous DRAM Precharge Bank................................................ 560 Write to Synchronous DRAM Non-Precharge Bank (Row Miss).................... 561 Write to Synchronous DRAM (Row Hit)......................................................... 561 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer..................................... 562 DDT Mode Setting ........................................................................................... 563 Single Address Mode/Burst Mode/Edge Detection/ External Device External Bus Data Transfer .............................................................................. 563 Single Address Mode/Burst Mode/Level Detection/ External Bus External Device Data Transfer ......................................................................... 564 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus External Device Data Transfer............................. 564 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device External Bus Data Transfer............................. 565 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1-3 Using Data Bus ........................................................ 566 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus ................................................................................... 567 Single Address Mode/Burst Mode/External Bus External Device Data Transfer/Direct Data Transfer Request to Channel 2 ....................................... 568 Single Address Mode/Burst Mode/External Device External Bus Data Transfer/Direct Data Transfer Request to Channel 2 ....................................... 569 Single Address Mode/Burst Mode/External Bus External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 570 Single Address Mode/Burst Mode/External Device External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 571 Block Diagram of the DMAC .......................................................................... 574 Rev. 6.0, 07/02, page xl of I Figure 14.54 Figure 14.55 Figure 14.56 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Figure 15.8 Figure 15.9 Figure 15.10 Figure 15.10 Figure 15.11 Figure 15.12 Figure 15.13 Figure 15.14 Figure 15.15 Figure 15.15 Figure 15.16 Figure 15.17 Figure 15.18 Figure 15.19 Figure 15.20 Figure 15.21 Figure 15.21 Figure 15.22 Figure 15.23 Figure 15.24 Figure 15.25 Figure 16.1 Figure 16.2 Figure 16.3 DTR Format (Transfer Request Format) (SH7750R)....................................... 584 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ....................... 589 Single Address Mode/Burst Mode/External Bus External Device/ 32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 .................. 590 Block Diagram of SCI...................................................................................... 595 MD0/SCK Pin .................................................................................................. 611 MD7/TxD Pin................................................................................................... 612 RxD Pin ............................................................................................................ 6 12 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ...................................................................................... 623 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode)...................................................................................... 625 Sample SCI Initialization Flowchart ................................................................ 626 Sample Serial Transmission Flowchart ............................................................ 627 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ............................................. 629 Sample Serial Reception Flowchart (1)............................................................ 630 Sample Serial Reception Flowchart (2)............................................................ 631 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ............................................. 633 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ..................................... 635 Sample Multiprocessor Serial Transmission Flowchart ................................... 636 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).................................................................... 638 Sample Multiprocessor Serial Reception Flowchart (1)................................... 639 Sample Multiprocessor Serial Reception Flowchart (2)................................... 640 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).................................................................... 641 Data Format in Synchronous Communication ................................................. 642 Sample SCI Initialization Flowchart ................................................................ 644 Sample Serial Transmission Flowchart ............................................................ 645 Example of SCI Transmit Operation................................................................ 646 Sample Serial Reception Flowchart (1)............................................................ 647 Sample Serial Reception Flowchart (2)............................................................ 648 Example of SCI Receive Operation ................................................................. 649 Sample Flowchart for Serial Data Transmission and Reception ...................... 650 Receive Data Sampling Timing in Asynchronous Mode ................................. 654 Example of Synchronous Transmission by DMAC ......................................... 655 Block Diagram of SCIF.................................................................................... 659 MD8/5765 Pin................................................................................................. 681 &765 Pin .......................................................................................................... 682 Rev. 6.0, 07/02, page xli of I Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Figure 16.9 Figure 16.10 Figure 16.10 Figure 16.11 Figure 16.12 Figure 16.13 Figure 16.14 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6 Figure 17.7 Figure 17.8 Figure 17.9 Figure 17.10 Figure 17.11 Figure 17.12 Figure 17.13 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 Figure 19.1 Figure 19.2 Figure 19.3 Figure 20.1 Figure 20.2 Figure 21.1 Figure 21.2 MD1/TxD2 Pin................................................................................................. 683 MD2/RxD2 Pin ................................................................................................ 683 Sample SCIF Initialization Flowchart .............................................................. 689 Sample Serial Transmission Flowchart ............................................................ 690 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit).................................................................................................... 692 Example of Operation Using Modem Control (&765)..................................... 692 Sample Serial Reception Flowchart (1)............................................................ 693 Sample Serial Reception Flowchart (2)............................................................ 694 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit).................................................................................................... 696 Example of Operation Using Modem Control (5765)..................................... 696 Receive Data Sampling Timing in Asynchronous Mode ................................. 699 Overrun Error Flag ........................................................................................... 701 Block Diagram of Smart Card Interface........................................................... 704 Schematic Diagram of Smart Card Interface Pin Connections......................... 711 Smart Card Interface Data Format ................................................................... 712 TEND Generation Timing................................................................................ 714 Sample Start Character Waveforms ................................................................. 715 Difference in Clock Output According to GM Bit Setting............................... 717 Sample Initialization Flowchart ....................................................................... 719 Sample Transmission Processing Flowchart .................................................... 721 Sample Reception Processing Flowchart ......................................................... 723 Receive Data Sampling Timing in Smart Card Mode ...................................... 725 Retransfer Operation in SCI Receive Mode ..................................................... 726 Retransfer Operation in SCI Transmit Mode ................................................... 727 Procedure for Stopping and Restarting the Clock ............................................ 728 16-Bit Port........................................................................................................ 732 4-Bit Port.......................................................................................................... 733 MD0/SCK Pin .................................................................................................. 734 MD7/TxD Pin................................................................................................... 735 RxD Pin ............................................................................................................ 735 MD1/TxD2 Pin................................................................................................. 736 MD2/RxD2 Pin ................................................................................................ 736 &765 Pin .......................................................................................................... 737 MD8/5765 Pin................................................................................................. 738 Block Diagram of INTC................................................................................... 752 Example of IRL Interrupt Connection.............................................................. 755 Interrupt Operation Flowchart.......................................................................... 769 Block Diagram of User Break Controller......................................................... 774 User Break Debug Support Function Flowchart .............................................. 794 Block Diagram of H-UDI Circuit..................................................................... 800 TAP Control State Transition Diagram ............................................................ 810 Rev. 6.0, 07/02, page xlii of I Figure 21.3 Figure 22.1 Figure 22.2(1) Figure 22.2(2) Figure 22.3 Figure 22.4 Figure 22.5 Figure 22.6 Figure 22.7 Figure 22.8 Figure 22.9 Figure 22.10 Figure 22.11 Figure 22.12 Figure 22.13 Figure 22.14 Figure 22.15 Figure 22.16 Figure 22.17 Figure 22.18 Figure 22.19 Figure 22.20 Figure 22.21 Figure 22.22 Figure 22.23 Figure 22.24 Figure 22.25 Figure 22.26 Figure 22.27 Figure 22.28 Figure 22.29 H-UDI Reset..................................................................................................... 811 EXTAL Clock Input Timing ............................................................................ 862 CKIO Clock Output Timing............................................................................. 862 CKIO Clock Output Timing............................................................................. 862 Power-On Oscillation Settling Time ................................................................ 863 Standby Return Oscillation Settling Time (Return by 5(6(7) ....................... 863 Power-On Oscillation Settling Time ................................................................ 864 Standby Return Oscillation Settling Time (Return by 5(6(7) ....................... 864 Standby Return Oscillation Settling Time (Return by NMI)............................ 865 Standby Return Oscillation Settling Time (Return by ,5/6-,5/3)................. 865 PLL Synchronization Settling Time in Case of 5(6(7 or NMI Interrupt....... 866 PLL Synchronization Settling Time in Case of IRL Interrupt.......................... 866 Manual Reset Input Timing.............................................................................. 867 Mode Input Timing .......................................................................................... 867 Control Signal Timing...................................................................................... 870 Pin Drive Timing for Standby Mode................................................................ 870 SRAM Bus Cycle: Basic Bus Cycle (No Wait)................................................ 877 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ................................ 878 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)879 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) ........................................................................... 880 Burst ROM Bus Cycle (No Wait) .................................................................... 881 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait)............................................................... 882 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) ........................................................................................... 883 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ................... 884 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) ........................... 885 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) ............................ 886 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD[1:0] = 01, CAS Latency = 3)............ 887 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3)............................................................................................. 888 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency = 3) ................................................... 889 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010).......................... 890 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) ........................... 891 Rev. 6.0, 07/02, page xliii of I Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010) ........ 892 Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) ........................................................................................... 893 Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL[2:0] = 010) ................................................ 894 Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (TPC[2:0] = 001)......................... 895 Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001).................. 896 Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001)...................................... 897 Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL)...................................... 898 Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET)......................................... 899 Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010 .................................... 900 Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ............................................................................................... 901 Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ............................................................................................... 902 Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) ............................................................................................... 903 Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) ....................................... 904 Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 905 Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 906 Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001)................................................................... 907 Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001)................................................................... 908 Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)........... 909 Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 910 Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) ....................................... 911 Rev. 6.0, 07/02, page xliv of I Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000, TRC[2:0] = 001) ............................................................... 912 Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001) ............................................................... 913 Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) ............................ 914 Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait............................................................................................ 915 Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait............................................................................................ 916 Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing) ........................................................................ 917 Figure 22.55 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait)..................................... 918 Figure 22.56 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait)..................................... 919 Figure 22.57 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait) (2) 1st Data (One Internal Wait), 2nd to 4th Data (One Internal Wait + One External Wait)........................................................................................... 920 Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait Control) ..................................................................................... 921 Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait)...................... 922 Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =01) .. 923 Figure 22.61 TCLK Input Timing ......................................................................................... 930 Figure 22.62 RTC Oscillation Settling Time at Power-On.................................................... 930 Figure 22.63 SCK Input Clock Timing ................................................................................. 930 Figure 22.64 SCI I/O Synchronous Mode Clock Timing ...................................................... 931 Figure 22.65 I/O Port Input/Output Timing........................................................................... 931 Figure 22.66(a) '5(4/DRAK Timing...................................................................................... 931 Figure 22.66(b) '%5(4/75 Input Timing and %$9/ Output Timing..................................... 932 Rev. 6.0, 07/02, page xlv of I Figure 22.67 Figure 22.68 Figure 22.69 Figure 22.70 Figure 22.71 Figure 22.72 Figure 22.73 Figure B.1 Figure B.2 Figure B.3 Figure B.4 Figure D.1 Figure G.1 Figure H.1 TCK Input Timing............................................................................................ 932 5(6(7 Hold Timing ........................................................................................ 932 H-UDI Data Transfer Timing........................................................................... 933 Pin Break Timing ............................................................................................. 933 NMI Input Timing............................................................................................ 933 Output Load Circuit ......................................................................................... 934 Load Capacitance vs. Delay Time.................................................................... 935 Package Dimensions (256-Pin BGA) (SH7750 and SH7750S) ....................... 943 Package Dimensions (256-Pin BGA) (SH7750R Only)................................... 944 Package Dimensions (208-Pin QFP) ................................................................ 945 Package Dimensions (264-Pin CSP) ................................................................ 946 &.,25(1% Pin Configuration ........................................................................ 949 Instruction Prefetch .......................................................................................... 977 Power-On and Power-Off Procedures .............................................................. 978 Tables Table 1.1 Table 1.2 Table 1.3 Table 1.4 Table 2.1 Table 3.1 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 5.1 Table 5.2 Table 5.3 Table 6.1 Table 6.2 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Table 7.10 Table 7.11 SH7750 Series Features ..................................................................................... 1 Pin Functions...................................................................................................... 13 Pin Functions...................................................................................................... 23 Pin Functions...................................................................................................... 31 Initial Register Values ........................................................................................ 43 MMU Registers .................................................................................................. 60 Cache Features (SH7750, SH7750S) ................................................................. 95 Cache Features (SH7750R) ................................................................................ 95 Features of Store Queues.................................................................................... 96 Cache Control Registers..................................................................................... 96 Exception-Related Registers .............................................................................. 127 Exceptions .......................................................................................................... 130 Types of Reset.................................................................................................... 137 Floating-Point Number Formats and Parameters ............................................... 162 Floating-Point Ranges ........................................................................................ 163 Addressing Modes and Effective Addresses ...................................................... 175 Notation Used in Instruction List ....................................................................... 179 Fixed-Point Transfer Instructions....................................................................... 180 Arithmetic Operation Instructions...................................................................... 182 Logic Operation Instructions.............................................................................. 184 Shift Instructions ................................................................................................ 185 Branch Instructions ............................................................................................ 186 System Control Instructions ............................................................................... 187 Floating-Point Single-Precision Instructions...................................................... 189 Floating-Point Double-Precision Instructions .................................................... 190 Floating-Point Control Instructions.................................................................... 190 Rev. 6.0, 07/02, page xlvi of I Table 7.12 Table 8.1 Table 8.2 Table 8.3 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 10.1 Table 10.2 Table 10.3 (1) Table 10.3 (2) Table 10.4 Table 10.5 Table 11.1 Table 11.2 Table 11.3 Table 12.1 Table 12.2 Table 12.3 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 13.7 (1) Table 13.7 (2) Table 13.8 Table 13.9 Table 13.10 Table 13.11 (1) Table 13.11 (2) Table 13.12 Table 13.13 Table 13.14 Table 13.15 Table 13.16 Table 13.17 Table 13.18 Table 14.1 Floating-Point Graphics Acceleration Instructions ............................................ 191 Instruction Groups.............................................................................................. 200 Parallel-Executability ......................................................................................... 204 Execution Cycles................................................................................................ 211 Status of CPU and Peripheral Modules in Power-Down Modes ........................ 222 Power-Down Mode Registers ............................................................................ 223 Power-Down Mode Pins .................................................................................... 223 State of Registers in Standby Mode ................................................................... 231 CPG Pins ............................................................................................................ 252 CPG Register...................................................................................................... 252 Clock Operating Modes (SH7750, SH7750S).................................................... 253 Clock Operating Modes (SH7750R) .................................................................. 253 FRQCR Settings and Internal Clock Frequencies .............................................. 254 WDT Registers................................................................................................... 260 RTC Pins ............................................................................................................ 269 RTC Registers .................................................................................................... 269 Crystal Oscillator Circuit Constants (Recommended Values) ........................... 289 TMU Pins ........................................................................................................... 292 TMU Registers ................................................................................................... 293 TMU Interrupt Sources ...................................................................................... 309 BSC Pins ............................................................................................................ 314 BSC Registers .................................................................................................... 318 External Memory Space Map............................................................................. 320 PCMCIA Interface Features............................................................................... 322 PCMCIA Support Interfaces .............................................................................. 323 MPX Interface is Selected (Areas 0 to 6) ........................................................... 350 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 372 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 373 32-Bit External Device/Big-Endian Access and Data Alignment ...................... 374 16-Bit External Device/Big-Endian Access and Data Alignment ...................... 375 8-Bit External Device/Big-Endian Access and Data Alignment ........................ 376 64-Bit External Device/Little-Endian Access and Data Alignment ................... 377 64-Bit External Device/Little-Endian Access and Data Alignment ................... 378 32-Bit External Device/Little-Endian Access and Data Alignment ................... 379 16-Bit External Device/Little-Endian Access and Data Alignment ................... 380 8-Bit External Device/Little-Endian Access and Data Alignment ..................... 381 Relationship between AMXEXT and AMX2-0 Bits and Address Multiplexing......................................................................................... 399 Example of Correspondence between SH7750 Series and Synchronous DRAM Address Pins (64-Bit Bus Width, AMX2-AMX0 = 011, AMXEXT = 0) ......... 416 Cycles for which Pipeline Access is Possible .................................................... 431 Relationship between Address and CE when Using PCMCIA Interface ........... 446 DMAC Pins ........................................................................................................ 493 Rev. 6.0, 07/02, page xlvii of I Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 14.15 Table 14.16 Table 14.17 Table 14.18 Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 15.6 Table 15.7 Table 15.8 Table 15.9 Table 15.10 Table 15.11 Table 15.12 Table 15.13 Table 16.1 Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Table 17.1 Table 17.2 Table 17.3 Table 17.4 Table 17.5 DMAC Pins in DDT Mode ................................................................................ 494 DMAC Registers ................................................................................................ 494 Selecting External Request Mode with RS Bits ................................................. 513 Selecting On-Chip Peripheral Module Request Mode with RS Bits .................. 514 Supported DMA Transfers ................................................................................. 518 Relationship between DMA Transfer Type, Request Mode, and Bus Mode ..... 524 External Request Transfer Sources and Destinations in Normal Mode ............. 525 External Request Transfer Sources and Destinations in DDT Mode ................. 526 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings ............................................ 544 DMAC Pins ........................................................................................................ 575 DMAC Pins in DDT Mode ................................................................................ 576 Register Configuration ....................................................................................... 577 Channel Selection by DTR Format (DMAOR.DBL = 1)................................... 584 Notification of Transfer Channel in Eight-Channel DDT Mode........................ 587 Function of %$9/ ............................................................................................. 587 DTR Format for Clearing Request Queues ........................................................ 588 DMAC Interrupt-Request Codes........................................................................ 589 SCI Pins.............................................................................................................. 596 SCI Registers...................................................................................................... 596 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ............. 615 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode................ 618 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)........................................................................................ 619 Maximum Bit Rate with External Clock Input (Asynchronous Mode).............. 620 Maximum Bit Rate with External Clock Input (Synchronous Mode) ................ 620 SCSMR1 Settings for Serial Transfer Format Selection .................................... 622 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection...................... 622 Serial Transfer Formats (Asynchronous Mode) ................................................. 624 Receive Error Conditions ................................................................................... 632 SCI Interrupt Sources ......................................................................................... 651 SCSSR1 Status Flags and Transfer of Receive Data.......................................... 652 SCIF Pins ........................................................................................................... 660 SCIF Registers.................................................................................................... 661 SCSMR2 Settings for Serial Transfer Format Selection .................................... 685 SCSCR2 Settings for SCIF Clock Source Selection .......................................... 686 Serial Transmit/Receive Formats ....................................................................... 687 SCIF Interrupt Sources....................................................................................... 697 Smart Card Interface Pins .................................................................................. 705 Smart Card Interface Registers........................................................................... 705 Smart Card Interface Register Settings .............................................................. 713 Values of n and Corresponding CKS1 and CKS0 Settings ................................ 715 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)... 716 Rev. 6.0, 07/02, page xlviii of I Table 17.6 Table 17.7 Table 17.8 Table 17.9 Table 18.1 Table 18.2 Table 18.3 Table 18.4 Table 19.1 Table 19.2 Table 19.3 Table 19.4 Table 19.5 Table 19.6 Table 19.7 Table 19.8 Table 19.9 Table 20.1 Table 21.1 Table 21.2 Table 21.3 Table 21.3 Table 21.3 Table 22.1 Table 22.2 Table 22.3 Table 22.4 Table 22.5 Table 22.6 Table 22.7 Table 22.8 Table 22.9 Table 22.10 Table 22.11 Table 22.12 Table 22.13 Table 22.14 Table 22.15 Table 22.16 Table 22.17 Table 22.18 Table 22.19 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) ................ 716 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ........ 716 Register Settings and SCK Pin State .................................................................. 717 Smart Card Mode Operating States and Interrupt Sources................................. 724 20-Bit General-Purpose I/O Port Pins ................................................................ 739 SCI I/O Port Pins................................................................................................ 740 SCIF I/O Port Pins.............................................................................................. 740 I/O Port Registers ............................................................................................... 741 INTC Pins........................................................................................................... 753 INTC Registers................................................................................................... 753 ,5/6-,5/3 Pins and Interrupt Levels................................................................ 756 SH7750 ,5/6-,5/3 Pins and Interrupt Levels (When IRLM = 1).................... 757 Interrupt Exception Handling Sources and Priority Order ................................. 759 Interrupt Request Sources and IPRA-IPRD Registers....................................... 762 Interrupt Request Sources and the Bits of the INTPRI00 Register .................... 765 Bit Assignments ................................................................................................. 767 Interrupt Response Time .................................................................................... 771 UBC Registers.................................................................................................... 775 H-UDI Pins......................................................................................................... 801 H-UDI Registers................................................................................................. 802 Configuration of the Boundary Scan Register (1) .............................................. 807 Configuration of the Boundary Scan Register (2) .............................................. 808 Configuration of the Boundary Scan Register (3) .............................................. 809 Absolute Maximum Ratings............................................................................... 813 DC Characteristics (HD6417750RBP240)......................................................... 814 DC Characteristics (HD6417750RF240) ........................................................... 816 DC Characteristics (HD6417750RBP200)......................................................... 818 DC Characteristics (HD6417750RF200) ........................................................... 820 DC Characteristics (HD6417750SBP200) ......................................................... 822 DC Characteristics (HD6417750SF200)............................................................ 824 DC Characteristics (HD6417750BP200M) ........................................................ 826 DC Characteristics (HD6417750SF167)............................................................ 828 DC Characteristics (HD6417750SF167I)........................................................... 830 DC Characteristics (HD6417750F167) .............................................................. 832 DC Characteristics (HD6417750F167I)............................................................. 834 DC Characteristics (HD6417750SVF133) ......................................................... 836 DC Characteristics (HD6417750SVBT133) ...................................................... 838 DC Characteristics (HD6417750VF128) ........................................................... 840 Permissible Output Currents .............................................................................. 841 Clock Timing (HD6417750RBP240)................................................................. 842 Clock Timing (HD6417750RF240) ................................................................... 842 Clock Timing (HD6417750BP200M, HD6417750SBP200, HD6417750RBP200) ......................................................................................... 842 Rev. 6.0, 07/02, page xlix of I Table 22.20 Table 22.21 Table 22.22 Table 22.23 Table 22.24 Table 22.25 Table 22.26 Table 22.27 Table 22.28 Table 22.29 Table 22.30 Table 22.31 Table 22.32 Table 22.33 Table 22.34 Table 22.34 Table 22.35 Table 22.35 Table 22.35 Table 22.36 Table 22.36 Table 22.36 Table A.1 Table E.1 Table I.1 Clock Timing (HD6417750RF200) ................................................................... 842 Clock Timing (HD6417750SF200).................................................................... 842 Clock Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I) ........................................................................................... 843 Clock Timing (HD6417750SVF133, HD6417750SVBT133) ........................... 843 Clock Timing (HD6417750VF128) ................................................................... 843 Clock and Control Signal Timing (HD6417750RBP240).................................. 844 Clock and Control Signal Timing (HD6417750RF240) .................................... 846 Clock and Control Signal Timing (HD6417750RBP200).................................. 848 Clock and Control Signal Timing (HD6417750RF200) .................................... 850 Clock and Control Signal Timing (HD6417750BP200M, HD6417750SBP200).......................................................................................... 852 Clock and Control Signal Timing (HD6417750SF200)..................................... 854 Clock and Control Signal Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I) ........................................................... 856 Clock and Control Signal Timing (HD6417750SVF133, HD6417750SVBT133)....................................................................................... 858 Clock and Control Signal Timing (HD6417750VF128) .................................... 860 Control Signal Timing (1) .................................................................................. 868 Control Signal Timing (2) .................................................................................. 869 Bus Timing (1) ................................................................................................... 871 Bus Timing (2) ................................................................................................... 873 Bus Timing (3) ................................................................................................... 875 Peripheral Module Signal Timing (1) ................................................................ 924 Peripheral Module Signal Timing (2) ................................................................ 926 Peripheral Module Signal Timing (3) ................................................................ 928 Address List ....................................................................................................... 937 Pin States in Reset, Power-Down State, and Bus-Released State ...................... 951 SH7750 Series Product Code Lineup ................................................................. 979 Rev. 6.0, 07/02, page l of I Section 1 Overview 1.1 SH7750 Series (SH7750, SH7750S, SH7750R) Features The SH7750 Series (SH7750, SH7750S, SH7750R) is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The SH7750 and SH7750S have an 8-kbyte instruction cache and a 16-kbyte data cache. The SH7750R has a 16-kbyte instruction cache and a 32-kbyte data cache. The SH7750 Series has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions. The features of the SH7750 Series are summarized in table 1.1. Table 1.1 Item LSI SH7750 Series Features Features * * 1 23 2 Operating frequency: 240 MHz* , 200 MHz, 167 MHz* * , 133 MHz* , 3 128 MHz* Performance 432 MIPS (240 MHz), 360 MIPS (200 MHz), 300 MIPS (167 MHz), 240 MIPS (133 MHz), 230 MIPS (128 MHz) 1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz), 1.2 GFLOPS (167 MHz), 0.9 GFLOPS (133 MHz, 128 MHz) * * * Superscalar architecture: Parallel execution of two instructions Packages: 256-pin BGA, 208-pin QFP, 264-pin CSP* External buses Separate 26-bit address and 64-bit data buses External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency 2 Rev. 6.0, 07/02, page 1 of 986 Table 1.1 Item CPU SH7750 Series Features (cont) Features * * * Original Hitachi SH architecture 32-bit internal data bus General register file: Sixteen 32-bit general registers (and eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers * RISC-type instruction set (upward-compatible with SH Series) Fixed 16-bit instruction length for improved code efficiency Load-store architecture Delayed branch instructions Conditional execution C-based instruction set * * * * * * Superscalar architecture (providing simultaneous execution of two instructions) including FPU Instruction execution time: Maximum 2 instructions/cycle Virtual address space: 4 Gbytes (448-Mbyte external memory space) Space identifier ASIDs: 8 bits, 256 virtual address spaces On-chip multiplier Five-stage pipeline Rev. 6.0, 07/02, page 2 of 986 Table 1.1 Item FPU SH7750 Series Features (cont) Features * * * * * * * * * * * On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 Floating-point registers: 32 bits x 16 words x 2 banks (single-precision x 16 words or double-precision x 8 words) x 2 banks 32-bit CPU-FPU floating-point communication register (FPUL) Supports FMAC (multiply-and-accumulate) instruction Supports FDIV (divide) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution times Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles (double-precision) Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles (double-precision) Note: FMAC is supported for single-precision only. * 3-D graphics instructions (single-precision only): 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 7 cycles (latency) 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency) Rev. 6.0, 07/02, page 3 of 986 Table 1.1 Item SH7750 Series Features (cont) Features * Choice of main clock: SH7750, SH7750S: 1/2, 1, 3, or 6 times EXTAL SH7750R: 1, 6, or 12 times EXTAL * Clock modes: CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock Bus frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock Note: Maximum frequency varies with models. * Power-down modes Sleep mode Standby mode Module standby function * Single-channel watchdog timer 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs) Single virtual mode and multiple virtual memory mode Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte 4-entry fully-associative TLB for instructions 64-entry fully-associative TLB for instructions and operands Supports software-controlled replacement and random-counter replacement algorithm TLB contents can be accessed directly by address mapping Clock pulse generator (CPG) Memory management unit (MMU) * * * * * * * Rev. 6.0, 07/02, page 4 of 986 Table 1.1 Item SH7750 Series Features (cont) Features Instruction cache (IC) 8 kbytes, direct mapping 256 entries, 32-byte block length Normal mode (8-kbyte cache) Index mode * Operand cache (OC) 16 kbytes, direct mapping 512 entries, 32-byte block length Normal mode (16-kbyte cache) Index mode RAM mode (8-kbyte cache + 8-kbyte RAM) Choice of write method (copy-back or write-through) * * * Single-stage copy-back buffer, single-stage write-through buffer Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) Store queue (32 bytes x 2 entries) Instruction cache (IC) 16 kbytes, 2-way set associative 256 entries/way, 32-byte block length Cache-double-mode (16-kbyte cache) Index mode SH7750/SH7750S-compatible mode (8 kbytes, direct mapping) * Operand cache (OC) 32 kbytes, 2-way set associative 512 entries/way, 32-byte block length Cache-double-mode (32-kbyte cache) Index mode RAM mode (16-kbyte cache + 16-kbyte RAM) SH7750/SH7750S-compatible mode (16 kbytes, direct mapping) * * * Single-stage copy-back buffer, single-stage write-through buffer Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) Store queue (32 bytes x 2 entries) Cache memory * [SH7750, SH7750S] Cache memory [SH7750R] * Rev. 6.0, 07/02, page 5 of 986 Table 1.1 Item SH7750 Series Features (cont) Features * * * Five independent external interrupts: NMI, IRL3 to IRL0 15-level encoded external interrupts: IRL3 to IRL0 On-chip peripheral module interrupts: Priority level can be set for each module Supports debugging by means of user break interrupts Two break channels Address, data value, access type, and data size can all be set as break conditions Supports sequential break function Supports external memory access 64/32/16/8-bit external data bus * External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: Bus size (8, 16, 32, or 64 bits) Number of wait cycles (hardware wait function also supported) Connection of DRAM, synchronous DRAM, and burst ROM possible by setting space type Supports fast page mode and DRAM EDO Supports PCMCIA interface Chip select signals (&63 to &69) output for relevant areas * DRAM/synchronous DRAM refresh functions Programmable refresh interval Supports CAS-before-RAS refresh mode and self-refresh mode * * DRAM/synchronous DRAM burst access function Big endian or little endian mode can be set Interrupt controller (INTC) User break controller (UBC) * * * * Bus state controller (BSC) * Rev. 6.0, 07/02, page 6 of 986 Table 1.1 Item SH7750 Series Features (cont) Features * Physical address DMA controller: SH7750, SH7750S: 4-channel SH7750R: 8-channel * * Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes Address modes: Single address mode Dual address mode * * * Transfer requests: External, on-chip module, or auto-requests Bus modes: Cycle-steal or burst mode Supports on-demand data transfer Auto-reload 32-bit timer: SH7750, SH7750S: 3-channel SH7750R: 5-channel * * Input capture function Choice of seven counter input clocks On-chip clock and calendar functions Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution (cycle interrupts) Two full-duplex communication channels (SCI, SCIF) Channel 1 (SCI): Choice of asynchronous mode or synchronous mode Supports smart card interface * Channel 2 (SCIF): Supports asynchronous mode Separate 16-byte FIFOs provided for transmitter and receiver Direct memory access controller (DMAC) Timer unit (TMU) * Realtime clock (RTC) * * Serial communication interface (SCI, SCIF) * * Rev. 6.0, 07/02, page 7 of 986 Table 1.1 Item SH7750 Series Features (cont) Features Abbreviation SH7750 Voltage (Internal) 1.95 V 1.8 V 1.5 V SH7750S 1.95 V Operating Frequency 200 MHz 167 MHz 128 MHz 200 MHz Model No. HD6417750BP200M HD6417750F167 HD6417750F167I HD6417750VF128 HD6417750SBP200 HD6417750SF200 1.8 V 1.5 V 167 MHz 133 MHz HD6417750SF167 HD6417750SF167I HD6417750SVF133 HD6417750SVBT133 SH7750R 1.5 V 240 MHz HD6417750RBP240 HD6417750RF240 200 MHz HD6417750RBP200 HD6417750RF200 264-pin CSP 256-pin BGA 208-pin QFP 256-pin BGA 208-pin QFP 256-pin BGA 208-pin QFP Package 256-pin BGA 208-pin QFP Product lineup Notes: *1 For SH7750R only *2 For SH7750S only *3 For SH7750 only Rev. 6.0, 07/02, page 8 of 986 1.2 Block Diagram Figure 1.1 shows an internal block diagram of the SH7750 Series. CPU 32-bit address (instructions) UBC FPU 32-bit data (instructions) 32-bit address (data) 32-bit data (store) 64-bit data (store) Lower 32-bit data Lower 32-bit data I cache ITLB Cache and TLB controller UTLB O cache 29-bit address 32-bit data CPG INTC 16-bit peripheral data bus Peripheral address bus SCI (SCIF) BSC 32-bit data DMAC 64-bit data TMU External bus interface 26-bit address 64-bit data Unified TLB (translation lookaside buffer) Realtime clock Serial communication interface Serial communication interface with FIFO Timer unit User break controller BSC: CPG: DMAC: FPU: INTC: ITLB: Bus state controller Clock pulse generator Direct memory access controller Floating-point unit Interrupt controller Instruction TLB (translation lookaside buffer) UTLB: RTC: SCI: SCIF: TMU: UBC: Figure 1.1 Block Diagram of SH7750 Series Functions Rev. 6.0, 07/02, page 9 of 986 64-bit data RTC Address Upper 32-bit data 32-bit data (load) 1.3 Pin Arrangement XTAL VSS-CPG VDD-CPG(3.3V) VDD-PLL1(3.3V) VDD-PLL2(3.3V) TDI TCK TMS TDO /BRKACK MD6/ STATUS1 STATUS0 DACK1 DACK0 MD5/ MD4/ VDD-RTC(3.3V) VSS-RTC EXTAL2 XTAL2 18 19 20 1 A 2 3 4 5 6 7 8 9 10 MD3/ A25 A24 A23 A22 A21 A20 A19 A18 MD7/TXD SCK2/ MD8/ TCLK 11 12 13 14 15 16 17 EXTAL B VSS-PLL1 VSS-PLL2 C D47 D32 D46 D33 D45 D34 D44 D35 D43 D36 D42 D37 D41 D38 D40 D39 D15 D0 D14 D1 D13 D2 D12 D3 D11 D4 D10 D5 D9 D6 D E F G H J K L M N P R T ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,,,,,,,, , , , A1 A0 NMI MD1/TXD2 MD0/SCK D63 D48 D62 D49 D61 D50 D60 D51 D59 D52 D58 D53 D57 D54 D56 D55 D31 D16 D30 D17 D29 D18 D28 D19 D27 D20 D26 D21 D25 CA* MD2/RXD2 RD/ BGA256 (Top view) / / RXD U V W ,, ,, ,, ,,,,, ,, ,, ,, ,, ,,,,, ,, CKIO CKIO2 A6 A5 A4 A3 A2 / / , , , , , , , , Y D8 D7 CKE /DQM5 /DQM4 /DQM1 /DQM0 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 DRAK1 DRAK0 / / / Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Figure 1.2 Pin Arrangement (256-Pin BGA) Rev. 6.0, 07/02, page 10 of 986 RD/ /DQM2/ /DQM3/ / /DQM6 /DQM7/ D23 D24 D22 , VDDQ (IO) VSSQ (IO) VDD (internal) VSS (internal) NC / / / / EXTAL XTAL VSS-CPG VDD-CPG(3.3V) VSS-PLL1 VDD-PLL1(3.3V) VSS-PLL2 VDD-PLL2(3.3V) /BRKACK MD6/ STATUS1 STATUS0 A1 , D47 D32 D46 D33 D45 D34 D44 D35 D43 D36 D42 D37 D41 D38 D40 D39 D15 D0 D14 D1 D13 D2 D12 D3 D11 D4 D10 D5 D9 D6 / / , , , ,, ,, /DQM5 /DQM4 /DQM1 /DQM0 A17 A16 A15 /DQM2/ /DQM3/ / /DQM6 D8 D7 CKE A12 A11 A10 A9 A8 A7 CKIO A6 A5 A4 A3 A2 DRAK1 DRAK0 RD/ / / / / / Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Figure 1.3 Pin Arrangement (208-Pin QFP) Rev. 6.0, 07/02, page 11 of 986 / / / /DQM7/ / D23 D24 D22 A14 A13 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 ,, , , CA* VDD-RTC(3.3V) VSS-RTC EXTAL2 XTAL2 SCK2/ MD7/TXD MD8/ TCLK A0 DACK1 DACK0 MD5/ MD4/ MD3/ A25 A24 TDO TDI TCK TMS A23 A22 A21 A20 A19 A18 QFP208 Top view ,, ,, ,, ,, ,, ,, VDD (internal) VSS (internal) VDDQ (IO) VSSQ (IO) 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 NMI ,, ,, MD2/RXD2 MD1/TXD2 MD0/SCK D63 D48 D62 D49 D61 D50 D60 D51 D59 D52 D58 D53 D57 D54 D56 D55 D31 D16 D30 D17 D29 D18 D28 D19 D27 D20 D26 D21 D25 RXD ,, ,, ,, ,, ,, ,, ,, ,, , , ,, ,,,,, ,,,,,, ,,, ,,, ,, , ,, , ,,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,, , ,, ,,, ,,,,, , ,,, ,,, ,,, ,,, ,,, ,, ,,, ,,, ,, 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A VSS-CPG XTAL EXTAL VDD-CPG TDO MD6 A0 VDDQ VDDQ A20 VDD TCLK VSS-RTC XTAL2 EXTAL2 B VDD-PLL2 VSS STATUS0 DACK0 A24 VDDQ MD7/TXD CA C VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/ A22 A18 VDDQ VDDQ VDD-RTC MD1/TXD2 NMI D VSSQ TDI VDD A1 MD5/ A23 VSS MD8/ VSSQ E TMS VDDQ VDDQ MD4/ VSSQ VSSQ SCK2 D48 RD/ MD2/RXD2 VSSQ F VDD D47 VDDQ D32 D33 STATUS1 DACK1 VSSQ A25 A21 A19 D49 VDDQ D63 MD0/SCK D62 G D45 VDDQ D46 VSS VSSQ D34 D50 VDDQ VDD VSSQ VSS D61 H VDDQ D43 D44 D35 VSSQ D36 J VDDQ D38 D42 D41 D37 VSSQ CSP264 (Top view) D52 VDDQ D51 VSSQ D60 D59 VSSQ D57 D53 D54 D58 VDDQ K D39 D0 VSSQ D15 VDDQ D40 D56 VSSQ D31 D16 D55 VDDQ L D1 VSS VSSQ VDD VDDQ D14 D30 VSSQ VSS D18 VDDQ D17 M D2 D4 D3 VDDQ D13 D14 A9 VDDQ A6 A2 D29 D28 D27 VDDQ D19 VDD N VSSQ D5 D11 D12 A16 VDDQ VDDQ A7 A4 DRAK0 VSSQ VSS D26 D21 VDDQ D20 P VSSQ VDDQ VDDQ VDD A11 VSSQ VSSQ VSSQ VSSQ D25 R D6 D10 CKE A17 VSS A12 A8 VDDQ VDDQ RXD T VSSQ D8 VDDQ VSSQ A13 VSSQ CKIO2 A3 VDD RD/ D24 D22 VSSQ U D9 D7 A15 VSSQ A10 CKIO A5 DRAK1 VDDQ VDDQ D23 VSSQ VDDQ (IO) VSSQ (IO) VDD (internal) VSS (internal) NC Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. Figure 1.4 Pin Arrangement (264-Pin CSP) Rev. 6.0, 07/02, page 12 of 986 1.4 1.4.1 Table 1.2 Pin No. B2 B1 C2 C1 D4 D3 D2 D1 E4 E3 F3 F4 E2 E1 G3 G4 F2 F1 H3 H4 G2 G1 H2 H1 J3 J4 J2 J1 Pin Functions Pin Functions (256-Pin BGA) Pin Functions Memory Interface Pin Name 5'< 5(6(7 &63 &64 &67 &68 &69 %6 VSSQ 5'5 VDDQ VSSQ D47 D32 VDD VSS D46 D33 VDDQ VSSQ D45 D34 D44 D35 VDDQ VSSQ D43 D36 I/O I I O O O O O O Function Bus ready Reset Chip select 0 Chip select 1 Chip select 4 Chip select 5 Chip select 6 Bust start &63 &64 &67 &68 &69 (%6) (%6) (%6) &(4$ &(4% (%6) Reset SRAM 5'< DRAM SDRAM PCMCIA MPX 5'< 5(6(7 &63 &64 &67 &68 &69 (%6) 5'< No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Power IO GND (0 V) O 5'/&$66/ )5$0( 2( &$6 2( )5$0( Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power Internal VDD (1.8 V) Power Internal GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Rev. 6.0, 07/02, page 13 of 986 Table 1.2 Pin No. K2 K1 K3 K4 L1 L2 M1 M2 L3 L4 N1 N2 P1 P2 M3 M4 R1 R2 P3 P4 T1 T2 R3 R4 U1 U2 V1 V2 T3 T4 W1 Y1 Pin Functions (cont) Memory Interface Pin Name D42 D37 VDDQ VSSQ D41 D38 D40 D39 VDDQ VSSQ D15 D0 D14 D1 VDDQ VSSQ D13 D2 VDD VSS D12 D3 VDDQ VSSQ D11 D4 D10 D5 VDDQ VSSQ D9 D6 I/O I/O I/O Function Data/port Data/port Reset SRAM (Port) (Port) DRAM (Port) (Port) SDRAM PCMCIA MPX (Port) (Port) (Port) (Port) (Port) (Port) No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A15 A0 A14 A1 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A13 A2 Power Internal VDD Power Internal GND (0 V) I/O I/O Data Data A12 A3 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A11 A4 A10 A5 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A9 A6 Rev. 6.0, 07/02, page 14 of 986 Table 1.2 Pin No. U3 Pin Functions (cont) Memory Interface Pin Name %$&./ %65(4 %5(4/ %6$&. D8 D7 CKE VDDQ VSSQ I/O O Function Bus acknowledge/ bus request Bus request/bus acknowledge Data Data Clock output enable CKE A8 A7 Reset SRAM DRAM SDRAM PCMCIA MPX No. 61 62 V3 I 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 W2 Y2 W3 V5 U5 Y3 W4 Y4 W5 Y5 V6 U6 W6 Y6 V7 U7 W7 Y7 V8 U8 V4 W8 Y8 W9 I/O I/O O Power IO VDD (3.3 V) Power IO GND (0 V) D47-D40 select signal D39-D32 select signal D15-D8 select signal D7-D0 select signal Address :(8 :(7 :(4 :(3 &$68 &$67 &$64 &$63 DQM5 DQM4 DQM1 DQM0 :(4 :(8/&$68/ O DQM5 :(7/&$67/ O DQM4 :(4/&$64/ O DQM1 :(3/&$63/ O DQM0 A17 VDDQ VSSQ A16 A15 VDD VSS A14 A13 VDDQ VSSQ NC A12 A11 A10 O O O O Power IO VDD (3.3 V) Power IO GND (0 V) O O Address Address Power Internal VDD Power Internal GND (0 V) O O Address Address Power IO VDD (3.3 V) Power IO GND (0 V) Address Address Address Rev. 6.0, 07/02, page 15 of 986 Table 1.2 Pin No. V9 U9 Y9 W10 Y10 Y11 V10 U10 W11 Y12 W12 Y13 V11 Pin Functions (cont) Memory Interface Pin Name VDDQ VSSQ A9 A8 A7 CKIO VDDQ VSSQ CKIO2 A6 A5 A4 VDDQ VSSQ A3 A2 DRAK1 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX No. 87 88 89 90 91 92 93 94 95 96 97 98 99 Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address Address Clock output CKIO Power IO VDD (3.3 V) Power IO GND (0 V) O O O O 1 CKIO* CKIO Address Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O O Address Address DMAC1 request acknowledge DMAC0 request acknowledge 100 U11 101 W13 102 Y14 103 V12 104 U13 DRAK0 O 105 V13 106 U12 107 W14 108 Y15 109 V14 110 U14 111 W15 112 Y16 113 V15 114 U15 VDDQ VSSQ &66 &65 VDD VSS 5$6 5'/&$66/ )5$0( VDDQ VSSQ Power IO VDD (3.3 V) Power IO GND (0 V) O O Chip select 3 Chip select 2 &66 &65 (&66) (&65) &66 &65 &66 &65 Power Internal VDD Power Internal GND (0 V) O O 5$6 Read/&$6/ )5$0( 2( 5$6 5$6 &$6 2( )5$0( Power IO VDD (3.3 V) Power IO GND (0 V) Rev. 6.0, 07/02, page 16 of 986 Table 1.2 Pin No. Pin Functions (cont) Memory Interface Pin Name RD/:5 I/O O Function Read/write D23-D16 select signal D31-D24 select signal D55-D48 select signal Reset SRAM DRAM SDRAM PCMCIA MPX RD/:5 ,&,25' No. 115 W16 116 Y17 RD/:5 RD/:5 RD/:5 :(5 &$65 DQM2 :(5/&$65/ O DQM2/ ,&,25' :(6/&$66/ O DQM3/ ,&,2:5 :(9/&$69/ O DQM6 VDDQ VSSQ 117 W17 :(6 &$66 DQM3 ,&,2:5 118 Y18 119 V16 120 U16 121 W18 122 Y19 123 W19 124 Y20 125 V17 126 U17 127 U18 128 W20 129 T18 130 T17 131 V19 132 V20 133 U19 134 U20 135 R18 136 R17 137 T19 138 T20 139 P18 140 P17 141 R19 :(9 &$69 DQM6 Power IO VDD (3.3 V) Power IO GND (0 V) D63-D56 select signal Data Data Data SCI data input Request from DMAC0 Request from DMAC1 Data A25 :(: &$6: DQM7 5(* A23 A24 A22 :(:/&$6:/ O DQM7/5(* D23 D24 D22 RXD '5(43 '5(44 D25 VDDQ VSSQ D21 D26 D20 D27 VDDQ VSSQ D19 D28 VDD VSS D18 I/O I/O I/O I I I I/O Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A20 A21 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A19 Power Internal VDD Power Internal GND (0 V) I/O Data A18 Rev. 6.0, 07/02, page 17 of 986 Table 1.2 Pin No. Pin Functions (cont) Memory Interface Pin Name D29 VDDQ VSSQ D17 D30 D16 D31 VDDQ VSSQ D55 D56 D54 D57 VDDQ VSSQ D53 D58 D52 D59 VDDQ VSSQ D51 D60 D50 D61 VDDQ VSSQ D49 D62 VDD VSS D48 I/O I/O Function Data Reset SRAM DRAM SDRAM PCMCIA MPX No. 142 R20 143 N18 144 N17 145 P19 146 P20 147 N19 148 N20 149 M18 150 M17 151 M19 152 M20 153 L19 154 L20 155 L18 156 L17 157 K20 158 K19 159 J20 160 J19 161 K18 162 K17 163 H20 164 H19 165 G20 166 G19 167 J18 168 J17 169 F20 170 F19 171 G18 172 G17 173 E20 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A16 A17 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE1 Power Internal VDD Power Internal GND (0 V) I/O Data/port (Port) (Port) (Port) (Port) (Port) Rev. 6.0, 07/02, page 18 of 986 Table 1.2 Pin No. Pin Functions (cont) Memory Interface Pin Name D63 VDDQ VSSQ VSSQ RD/:55 MD0/SCK I/O I/O Function Data Reset SRAM DRAM SDRAM PCMCIA MPX ACCSIZE2 No. 174 E19 175 F18 176 F17 177 E17 178 E18 179 D20 180 D19 181 D18 182 C20 183 C19 184 B20 185 C18 186 A20 187 B19 188 A19 189 B18 190 A18 191 D17 192 C17 193 B17 194 C16 195 A17 196 B16 Power IO VDD (3.3 V) Power IO GND (0 V) Power IO GND (0 V) O I/O RD/:5 Mode/SCI clock Mode SCIF data output Mode/SCIF data input Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 3 Nonmaskable interrupt RTC crystal resonator pin RTC crystal resonator pin MD0 MD1 MD2 RD/:5 RD/:5 RD/:5 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 RD/:5 SCK TXD2 RXD2 MD1/TXD2 I/O MD2/RXD2 I ,5/3 ,5/4 ,5/5 ,5/6 NMI XTAL2 EXTAL2 VSS-RTC VDD-RTC CA VSS VDDQ &765 TCLK I I I I I O I Power RTC GND (0 V) Power RTC VDD (3.3 V) I *2 Power Internal GND (0 V) Power IO VDD (3.3 V) I/O I/O SCIF data control (&76) RTC/TMU clock Mode/SCIF data control (576) MD8 5765 5765 5765 5765 5765 MD8/5765 I/O Rev. 6.0, 07/02, page 19 of 986 Table 1.2 Pin No. Pin Functions (cont) Memory Interface Pin Name VDDQ VSSQ MD7/TXD SCK2/ 05(6(7 VDD VSS A18 A19 VDDQ VSSQ A20 A21 A22 A23 VDDQ VSSQ A24 A25 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX No. 197 C15 198 D15 199 B15 200 A16 201 C14 202 D14 203 A15 204 B14 205 C13 206 D13 207 A14 208 B13 209 A13 210 B12 211 C12 212 D12 213 A12 214 B11 215 A11 216 A10 217 C11 218 D11 219 B10 220 A9 221 B9 222 C8 223 C10 224 D10 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I Mode/SCI data output SCIF clock/ manual reset MD7 TXD TXD SCK2 TXD SCK2 TXD SCK2 TXD SCK2 05(6(7 SCK2 Power Internal VDD Power Internal GND (0 V) O O Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O Address Address Mode/ PCMCIA-CE Mode/ PCMCIA-CE MD3 MD4 &(5$ &(5% MD3/&(5$ I/O MD4/&(5% I/O VDDQ VSSQ Power IO VDD (3.3 V) Power IO GND (0 V) Mode/5$6 (DRAM) DMAC0 bus acknowledge DMAC1 bus acknowledge Address MD5 5$65 MD5/5$65 I/O DACK0 DACK1 A0 VDDQ VSSQ O O O Power IO VDD (3.3 V) Power IO GND (0 V) Rev. 6.0, 07/02, page 20 of 986 Table 1.2 Pin No. Pin Functions (cont) Memory Interface Pin Name A1 STATUS0 STATUS1 MD6/ ,2,649 VDDQ VSSQ $6(%5./ BRKACK TDO VDD VSS TMS TCK TDI 7567 I/O O O O I Function Address Status Status Mode/,2,649 (PCMCIA) MD6 ,2,649 Reset SRAM DRAM SDRAM PCMCIA MPX No. 225 D8 226 A8 227 B8 228 A7 229 C9 230 D9 231 B7 Power IO VDD (3.3 V) Power IO GND (0 V) I/O Pin break/ acknowledge (H-UDI) Data out (H-UDI) 232 A6 233 C7 234 D7 235 B6 236 A5 237 B5 238 C4 239 C3 O Power Internal VDD Power Internal GND (0 V) I I I I Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) Reset (H-UDI) CKIO2, 5'5, RD/:55 enable &.,25(1% I 240 C6 241 A4 242 D6 243 B4 244 D5 245 A3 246 B3 247 A2 NC VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL Power PLL2 VDD (3.3V) Power PLL2 GND (0V) Power PLL1 VDD (3.3V) Power PLL1 GND (0V) Power CPG VDD (3.3V) Power CPG GND (0V) O Crystal resonator Rev. 6.0, 07/02, page 21 of 986 Table 1.2 Pin No. Pin Functions (cont) Memory Interface Pin Name EXTAL I/O I Function External input clock/crystal resonator Reset SRAM DRAM SDRAM PCMCIA MPX No. 248 A1 249 C5 250 D16 251 H17 252 H18 253 N3 254 N4 255 U4 256 V18 NC NC NC NC NC NC NC NC I: O: I/O: Power: Input Output Input/output Power supply Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby mode, supply power to RTC as a minimum. 2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. 3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-chip crystal resonator is used. 4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used. 5. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package. 6. In the SH7750S and SH7750R, at least the RTC power supply must be supplied in hardware standby mode. 7. NC pins must be left completely open, and not connected to a power supply, GND, etc. *1 CKIO2 is not connected to PLL2. *2 Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Rev. 6.0, 07/02, page 22 of 986 1.4.2 Table 1.3 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Functions (208-Pin QFP) Pin Functions Memory Interface Pin Name 5'< 5(6(7 &63 &64 &67 &68 &69 %6 VDDQ VSSQ D47 D32 VDD VSS D46 D33 D45 D34 D44 D35 VDDQ VSSQ D43 D36 D42 D37 D41 D38 D40 D39 I/O I I O O O O O O Power Power I/O I/O Power Power I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O Function Bus ready Reset Chip select 0 Chip select 1 Chip select 4 Chip select 5 Chip select 6 Bust start IO VDD (3.3 V) IO GND (0 V) Data/port Data/port Internal VDD Internal GND (0 V) Data/port Data/port Data/port Data/port Data/port Data/port IO VDD (3.3 V) IO GND (0 V) Data/port Data/port Data/port Data/port Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) &63 &64 &67 &68 &69 (%6) (%6) (%6) &(4$ &(4% (%6) Reset SRAM 5'< DRAM SDRAM PCMCIA MPX 5'< 5(6(7 &63 &64 &67 &68 &69 (%6) 5'< Rev. 6.0, 07/02, page 23 of 986 Table 1.3 Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin Functions (cont) Memory Interface Pin Name VDDQ VSSQ D15 D0 D14 D1 D13 D2 VDD VSS D12 D3 VDDQ VSSQ D11 D4 D10 D5 D9 D6 %$&./ %65(4 %5(4/ %6$&. D8 D7 CKE VDDQ VSSQ I/O Power Power I/O I/O I/O I/O I/O I/O Power Power I/O I/O Power Power I/O I/O I/O I/O I/O I/O O Function IO VDD (3.3 V) IO GND (0 V) Data Data Data Data Data Data Internal VDD (1.8 V) Internal GND (0 V) Data Data IO VDD (3.3 V) IO GND (0 V) Data Data Data Data Data Data Bus acknowledge/ bus request Bus request/bus acknowledge Data Data Clock output enable IO VDD (3.3 V) IO GND (0 V) D47-D40 select signal Reset SRAM DRAM SDRAM PCMCIA MPX A15 A0 A14 A1 A13 A2 A12 A3 A11 A4 A10 A5 A9 A6 52 53 54 55 56 57 58 I I/O I/O O Power Power A8 A7 CKE :(8/&$68/ O DQM5 :(8 &$68 DQM5 Rev. 6.0, 07/02, page 24 of 986 Table 1.3 Pin No. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Pin Functions (cont) Memory Interface Pin Name I/O Function D39-D32 select signal D15-D8 select signal D7-D0 select signal Address Address Address Internal VDD Internal GND (0 V) Address Address IO VDD (3.3 V) IO GND (0 V) Address Address Address Address Address Address Clock output IO VDD (3.3 V) IO GND (0 V) Address Address Address Address Address DMAC1 request acknowledge DMAC0 request acknowledge IO VDD (3.3 V) Reset SRAM :(7 :(4 :(3 DRAM &$67 &$64 &$63 SDRAM PCMCIA MPX DQM4 DQM1 DQM0 :(4 :(7/&$67/ O DQM4 :(4/&$64/ O DQM1 :(3/&$63/ O DQM0 A17 A16 A15 VDD VSS A14 A13 VDDQ VSSQ A12 A11 A10 A9 A8 A7 CKIO VDDQ VSSQ A6 A5 A4 A3 A2 DRAK1 DRAK0 VDDQ O O O Power Power O O Power Power O O O O O O O Power Power O O O O O O O Power CKIO Rev. 6.0, 07/02, page 25 of 986 Table 1.3 Pin No. 88 89 90 91 92 93 94 95 96 Pin Functions (cont) Memory Interface Pin Name VSSQ &66 &65 VDD VSS 5$6 5'/&$66/ )5$0( RD/:5 I/O Power O O Power Power O O O Function IO GND (0 V) Chip select 3 Chip select 2 Internal VDD Internal GND (0 V) 5$6 Read/&$6/ )5$0( Read/write D23-D16 select signal D31-D24 select signal D55-D48 select signal IO VDD (3.3 V) IO GND (0 V) D63-D56 select signal Data Data Data SCI Data input Request from DMAC0 Request from DMAC1 Data Data Data Data Data IO VDD (3.3 V) Reset SRAM DRAM SDRAM PCMCIA MPX &66 &65 (&66) (&65) &66 &65 &66 &65 5$6 2( 5$6 &$6 2( )5$0( RD/:5 ,&,25' RD/:5 RD/:5 RD/:5 :(5 &$65 DQM2 :(5/&$65/ O DQM2/ ,&,25' :(6/&$66/ O DQM3/ ,&,2:5 :(9/&$69/ O DQM6 VDDQ VSSQ Power Power 97 :(6 &$66 DQM3 ,&,2:5 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 :(9 &$69 DQM6 :(:/&$6:/ O DQM7/5(* D23 D24 D22 RXD '5(43 '5(44 D25 D21 D26 D20 D27 VDDQ I/O I/O I/O I I I I/O I/O I/O I/O I/O Power :(: &$6: DQM7 5(* A23 A24 A22 A25 A21 A20 Rev. 6.0, 07/02, page 26 of 986 Table 1.3 Pin No. 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Functions (cont) Memory Interface Pin Name VSSQ D19 D28 VDD VSS D18 D29 D17 D30 D16 D31 VDDQ VSSQ D55 D56 D54 D57 D53 D58 D52 D59 VDDQ VSSQ D51 D60 D50 D61 D49 D62 VDD VSS I/O Power I/O I/O Power Power I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O Power Power Function IO GND (0 V) Data Data Internal VDD Internal GND (0 V) Data Data Data Data Data Data IO VDD (3.3 V) IO GND (0 V) Data Data Data Data Data Data Data Data IO VDD (3.3 V) IO GND (0 V) Data/port Data Data/port Data Data/port Data Internal VDD Internal GND (0 V) Reset SRAM DRAM SDRAM PCMCIA MPX A19 A18 A17 A16 (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) ACCSIZE1 Rev. 6.0, 07/02, page 27 of 986 Table 1.3 Pin No. 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 Pin Functions (cont) Memory Interface Pin Name D48 D63 VDDQ VSSQ MD0/SCK MD1/TXD2 MD2/RXD2 ,5/3 ,5/4 ,5/5 ,5/6 NMI XTAL2 EXTAL2 VSS-RTC VDD-RTC CA VSS VDDQ &765 TCLK MD8/5765 MD7/TXD I/O I/O I/O Power Power I/O I/O I I I I I I O I Power Power I Power Power I/O I/O I/O I/O Function Data/port Data IO VDD (3.3 V) IO GND (0 V) Mode/SCI clock Reset SRAM (Port) DRAM (Port) SDRAM PCMCIA MPX (Port) (Port) (Port) ACCSIZE2 MD0 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 Mode SCIF data MD1 output Mode/SCIF data MD2 input Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 3 Nonmaskable interrupt RTC crystal resonator pin RTC crystal resonator pin RTC GND (0 V) RTC VDD (3.3 V) * Internal GND (0 V) IO VDD (3.3 V) SCIF data control (&76) RTC/TMU clock Mode/SCIF data MD8 control (576) Mode/SCI data output MD7 5765 TXD 5765 TXD 5765 TXD 5765 TXD 5765 TXD Rev. 6.0, 07/02, page 28 of 986 Table 1.3 Pin No. 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 Pin Functions (cont) Memory Interface Pin Name SCK2/ 05(6(7 VDD VSS A18 A19 A20 A21 A22 A23 VDDQ VSSQ A24 A25 MD3/&(5$ MD4/&(5% MD5/5$65 DACK0 DACK1 A0 VDDQ VSSQ A1 STATUS0 STATUS1 MD6/ ,2,649 $6(%5./ BRKACK I/O I Power Power O O O O O O Power Power O O I/O I/O I/O O O O Power Power O O O I I/O Function SCIF clock/ manual reset Internal VDD Internal GND (0 V) Address Address Address Address Address Address IO VDD (3.3 V) IO GND (0 V) Address Address Mode/ PCMCIA-CE Mode/ PCMCIA-CE Mode/5$6 (DRAM) DMAC0 bus acknowledge DMAC1 bus acknowledge Address IO VDD (3.3 V) IO GND (0 V) Address Status Status Mode/,2,649 (PCMCIA) Pin break/ acknowledge (H-UDI) Reset SRAM DRAM SCK2 SDRAM PCMCIA MPX SCK2 SCK2 SCK2 05(6(7 SCK2 MD3 MD4 MD5 5$65 &(5$ &(5% MD6 ,2,649 Rev. 6.0, 07/02, page 29 of 986 Table 1.3 Pin No. 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Functions (cont) Memory Interface Pin Name TDO VDD VSS TMS TCK TDI 7567 VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL EXTAL I/O O Power Power I I I I Power Power Power Power Power Power O I Function Data out (H-UDI) Internal VDD Internal GND (0 V) Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) Reset (H-UDI) PLL2 VDD (3.3V) PLL2 GND (0V) PLL1 VDD (3.3V) PLL1 GND (0V) CPG VDD (3.3V) CPG GND (0V) Crystal resonator External input clock/crystal resonator Reset SRAM DRAM SDRAM PCMCIA MPX I: O: I/O: Power: Input Output Input/output Power supply Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby mode, supply power to RTC as a minimum. 2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. 3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-chip crystal resonator is used. 4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used. 5. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package. 6. In the SH7750S and SH7750R, at least the RTC power supply must be supplied in hardware standby mode. 7. The 5'5, RD/:55, CKIO2, and &.,25(1% pins are not provided on the QFP package. 8. For a QFP package, the maximum operating frequency of the external bus is 84 MHz. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Rev. 6.0, 07/02, page 30 of 986 1.4.3 Table 1.4 Pin No. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C2 B1 D3 E2 B2 E3 E4 E1 F4 F3 D4 F2 F5 F1 G4 G3 F6 G2 G5 G1 G6 H3 H4 H1 H5 H2 H6 J3 J5 J1 Pin Functions (264-Pin CSP) Pin Functions Memory Interface Pin Name 5'< 5(6(7 &63 &64 &67 &68 &69 %6 5'5 VDDQ VSSQ D47 D32 VDD VSS D46 D33 VDDQ VSSQ D45 D34 D44 D35 VDDQ VSSQ D43 D36 D42 D37 VDDQ I/O I I O O O O O O O Function Bus ready Reset Chip select 0 Chip select 1 Chip select 4 Chip select 5 Chip select 6 Bus start 5'/&$66/ )5$0( &63 &64 &67 &68 &69 (%6) 2( (%6) (%6) &$6 &(4$ &(4% (%6) 2( Reset SRAM 5'< DRAM SDRAM PCMCIA MPX 5'< 5(6(7 &63 &64 &67 &68 &69 (%6) )5$0( 5'< Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power Internal VDD (1.5 V) Power Internal GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Rev. 6.0, 07/02, page 31 of 986 Table 1.4 Pin No. No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 J6 J4 J2 K6 K1 K5 K3 K4 K2 L6 L1 L5 L3 M5 M1 L4 L2 N5 M3 M4 N1 N4 M2 R3 N3 P3 P1 U1 R1 T1 Pin Functions (cont) Memory Interface Pin Name VSSQ D41 D38 D40 D39 VDDQ VSSQ D15 D0 D14 D1 VDDQ VSSQ D13 D2 VDD VSS D12 D3 VDDQ VSSQ D11 D4 D10 D5 VDDQ VSSQ D9 D6 %$&./ %65(4 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A15 A0 A14 A1 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A13 A2 Power Internal VDD (1.5 V) Power Internal GND (0 V) I/O I/O Data Data A12 A3 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A11 A4 A10 A5 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O O Data Data Bus acknowledge/ bus request A9 A6 Rev. 6.0, 07/02, page 32 of 986 Table 1.4 Pin No. No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 R2 T3 U2 R4 T5 T2 R5 P5 U5 P6 R6 P4 T6 N6 U6 P7 R7 M6 T7 N7 U7 R8 P8 U8 N8 T8 M8 R9 Pin Functions (cont) Memory Interface Pin Name %5(4/ %6$&. D8 D7 CKE VDDQ VSSQ I/O I I/O I/O O Function Bus request/bus acknowledge Data Data Clock output enable CKE A8 A7 Reset SRAM DRAM SDRAM PCMCIA MPX Power IO VDD (3.3 V) Power IO GND (0 V) D47-D40 select signal D39-D32 select signal D15-D8 select signal D7-D0 select signal Address :(8 :(7 :(4 :(3 &$68 &$67 &$64 &$63 DQM5 DQM4 DQM1 DQM0 :(4 :(8/&$68/ O DQM5 :(7/&$67/ O DQM4 :(4/&$64/ O DQM1 :(3/&$63/ O DQM0 A17 VDDQ VSSQ A16 A15 VDD VSS A14 A13 VDDQ VSSQ A12 A11 A10 VDDQ VSSQ A9 A8 O Power IO VDD (3.3 V) Power IO GND (0 V) O O Address Address Power Internal VDD (1.5 V) Power Internal GND (0 V) O O Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O O Address Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O Address Address Rev. 6.0, 07/02, page 33 of 986 Table 1.4 Pin No. No. 89 90 91 92 93 94 95 96 97 98 99 N9 U9 M9 P9 T9 Pin Functions (cont) Memory Interface Pin Name A7 CKIO VDDQ VSSQ CKIO2 I/O O O Function Address Clock output CKIO Reset SRAM DRAM SDRAM PCMCIA MPX Power IO VDD (3.3 V) Power IO GND (0 V) O O O O CKIO* Address Address Address CKIO M10 A6 U10 N10 R10 P10 T10 A5 A4 VDDQ VSSQ A3 Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address DMAC1 request acknowledge DMAC0 request acknowledge 100 M11 A2 101 U11 102 N11 103 R11 104 N12 105 U12 106 P11 107 T11 108 N13 109 R12 110 P12 111 U13 112 P13 113 T12 114 R15 DRAK1 DRAK0 VDDQ VSSQ &66 &65 VDD VSS 5$6 5'/&$66/ )5$0( VDDQ VSSQ RD/:5 Power IO VDD (3.3 V) Power IO GND (0 V) O O Chip select 3 Chip select 2 &66 &65 (&66) (&65) &66 &65 &66 &65 Power Internal VDD (1.5 V) Power Internal GND (0 V) O O 5$6 Read/&$6/ )5$0( 2( 5$6 5$6 &$6 2( )5$0( Power IO VDD (3.3 V) Power IO GND (0 V) O Read/write D23-D16 select signal D31-D24 select signal RD/:5 RD/:5 RD/:5 :(5 &$65 DQM2 ,&,25' RD/:5 :(5/&$65/ O DQM2/ ,&,25' :(6/&$66/ O DQM3/ ,&,2:5 115 R13 :(6 &$66 DQM3 ,&,2:5 Rev. 6.0, 07/02, page 34 of 986 Table 1.4 Pin No. No. 116 R14 117 U14 118 U17 119 U15 120 U16 121 T13 122 T15 123 R16 124 T17 125 P17 126 P15 127 N16 128 T16 129 N15 130 N14 131 N17 Pin Functions (cont) Memory Interface Pin Name I/O Function D55-D48 select signal Reset SRAM :(9 DRAM &$69 SDRAM PCMCIA MPX DQM6 :(9/&$69/ O DQM6 VDDQ VSSQ Power IO VDD (3.3 V) Power IO GND (0 V) D63-D56 select signal Data Data Data SCI1 data input Request from DMAC0 Request from DMAC1 Data A25 :(: &$6: DQM7 5(* A23 A24 A22 :(:/&$6:/ O DQM7/5(* D23 D24 D22 RXD '5(43 '5(44 D25 VDDQ VSSQ D21 D26 D20 I/O I/O I/O I I I I/O Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A20 A21 132 M14 D27 133 M15 VDDQ 134 P14 VSSQ Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A19 135 M16 D19 136 M13 D28 137 M17 VDD 138 L14 139 L15 VSS D18 Power Internal VDD (1.5 V) Power Internal GND (0 V) I/O I/O Data Data A18 140 M12 D29 141 L16 142 L13 143 L17 144 L12 VDDQ VSSQ D17 D30 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A17 Rev. 6.0, 07/02, page 35 of 986 Table 1.4 Pin No. No. 145 K15 146 K14 147 K17 148 K13 149 K16 150 K12 151 J15 152 J13 153 J17 154 J12 155 J14 156 J16 157 H12 158 H17 159 H13 160 H15 161 H14 162 H16 Pin Functions (cont) Memory Interface Pin Name D16 D31 VDDQ VSSQ D55 D56 D54 D57 VDDQ VSSQ D53 D58 D52 D59 VDDQ VSSQ D51 D60 I/O I/O I/O Function Data Data Reset SRAM DRAM SDRAM PCMCIA MPX A16 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) 163 G12 D50 164 G17 D61 165 G13 VDDQ 166 G15 VSSQ 167 F13 168 F17 D49 D62 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE1 169 G14 VDD 170 G16 VSS 171 E13 172 F15 173 F14 174 E17 175 E14 D48 D63 VDDQ VSSQ RD/:55 Power Internal VDD (1.5 V) Power Internal GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE2 Power IO VDD (3.3 V) Power IO GND (0 V) O RD/:5 RD/:5 RD/:5 RD/:5 RD/:5 Rev. 6.0, 07/02, page 36 of 986 Table 1.4 Pin No. No. 176 F16 177 C15 178 E15 179 D15 180 D17 181 A17 182 B17 183 C16 184 A15 185 A16 186 A14 187 C14 188 B13 189 C13 190 D13 191 A13 192 D12 193 C12 194 D14 195 B12 196 E12 197 A12 Pin Functions (cont) Memory Interface Pin Name MD0/SCK MD1/TXD2 I/O I/O I/O Function Mode/SCI1 clock Mode/SCIF data output Mode/SCIF data input Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 3 Nonmaskable interrupt RTC crystal resonator pin RTC crystal resonator pin Reset MD0 MD1 MD2 SRAM SCK TXD2 RXD2 DRAM SCK TXD2 RXD2 SDRAM PCMCIA MPX SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 MD2/RXD2 I ,5/3 ,5/4 ,5/5 ,5/6 NMI XTAL2 EXTAL2 VSS-RTC VDD-RTC CA VDDQ &765 TCLK MD8/5765 VDDQ VSSQ MD7/TXD SCK2/ 05(6(7 VDD I I I I I O I Power RTC GND (0 V) Power RTC VDD (3.3 V) I Hardware standby request Power IO VDD (3.3 V) I/O I/O I/O SCIF data control (&76) RTC/TMU clock Mode/SCIF data MD8 control (576) 5765 5765 5765 5765 5765 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I Mode/SCI1 data MD7 output SCIF clock/ manual reset TXD TXD SCK2 TXD SCK2 TXD SCK2 TXD SCK2 05(6(7 SCK2 Power Internal VDD (1.5 V) Rev. 6.0, 07/02, page 37 of 986 Table 1.4 Pin No. No. 198 D11 199 C11 200 F12 201 B11 202 E11 203 A11 204 F11 205 C10 206 D10 207 A10 208 E10 209 B10 210 F10 211 C9 212 E9 213 A9 214 F9 215 D9 216 B9 217 F8 218 A8 219 E8 220 C8 221 D8 222 B8 223 F7 224 A7 225 E7 226 C7 Pin Functions (cont) Memory Interface Pin Name VSS A18 A19 VDDQ VSSQ A20 A21 A22 A23 VDDQ VSSQ A24 A25 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Power Internal GND (0 V) O O Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O Address Address Mode/ PCMCIA-CE Mode/ PCMCIA-CE MD3 MD4 &(5$ &(5% MD3/&(5$ I/O MD4/&(5% I/O VDDQ VSSQ Power IO VDD (3.3 V) Power IO GND (0 V) Mode/5$6 (DRAM) DMAC0 bus acknowledge DMAC1 bus acknowledge Address MD5 5$65 MD5/5$65 I/O DACK0 DACK1 A0 VDDQ VSSQ A1 STATUS0 STATUS1 MD6/ ,2,649 VDDQ VSSQ O O O Power IO VDD (3.3 V) Power IO GND (0 V) O O O I Address Status Status Mode/,2,649 (PCMCIA) MD6 ,2,649 Power IO VDD (3.3 V) Power IO GND (0 V) Rev. 6.0, 07/02, page 38 of 986 Table 1.4 Pin No. No. 227 E6 Pin Functions (cont) Memory Interface Pin Name $6(%5./ BRKACK TDO VDD VSS TMS TCK TDI 7567 I/O I/O Function Pin break/ acknowledge (H-UDI) Data out (H-UDI) Reset SRAM DRAM SDRAM PCMCIA MPX 228 A6 229 D7 230 B7 231 E5 232 C6 233 D6 234 A5 235 D5 236 B6 237 C3 238 C5 239 C4 240 A4 241 A1 242 A2 243 A3 244 B3 245 B4 246 B5 247 B14 248 B15 249 B16 250 C1 251 C17 252 D1 253 D2 254 D16 255 E16 O Power Internal VDD (1.5 V) Power Internal GND (0 V) I I I I Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) Reset (H-UDI) CKIO2, 5'5, RD/:55 enable &.,25(1% I VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL EXTAL NC-1 NC-2 NC-3 NC-4 NC-5 NC-6 NC-7 NC-8 NC-9 NC-10 NC-11 NC-12 Power PLL2 VDD (3.3V) Power PLL2 GND (0V) Power PLL1 VDD (3.3V) Power PLL1 GND (0V) Power CPG VDD (3.3V) Power CPG GND (0V) O I Crystal resonator External clock/ crystal resonator Rev. 6.0, 07/02, page 39 of 986 Table 1.4 Pin No. No. 256 M7 257 N2 258 P2 259 P16 260 R17 261 T4 262 T14 263 U3 264 U4 Pin Functions (cont) Memory Interface Pin Name NC-13 NC-14 NC-15 NC-16 NC-17 NC-18 NC-19 NC-20 NC-21 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX I: O: I/O: Power: Input Output Input/output Power supply Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby mode, supply power to RTC as a minimum. 2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. 3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-chip crystal resonator is used. 4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used. 5. At least the RTC power supply must be supplied in hardware standby mode. 6. NC pins must be left completely open, and not connected to a power supply, GND, etc. * CKIO2 is not connected to PLL2. Rev. 6.0, 07/02, page 40 of 986 Section 2 Programming Model 2.1 Data Formats The data formats handled by the SH7750 Series are shown in figure 2.1. 7 Byte (8 bits) 15 Word (16 bits) 31 Longword (32 bits) 31 30 Single-precision floating-point (32 bits) 63 62 Double-precision floating-point (64 bits) s exp 51 fraction s exp 22 fraction 0 0 0 0 0 Figure 2.1 Data Formats Rev. 6.0, 07/02, page 41 of 986 2.2 2.2.1 Register Configuration Privileged Mode and Banks Processor Modes: The SH7750 Series has two processor modes, user mode and privileged mode. The SH7750 Series normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers--general registers, system registers, control registers, and floating-point registers--and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), the program counter (PC), the floating-point status/control register (FPSCR), and the floating-point communication register (FPUL). Access to these registers does not depend on the processor mode. Rev. 6.0, 07/02, page 42 of 986 Floating-Point Registers: There are thirty-two floating-point registers, FR0-FR15 and XF0- XF15. FR0-FR15 and XF0-XF15 can be assigned to either of two banks (FPR0_BANK0- FPR15_BANK0 or FPR0_BANK1-FPR15_BANK1). FR0-FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0- XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. Register values after a reset are shown in table 2.1. Table 2.1 Type General registers Initial Register Values Registers R0_BANK0-R7_BANK0, R0_BANK1-R7_BANK1, R8-R15 SR Initial Value* Undefined Control registers MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, I3-I0 = 1111 (H'F), reserved bits = 0, others undefined Undefined H'00000000 Undefined H'A0000000 H'00040001 Undefined GBR, SSR, SPC, SGR, DBR VBR System registers MACH, MACL, PR, FPUL PC FPSCR Floating-point registers FR0-FR15, XF0-XF15 Note: * Initialized by a power-on reset and manual reset. The register configuration in each processor is shown in figure 2.2. Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. Rev. 6.0, 07/02, page 43 of 986 31 R0_BANK0*1 *2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR 0 31 R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR 0 31 R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR 0 GBR MACH MACL PR PC (a) Register configuration in user mode R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1) R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0) Notes: *1 The R0 register is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. *2 Banked registers *3 Banked registers Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. *4 Banked registers Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.2 CPU Register Configuration in Each Processor Mode Rev. 6.0, 07/02, page 44 of 986 2.2.2 General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH7750 Series has twenty-four 32-bit general registers (R0_BANK0-R7_BANK0, R0_BANK1- R7_BANK1, and R8-R15). However, only 16 of these can be accessed as general registers R0- R15 in one processor mode. The SH7750 Series has two processor modes, user mode and privileged mode, in which R0-R7 are assigned as shown below. * R0_BANK0-R7_BANK0 In user mode (SR.MD = 0), R0-R7 are always assigned to R0_BANK0-R7_BANK0. In privileged mode (SR.MD = 1), R0-R7 are assigned to R0_BANK0-R7_BANK0 only when SR.RB = 0. * R0_BANK1-R7_BANK1 In user mode, R0_BANK1-R7_BANK1 cannot be accessed. In privileged mode, R0-R7 are assigned to R0_BANK1-R7_BANK1 only when SR.RB = 1. Rev. 6.0, 07/02, page 45 of 986 SR.MD = 0 or (SR.MD = 1, SR.RB = 0) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 (SR.MD = 1, SR.RB = 1) R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Figure 2.3 General Registers Programming Note: As the user's R0-R7 are assigned to R0_BANK0-R7_BANK0, and after an exception or interrupt R0-R7 are assigned to R0_BANK1-R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0-R7 (R0_BANK0-R7_BANK0). After a reset, the values of R0_BANK0-R7_BANK0, R0_BANK1-R7_BANK1, and R8-R15 are undefined. Rev. 6.0, 07/02, page 46 of 986 2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0-FPR15_BANK0 and FPR0_BANK1-FPR15_BANK1). These 32 registers are referenced as FR0-FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0-XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4). * Floating-point registers, FPRn_BANKi (32 registers) FPR0_BANK0, FPR1_BANK0, FPR2_BANK0, FPR3_BANK0, FPR4_BANK0, FPR5_BANK0, FPR6_BANK0, FPR7_BANK0, FPR8_BANK0, FPR9_BANK0, FPR10_BANK0, FPR11_BANK0, FPR12_BANK0, FPR13_BANK0, FPR14_BANK0, FPR15_BANK0 FPR0_BANK1, FPR1_BANK1, FPR2_BANK1, FPR3_BANK1, FPR4_BANK1, FPR5_BANK1, FPR6_BANK1, FPR7_BANK1, FPR8_BANK1, FPR9_BANK1, FPR10_BANK1, FPR11_BANK1, FPR12_BANK1, FPR13_BANK1, FPR14_BANK1, FPR15_BANK1 * Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0-FR15 are assigned to FPR0_BANK0-FPR15_BANK0. When FPSCR.FR = 1, FR0-FR15 are assigned to FPR0_BANK1-FPR15_BANK1. * Double-precision floating-point registers or single-precision floating-point register pairs, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} * Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} * Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0-XF15 are assigned to FPR0_BANK1-FPR15_BANK1. When FPSCR.FR = 1, XF0-XF15 are assigned to FPR0_BANK0-FPR15_BANK0. * Single-precision floating-point extended register pairs, XDi (8 registers): An XD register comprises two XF registers XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} Rev. 6.0, 07/02, page 47 of 986 * Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPSCR.FR = 0 FV0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 DR0 XF0 XF1 XD2 XF2 XF3 XD4 XF4 XF5 XD6 XF6 XF7 XD8 XF8 XF9 XD10 XF10 XF11 XD12 XF12 XF13 XD14 XF14 XF15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 FPSCR.FR = 1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XMTRX FV4 FV8 FV12 XMTRX XD0 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 Figure 2.4 Floating-Point Registers Rev. 6.0, 07/02, page 48 of 986 Programming Note: After a reset, the values of FPR0_BANK0-FPR15_BANK0 and FPR0_BANK1-FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined)) 31 30 29 28 27 -- MD RB BL -- 16 15 14 FD -- 10 9 M 8 Q 7 IMASK 4 3 -- 2 1 S 0 T Note: --: Reserved. These bits are always read as 0, and should only be written with 0. * MD: Processor mode MD = 0: User mode (some instructions cannot be executed, and some resources cannot be accessed) MD = 1: Privileged mode * RB: General register bank specifier in privileged mode (set to 1 by a reset, exception, or interrupt) RB = 0: R0_BANK0-R7_BANK0 are accessed as general registers R0-R7. (R0_BANK1- R7_BANK1 can be accessed using LDC/STC R0_BANK-R7_BANK instructions.) RB = 1: R0_BANK1-R7_BANK1 are accessed as general registers R0-R7. (R0_BANK0- R7_BANK0 can be accessed using LDC/STC R0_BANK-R7_BANK instructions.) * BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs while BL = 1, the processor switches to the reset state. * FD: FPU disable bit (cleared to 0 by a reset) FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F*** instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR) * M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions. * IMASK: Interrupt mask level External interrupts of a same level or a lower level than IMASK are masked. * S: Specifies a saturation operation for a MAC instruction. * T: True/false condition or carry/borrow bit Rev. 6.0, 07/02, page 49 of 986 Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC. Global base register, GBR (32 bits, initial value undefined): GBR is referenced as the base address in a GBR-referencing MOV instruction. Vector base register, VBR (32 bits, privilege protection, initial value = H'0000 0000): VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exceptions. Saved general register 15, SGR (32 bits, privilege protection, initial value undefined): The contents of R15 are saved to SGR in the event of an exception or interrupt. Debug base register, DBR (32 bits, privilege protection, initial value undefined): When the user break debug function is enabled (BRCR.UBDE = 1), DBR is referenced as the user break handler branch destination address instead of VBR. 2.2.5 System Registers Multiply-and-accumulate register high, MACH (32 bits, initial value undefined) Multiply-and-accumulate register low, MACL (32 bits, initial value undefined) MACH/MACL is used for the added value in a MAC instruction, and to store a MAC instruction or MUL operation result. Procedure register, PR (32 bits, initial value undefined): The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction, and PR is referenced by the subroutine return instruction (RTS). Program counter, PC (32 bits, initial value = H'A000 0000): PC indicates the instruction fetch address. Rev. 6.0, 07/02, page 50 of 986 Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 31 -- 22 21 20 19 18 17 FR SZ PR DN Cause 12 11 Enable 7 6 Flag 2 1 RM 0 Note: --: Reserved. These bits are always read as 0, and should only be written with 0. * FR: Floating-point register bank FR = 0: FPR0_BANK0-FPR15_BANK0 are assigned to FR0-FR15; FPR0_BANK1- FPR15_BANK1 are assigned to XF0-XF15. FR = 1: FPR0_BANK0-FPR15_BANK0 are assigned to XF0-XF15; FPR0_BANK1- FPR15_BANK1 are assigned to FR0-FR15. * SZ: Transfer size mode SZ = 0: The data size of the FMOV instruction is 32 bits. SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits). * PR: Precision mode PR = 0: Floating-point instructions are executed as single-precision operations. PR = 1: Floating-point instructions are executed as double-precision operations (the result of instructions for which double-precision is not supported is undefined). Do not set SZ and PR to 1 simultaneously; this setting is reserved. [SZ, PR = 11]: Reserved (FPU operation instruction is undefined.) * DN: Denormalization mode DN = 0: A denormalized number is treated as such. DN = 1: A denormalized number is treated as zero. * Cause: FPU exception cause field * Enable: FPU exception enable field * Flag: FPU exception flag field FPU Error (E) Cause Enable Flag FPU exception cause field FPU exception enable field FPU exception flag field Bit 17 None None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2 Rev. 6.0, 07/02, page 51 of 986 When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared. * RM: Rounding mode RM = 00: Round to Nearest RM = 01: Round to Zero RM = 10: Reserved RM = 11: Reserved * Bits 22 to 31: Reserved Floating-point communication register, FPUL (32 bits, initial value undefined): Data transfer between FPU registers and CPU registers is carried out via the FPUL register. Programming Note: When SZ = 1 and big endian mode is selected, FMOV can be used for double-precision floating-point load or store operations. In little endian mode, two 32-bit data size moves must be executed, with SZ = 0, to load or store a double-precision floating-point number. 2.3 Memory-Mapped Registers Appendix A, Address List shows the control registers mapped to memory. The control registers are double-mapped to the following two memory areas. All registers have two addresses. H'1C00 0000-H'1FFF FFFF H'FC00 0000-H'FFFF FFFF These two areas are used as follows. * H'1C00 0000-H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding filed of the TLB enables access to a memorymapped register. Accessing this area without using the address translation function of the MMU is not guaranteed. * H'FC00 0000-H'FFFF FFFF Access to area H'FF00 0000-H'FFFF FFFF in user mode will cause an address error. Memorymapped registers can be referenced in user mode by means of access that involves address translation. Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Rev. 6.0, 07/02, page 52 of 986 2.4 Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 Longword 0 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the MD5 external pin in a power-on reset. Big endian is selected when the MD5 pin is low, and little endian when high. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.5. A 31 7 07 A+1 23 07 A+2 15 7 07 A+3 0 0 A + 11 A + 10 A + 9 31 7 23 07 15 07 7 07 A+8 0 0 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 0 15 0 0 15 Word 0 31 Word 1 0 31 Word 1 Word 0 0 Address A + 4 Address A Longword Big endian Longword Little endian Figure 2.5 Data Formats In Memory Rev. 6.0, 07/02, page 53 of 986 Note: The SH7750 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. 2.6 Processor States The SH7750 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The reset state is entered when the 5(6(7 pin goes low. The CPU enters the power-on reset state if the 05(6(7 pin is high, and the manual reset state if the 05(6(7 pin is low. For more information on resets, see section 5, Exceptions. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and registers of onchip peripheral modules other than the bus state controller (BSC) are initialized. Since the bus state controller (BSC) is not initialized in the manual reset state, refreshing operations continue. Refer to the register configurations in the relevant sections for further details. Exception-Handling State: This is a transient state during which the CPU's processor state flow is altered by a reset, general exception, or interrupt exception handling source. In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the usercoded exception handling program. In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC), the status register (SR) contents are saved in the saved status register (SSR), and the R15 contents are saved in saved general register 15 (SGR). The CPU branches to the start address of the user-coded exception service routine found from the sum of the contents of the vector base address and the vector offset. See section 5, Exceptions, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode. For details, see section 9, Power-Down Modes. Bus-Released State: In this state the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.6. Rev. 6.0, 07/02, page 54 of 986 From any state when = 0 and =1 From any state when = 0 and =0 Power-on reset state = 0, =1 = 1, =1 Exception-handling state Manual reset state Reset state = 1, =0 Bus request Bus request clearance Exception interrupt End of exception transition processing Interrupt Interrupt Bus-released state Bus request Bus request Bus request clearance Bus request clearance Program execution state SLEEP instruction with STBY bit set SLEEP instruction with STBY bit cleared Sleep mode Standby mode Power-down state Figure 2.6 Processor State Transitions 2.7 Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which can only be accessed in privileged mode. Rev. 6.0, 07/02, page 55 of 986 Rev. 6.0, 07/02, page 56 of 986 Section 3 Memory Management Unit (MMU) 3.1 3.1.1 Overview Features The SH7750 Series can handle 29-bit external memory space from an 8-bit address space identifier and 32-bit logical (virtual) address space. Address translation from virtual address to physical address is performed using the memory management unit (MMU) built into the SH7750 Series. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB). The SH7750 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte). It is possible to set the virtual address space access right and implement storage protection independently for privileged mode and user mode. 3.1.2 Role of the MMU The MMU was conceived as a means of making efficient use of physical memory. As shown in figure 3.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory, it becomes necessary to divide the process into smaller parts, and map the parts requiring execution onto physical memory on an ad hoc basis ((1)). Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process. The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2)). With a virtual memory system, the size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. Thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally managed by the OS, and physical memory switching is carried out so as to enable the virtual memory required by a task to be mapped smoothly onto physical memory. Physical memory switching is performed via secondary storage, etc. The virtual memory system that came into being in this way works to best effect in a time sharing system (TSS) that allows a number of processes to run simultaneously ((3)). Running a number of processes in a TSS did not increase efficiency since each process had to take account of physical memory mapping. Efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4)). In this system, virtual memory is allocated to each process. The task of the MMU is to map a number of virtual memory areas onto physical memory in an efficient manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory. Rev. 6.0, 07/02, page 57 of 986 When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could be implemented by software alone, having address translation performed by software each time a process accessed physical memory would be very inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB) is provided in hardware, and frequently used address translation information is placed here. The TLB can be described as a cache for address translation information. However, unlike a cache, if address translation fails--that is, if an exception occurs--switching of the address translation information is normally performed by software. Thus memory management can be performed in a flexible manner by software. There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7750 Series is referred to as virtual address space, and the address space in physical memory as physical address space. Rev. 6.0, 07/02, page 58 of 986 Physical memory Process 1 Process 1 Physical memory Process 1 Virtual memory MMU Physical memory (1) (2) , ,,,, ,, MMU Physical memory Process 1 Physical memory Process 1 Virtual memory Process 2 Process 2 ,,,,,,,,,, ,,,,,,,,,, ,,,, ,,,,, ,,,,,,,,,, ,,,,,,,,,, ,, , ,,,,,,,, ,, ,,,,,,,,,, ,,,,, ,, Process 3 ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, , ,,,,,,,,,, , ,,,,,,,,,, ,,,,,,,,,, Process 3 (3) ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,, ,,,,,,,,,, , ,,,,,,,,,, ,,,,,,,,,, , , ,,,,,,,,,, ,,,,,, ,, ,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, , ,,,,,,,,,, ,,,,,,,,,, , ,,,,,,,,,, , , ,, ,,,,,,,,, ,,, , (4) Figure 3.1 Role of the MMU Rev. 6.0, 07/02, page 59 of 986 3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 Name Page table entry high register Page table entry low register Page table entry assistance register Translation table base register TLB exception address register MMU control register MMU Registers Abbreviation PTEH PTEL PTEA TTB TEA MMUCR R/W R/W R/W R/W R/W R/W R/W Initial 1 Value* Undefined Undefined Undefined Undefined Undefined P4 2 Address* Area 7 2 Address* Access Size H'FF00 0000 H'1F00 0000 32 H'FF00 0004 H'1F00 0004 32 H'FF00 0034 H'1F00 0034 32 H'FF00 0008 H'1F00 0008 32 H'FF00 000C H'1F00 000C 32 H'0000 0000 H'FF00 0010 H'1F00 0010 32 Notes: *1 The initial value is the value after a power-on reset or manual reset. *2 This is the address when using the virtual/physical address space P4 area. When making an access from physical address space area 7 using the TLB, the upper 3 bits of the address are ignored. 3.1.4 Caution Operation is not guaranteed if an area designated as a reserved area in this manual is accessed. Rev. 6.0, 07/02, page 60 of 986 3.2 Register Descriptions There are six MMU-related registers. 1. PTEH 31 VPN 10 9 8 7 ASID 0 ---- 2. PTEL 31 30 29 28 ------ PPN 10 9 8 7 6 5 4 3 2 1 0 -- V SZ PR SZ C D SH WT 3. PTEA 31 4 3 TC 2 SA 0 4. TTB 31 TTB 0 5. TEA 31 Virtual address at which MMU exception or address error occurred 6. MMUCR 31 LRUI 26 25 24 23 ---- URB 18 17 16 15 ---- URC 10 9 8 7 6 5 4 3 2 1 0 SV -- -- -- -- -- TI -- AT SQMD -- indicates a reserved bit: the write value must be 0, and a read will return 0. Figure 3.2 MMU-Related Registers Rev. 6.0, 07/02, page 61 of 986 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware. VPN varies according to the page size, but the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting can also be carried out by software. The number of the currently executing process is set in the ASID field by software. ASID is not updated by hardware. VPN and ASID are recorded in the UTLB by means of the LDLTB instruction. A branch to the P0, P3, or U0 area which uses the updated ASID after the ASID field in PTEH is rewritten should be made at least 6 instructions after the PTEH update instruction. 2. Page table entry low register (PTEL): Longword access to PTEL can be performed from H'FF00 0004 in the P4 area and H'1F00 0004 in area 7. PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not changed unless a software directive is issued. 3. Page table entry assistance register (PTEA): Longword access to PTEA can be performed from H'FF00 0034 in the P4 area and H'1F00 0034 in area 7. PTEL is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing access from the CPU in the SH7750S and SH7750R with MMUCR.AT = 0, access is always performed using the values of the SA and TC bits in this register. In the SH7750, it is not possible to access a PCMCIA interface area with MMUCR.AT = 0. In the SH7750 Series, access to a PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. The contents of this register are not changed unless a software directive is issued. 4. Translation table base register (TTB): Longword access to TTB can be performed from H'FF00 0008 in the P4 area and H'1F00 0008 in area 7. TTB is used, for example, to hold the base address of the currently used page table. The contents of TTB are not changed unless a software directive is issued. This register can be freely used by software. 5. TLB exception address register (TEA): Longword access to TEA can be performed from H'FF00 000C in the P4 area and H'1F00 000C in area 7. After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is set in TEA by hardware. The contents of this register can be changed by software. 6. MMU control register (MMUCR): MMUCR contains the following bits: LRUI: Least recently used ITLB URB: UTLB replace boundary URC: UTLB replace counter SQMD: Store queue mode bit SV: Single virtual mode bit Rev. 6.0, 07/02, page 62 of 986 TI: AT: TLB invalidate Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated by hardware. * LRUI: Least recently used ITLB. The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown below. A dash in this table means that updating is not performed. LRUI [5] When ITLB entry 0 is used When ITLB entry 1 is used When ITLB entry 2 is used When ITLB entry 3 is used Other than the above 0 1 -- -- -- [4] 0 -- 1 -- -- [3] 0 -- -- 1 -- [2] -- 0 1 -- -- [1] -- 0 -- 1 -- [0] -- -- 0 1 -- When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by an ITLB miss. An asterisk in this table means "don't care". LRUI [5] ITLB entry 0 is updated ITLB entry 1 is updated ITLB entry 2 is updated ITLB entry 3 is updated Other than the above 1 0 * * [4] 1 * 0 * [3] 1 * * 0 [2] * 1 0 * [1] * 1 * 0 [0] * * 1 0 Setting prohibited Ensure that values for which "Setting prohibited" is indicated in the above table are not set at the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. Rev. 6.0, 07/02, page 63 of 986 * URB: UTLB replace boundary. Bits that indicate the UTLB entry boundary at which replacement is to be performed. Valid only when URB > 0. * URC: UTLB replace counter. Random counter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed. When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a value is written to URC by software which results in the condition URC > URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB instruction. * SQMD: Store queue mode bit. Specifies the right of access to the store queues. 0: User/privileged access possible 1: Privileged access possible (address error exception in case of user access) * SV: Single virtual mode bit. Bit that switches between single virtual memory mode and multiple virtual memory mode. 0: Multiple virtual memory mode 1: Single virtual memory mode When this bit is changed, ensure that 1 is also written to the TI bit. * TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit always returns 0 when read. * AT: Address translation enable bit. Specifies MMU enabling or disabling. 0: MMU disabled 1: MMU enabled MMU exceptions are not generated when the AT bit is 0. In the case of software that does not use the MMU, therefore, the AT bit should be cleared to 0. 3.3 3.3.1 Address Space Physical Address Space The SH7750 Series supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3. The physical address space is permanently mapped onto 29-bit external memory space; this correspondence can be implemented by ignoring the upper 3 bits of the physical address space addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas (except the store queue area) in user mode will cause an address error. Rev. 6.0, 07/02, page 64 of 986 External memory space H'0000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'0000 0000 P0 area Cacheable U0 area Cacheable H'8000 0000 H'A000 0000 H'C000 0000 H'E000 0000 H'FFFF FFFF P1 area Cacheable P2 area Non-cacheable Address error P3 area Cacheable P4 area Non-cacheable Privileged mode Store queue area Address error User mode H'8000 0000 H'E000 0000 H'E400 0000 H'FFFF FFFF Figure 3.3 Physical Address Space (MMUCR.AT = 0) In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always performed using the values of the SA and TC bits set in the PTEA register. The PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or not the cache is used is determined by the cache control register (CCR). When the cache is used, with the exception of the P1 area, switching between the copy-back method and the write-through method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in these areas. P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3 bits of an address gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in this area. Rev. 6.0, 07/02, page 65 of 986 P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4. H'E000 0000 H'E400 0000 Reserved area H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 H'F800 0000 Store queue Instruction cache address array Instruction cache data array Instruction TLB address array Instruction TLB data arrays 1 and 2 Operand cache address array Operand cache data array Unified TLB address array Unified TLB data arrays 1 and 2 Reserved area H'FC00 0000 Control register area Figure 3.4 P4 Area The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the MMUCR.SQMD bit. For details, see section 4.7, Store Queues. The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache address array. For details, see section 4.5.1, IC Address Array. The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data array. For details, see section 4.5.2, IC Data Array. The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB address array. For details, see section 3.7.1, ITLB Address Array. Rev. 6.0, 07/02, page 66 of 986 The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2. The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 4.5.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array. For details, see section 4.5.4, OC Data Array. The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address array. For details, see section 3.7.4, UTLB Address Array. The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1 and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2. The area from H'FF00 0000 to H'FFFF FFFF is the on-chip peripheral module control register area. For details, see appendix A, Address List. 3.3.2 External Memory Space The SH7750 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC). H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 (reserved area) Figure 3.5 External Memory Space Rev. 6.0, 07/02, page 67 of 986 3.3.3 Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH7750 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256. This is called the virtual memory space. Mapping from virtual memory space to 29-bit external memory space is carried out using the TLB. Only when area 7 in external memory space is accessed using virtual memory space, addresses H'1C00 0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control register area in the physical memory space. Virtual memory space is illustrated in figure 3.6. 256 256 External memory space Area 0 Area 1 Area 2 P0 area Cacheable Address translation possible Area 3 Area 4 Area 5 Area 6 Area 7 U0 area Cacheable Address translation possible P1 area Cacheable Address translation not possible P2 area Non-cacheable Address translation not possible P3 area Cacheable Address translation possible P4 area Non-cacheable Address translation not possible Privileged mode Store queue area Address error User mode Address error Figure 3.6 Virtual Address Space (MMUCR.AT = 1) In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto a PCMCIA interface area by means of the TLB, it is necessary either to specify 1 for the WT bit or to specify 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set in page units of the TLB. Rev. 6.0, 07/02, page 68 of 986 Here, access to the PCMCIA interface area by accessing an area of P1, P2, or P4 from the CPU is disabled. In addition, the PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and address translation using the TLB. These areas can be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabled state and the TLB enable bit (C bit) is 1, accesses can be performed using the cache. In write accesses to the cache, switching between the copy-back method and the write-through method is indicated by the TLB write-through bit (WT bit), and is specified in page units. Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to the control register area. This enables on-chip peripheral module control registers to be accessed from the U0 area in user mode. In this case, the C bit for the corresponding page must be cleared to 0. P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4 area (except for the store queue area). Accesses to these areas are the same as for physical memory space. The store queue area can be mapped onto any external memory space by the MMU. However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces. For details, see section 4.7, Store Queues. 3.3.4 On-Chip RAM Space In the SH7750 Series, half of the instruction cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword) can be used in this area. This area can only be used in RAM mode. 3.3.5 Address Translation When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. Fast address translation is achieved by caching the contents of the address translation table located in external memory into the TLB. In the SH7750 Series, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the Rev. 6.0, 07/02, page 69 of 986 event of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and processing switches to the TLB miss exception routine. In the TLB miss exception routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. In the multiple virtual memory system, a number of processes run while sharing the virtual address space, and a particular virtual address may be translated into different physical addresses depending on the process. The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method (see section 3.4.3, Address Translation Method). 3.3.7 Address Space Identifier (ASID) In multiple virtual memory mode, the 8-bit address space identifier (ASID) is used to distinguish between processes running simultaneously while sharing the virtual address space. Software can set the ASID of the currently executing process in PTEH in the MMU. The TLB does not have to be purged when processes are switched by means of ASID. In single virtual memory mode, ASID is used to provide memory protection for processes running simultaneously while using the virtual memory space on an exclusive basis. Note: In single virtual memory mode, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously. Rev. 6.0, 07/02, page 70 of 986 3.4 3.4.1 TLB Functions Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the instruction TLB in the event of an ITLB miss Information in the address translation table located in external memory is cached into the UTLB. The address translation table contains virtual page numbers and address space identifiers, and corresponding physical page numbers and page management information. Figure 3.7 shows the overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure 3.8 shows the relationship between the address format and page size. Entry 0 Entry 1 Entry 2 ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Figure 3.7 UTLB Configuration Rev. 6.0, 07/02, page 71 of 986 * 1-kbyte page 31 Virtual address 10 9 VPN Offset 0 28 Physical address 10 9 PPN Offset 0 * 4-kbyte page 31 Virtual address 12 11 VPN Offset 0 28 Physical address 12 11 PPN Offset 0 * 64-kbyte page 31 VPN Virtual address 16 15 Offset 0 28 Physical address 16 15 PPN Offset 0 * 1-Mbyte page 31 VPN Virtual address 20 19 Offset 0 28 PPN Physical address 20 19 Offset 0 Figure 3.8 Relationship between Page Size and Address Format * VPN: Virtual page number For 1-kbyte page: upper 22 bits of virtual address For 4-kbyte page: upper 20 bits of virtual address For 64-kbyte page: upper 16 bits of virtual address For 1-Mbyte page: upper 12 bits of virtual address * ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed. * SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. Rev. 6.0, 07/02, page 72 of 986 * SZ: Page size bits Specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-Mbyte page * V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. * PPN: Physical page number Upper 22 bits of the physical address. With a 1-kbyte page, PPN bits [28:10] are valid. With a 4-kbyte page, PPN bits [28:12] are valid. With a 64-kbyte page, PPN bits [28:16] are valid. With a 1-Mbyte page, PPN bits [28:20] are valid. The synonym problem must be taken into account when setting the PPN (see section 3.5.5, Avoiding Synonym Problems). * PR: Protection key data 2-bit data expressing the page access right as a code. 00: Can be read only, in privileged mode 01: Can be read and written in privileged mode 10: Can be read only, in privileged or user mode 11: Can be read and written in privileged mode or user mode * C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1. Rev. 6.0, 07/02, page 73 of 986 * D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed * WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0. * SA: Space attribute bits Valid only when the page is mapped onto PCMCIA connected to area 5 or 6. 000: Undefined 001: Variable-size I/O space (base size according to ,2,649 signal) 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space * TC: Timing control bit Used to select wait control register bits in the bus control unit for areas 5 and 6. 0: WCR2 (A5W2-A5W0) and PCR (A5PCW1-A5PCW0, A5TED2-A5TED0, A5TEH2- A5TEH0) are used 1: WCR2 (A6W2-A6W0) and PCR (A6PCW1-A6PCW0, A6TED2-A6TED0, A6TEH2- A6TEH0) are used Rev. 6.0, 07/02, page 74 of 986 3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries. The address translation information is almost the same as that in the UTLB, but with the following differences: 1. D and WT bits are not supported. 2. There is only one PR bit, corresponding to the upper of the PR bits in the UTLB. Entry 0 ASID [7:0] VPN [31:10] V Entry 1 ASID [7:0] VPN [31:10] V Entry 2 ASID [7:0] VPN [31:10] V Entry 3 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Figure 3.9 ITLB Configuration 3.4.3 Address Translation Method Figures 3.10 and 3.11 show flowcharts of memory accesses using the UTLB and ITLB. Rev. 6.0, 07/02, page 75 of 986 Data access to virtual address (VA) VA is in P4 area On-chip I/O access VA is in P2 area 0 VA is in P1 area No VA is in P0, U0, or P3 area CCR.OCE? 1 MMUCR.AT = 1 Yes 0 CCR.CB? 1 0 CCR.WT? 1 No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes No VPNs match and V = 1 Yes No VPNs match and ASIDs match and V=1 Yes Only one entry matches Yes SR.MD? No Data TLB miss exception 0 (User) PR? 00 or 01 W 10 R/W? R Data TLB protection violation exception 11 R/W? R D? 0 W W 1 1 (Privileged) Memory access 01 or 11 R/W? R Data TLB multiple hit exception 00 or 10 R/W? R Data TLB protection violation exception W Initial page write exception C=1 and CCR.OCE = 1 Yes Cache access in copy-back mode 0 WT? 1 Cache access in write-through mode No Memory access (Non-cacheable) Figure 3.10 Flowchart of Memory Access Using UTLB Rev. 6.0, 07/02, page 76 of 986 Instruction access to virtual address (VA) VA is in P4 area VA is in P2 area 0 VA is in P1 area No CCR.ICE? 1 MMUCR.AT = 1 Yes VA is in P0, U0, or P3 area Access prohibited No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes No VPNs match and V = 1 Yes No VPNs match and ASIDs match and V=1 Yes Search UTLB Yes Hardware ITLB miss handling Record in ITLB Only one entry matches Yes No Match? No Instruction TLB miss exception 0 SR.MD? 0 (User) 1 (Privileged) PR? 1 Instruction TLB multiple hit exception Instruction TLB protection violation exception C=1 and CCR.ICE = 1 Yes Cache access No Memory access (Non-cacheable) Figure 3.11 Flowchart of Memory Access Using ITLB Rev. 6.0, 07/02, page 77 of 986 3.5 3.5.1 MMU Functions MMU Hardware Management The SH7750 Series supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C, WT, SA, and TC bits). 3. If address translation cannot be performed normally in a data access or instruction access, the MMU notifies software by means of an MMU exception. 4. If address translation information is not recorded in the ITLB in an instruction access, the MMU searches the UTLB, and if the necessary address translation information is recorded in the UTLB, the MMU copies this information into the ITLB in accordance with MMUCR.LRUI. 3.5.2 MMU Software Management Software processing for the MMU consists of the following: 1. Setting of MMU-related registers. Some registers are also partially updated by hardware automatically. 2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB. ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. For deleting or reading UTLB/ITLB entries, it is possible to access the memory-mapped UTLB/ITLB. 3. MMU exception handling. When an MMU exception occurs, processing is performed based on information set by hardware. 3.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7750 Series copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in figure 3.12. Rev. 6.0, 07/02, page 78 of 986 MMUCR 31 LRUI 26 25 24 23 -- URB 18 17 16 15 -- URC 10 9 8 7 SV -- 3210 TI -- AT Entry specification SQMD PTEL 31 29 28 -- 10 9 8 7 VPN -- ASID 0 PPN 10 9 8 7 6 5 4 3 2 1 0 -- V SZ PR SZ C D SHWT PTEH 31 PTEA 31 -- 432 TC SA 0 Write Entry 0 Entry 1 Entry 2 ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC UTLB Figure 3.12 Operation of LDTLB Instruction 3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7750 Series searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address translation information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software. Rev. 6.0, 07/02, page 79 of 986 3.5.5 Avoiding Synonym Problems When 1- or 4-kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity. This problem does not occur with the instruction TLB or instruction cache . In the SH7750 Series, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4kbyte page, are subject to address translation. As a result, bits [13:10] of the physical address after translation may differ from bits [13:10] of the virtual address. Consequently, the following restrictions apply to the recording of address translation information in UTLB entries. 1. When address translation information whereby a number of 1-kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:10] values are the same. 2. When address translation information whereby a number of 4-kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:12] values are the same. 3. Do not use 1-kbyte page UTLB entry physical addresses with UTLB entries of a different page size. 4. Do not use 4-kbyte page UTLB entry physical addresses with UTLB entries of a different page size. The above restrictions apply only when performing accesses using the cache. When cache index mode is used, VPN [25] is used for the entry address instead of VPN [13], and therefore the above restrictions apply to VPN [25]. Note: When multiple items of address translation information use the same physical memory to provide for future SuperH RISC engine family expansion, ensure that the VPN [20:10] values are the same. Also, do not use the same physical address for address translation information of different page sizes. Rev. 6.0, 07/02, page 80 of 986 3.6 MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions occurs. 3.6.1 Instruction TLB Multiple Hit Exception An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the virtual address to which an instruction access has been made. If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit exception will result. When an instruction TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. Rev. 6.0, 07/02, page 81 of 986 3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below. This is the same as the processing for a data TLB miss exception. Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the instruction TLB miss exception handling routine. Software Processing (Instruction TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the TLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. Rev. 6.0, 07/02, page 82 of 986 3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the instruction TLB protection violation exception handling routine. Software Processing (Instruction TLB Protection Violation Exception Handling Routine): Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. Rev. 6.0, 07/02, page 83 of 986 3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling. When a data TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted. Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. Rev. 6.0, 07/02, page 84 of 986 Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Rev. 6.0, 07/02, page 85 of 986 Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. The initial page write exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an initial page write exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'080 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the initial page write exception handling routine. Rev. 6.0, 07/02, page 86 of 986 Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table entry recorded in external memory. If necessary, the values of the SA and TC bits should be written to PTEA. 4. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 5. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.7 Memory-Mapped TLB Configuration To enable the ITLB and UTLB to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. A branch to an area other than the P2 area should be made at least 8 instructions after this MOV instruction. The ITLB and UTLB are allocated to the P4 area in physical memory space. VPN, V, and ASID in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as data array 2. VPN, D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both the address array side and the data array side. Only longword access is possible. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. Rev. 6.0, 07/02, page 87 of 986 3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field bits [1:0]. In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0]. The following two kinds of operation can be used on the ITLB address array: 1. ITLB address array read VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB address array write VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 24 23 31 Address field 1 1 1 1 0 0 1 0 31 Data field VPN VPN: Virtual page number V: Validity bit E: Entry 10 9 8 7 E 10 9 8 7 V ASID 0 0 ASID: Address space identifier : Reserved bits (0 write value, undefined read value) Figure 3.13 Memory-Mapped ITLB Address Array Rev. 6.0, 07/02, page 88 of 986 3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1, and the entry is selected by bits [9:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bit [6], C by bit [3], and SH by bit [1]. The following two kinds of operation can be used on ITLB data array 1: 1. ITLB data array 1 read PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 1 write PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 24 23 31 Address field 1 1 1 1 0 0 1 1 0 31 30 29 28 Data field PPN 10 9 8 7 E 10 9 8 7 6 5 4 3 2 1 0 V C 0 PPN: V: E: SZ: Physical page number Validity bit Entry Page size bits PR: C: SH: : PR SZ SH Protection key data Cacheability bit Share status bit Reserved bits (0 write value, undefined read value) Figure 3.14 Memory-Mapped ITLB Data Array 1 Rev. 6.0, 07/02, page 89 of 986 3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry is selected by bits [9:8]. In the data field, SA is indicated by bits [2:0], and TC by bit [3]. The following two kinds of operation can be used on ITLB data array 2: 1. ITLB data array 2 read SA and TC are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 2 write SA and TC specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 24 23 31 Address field 1 1 1 1 0 0 1 1 1 31 Data field TC: Timing control bit E: Entry 10 9 8 7 E 4320 SA TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) 0 Figure 3.15 Memory-Mapped ITLB Data Array 2 3.7.4 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field. Rev. 6.0, 07/02, page 90 of 986 In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0]. The following three kinds of operation can be used on the UTLB address array: 1. UTLB address array read VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. UTLB address array write (non-associative) VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. UTLB address array write (associative) When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. The usual address comparison rules are followed, but if a UTLB miss occurs, the result is no operation, and an exception is not generated. If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field, D and V specified in the data field are written to that entry. If there is more than one matching entry, a data TLB multiple hit exception results. This associative operation is simultaneously carried out on the ITLB, and if a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison results in no operation, a write to the ITLB side only is performed as long as there is an ITLB match. If there is a match in both the UTLB and ITLB, the UTLB information is also written to the ITLB. 31 24 23 Address field 1 1 1 1 0 1 1 0 31 30 29 28 Data field VPN: V: E: D: Virtual page number Validity bit Entry Dirty bit VPN 14 13 E 87 A 0 ASID 210 10 9 8 7 DV ASID: Address space identifier A: Association bit : Reserved bits (0 write value, undefined read value) Figure 3.16 Memory-Mapped UTLB Address Array Rev. 6.0, 07/02, page 91 of 986 3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry is selected by bits [13:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits [6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0]. The following two kinds of operation can be used on UTLB data array 1: 1. UTLB data array 1 read PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 1 write PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. 31 24 23 14 13 E 10 9 8 7 6 5 4 3 2 1 0 PPN PPN: V: E: SZ: D: Physical page number Validity bit Entry Page size bits Dirty bit PR: C: SH: WT: : V PR CD 87 0 Address field 1 1 1 1 0 1 1 1 0 31 30 29 28 Data field Protection key data SZ SH WT Cacheability bit Share status bit Write-through bit Reserved bits (0 write value, undefined read value) Figure 3.17 Memory-Mapped UTLB Data Array 1 Rev. 6.0, 07/02, page 92 of 986 3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry is selected by bits [13:8]. In the data field, TC is indicated by bit [3], and SA by bits [2:0]. The following two kinds of operation can be used on UTLB data array 2: 1. UTLB data array 2 read SA and TC are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 2 write SA and TC specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 1 1 1 1 31 Data field TC: Timing control bit E: Entry 14 13 E 432 SA TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) 0 87 0 Figure 3.18 Memory-Mapped UTLB Data Array 2 Rev. 6.0, 07/02, page 93 of 986 Rev. 6.0, 07/02, page 94 of 986 Section 4 Caches 4.1 4.1.1 Overview Features An SH7750 or SH7750S has an on-chip 8-kbyte instruction cache (IC) for instructions and 16kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) may alternatively be used as on-chip RAM. The features of this cache are summarized in table 4.1 The SH7750R has an on-chip 16-kbyte instruction cache (IC) for instructions and 32-kbyte operand cache (OC) for data. Half of the memory of the operand cache (16 kbytes) may alternatively be used as on-chip RAM. When the EMODE bit of the CCR register is 0, the SH7750R's cache is set to operate in the SH7750/SH7750S-compatible mode and behaves as shown in table 4.1. The features of the cache when the EMODE bit in the CCR register is 1 are given in table 4.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset. For high-speed writing to external memories, the SH7750 series supports 32 bytes x 2 of store queues (SQ). Table 4.3 lists the features of these SQs. Table 4.1 Item Capacity Type Line size Entries Write method Cache Features (SH7750, SH7750S) Instruction Cache 8-kbyte cache Direct mapping 32 bytes 256 Operand Cache 16-kbyte cache or 8-kbyte cache + 8-kbyte RAM Direct mapping 32 bytes 512 Copy-back/write-through selectable Table 4.2 Item Capacity Type Line size Entries Cache Features (SH7750R) Instruction Cache 16-kbyte cache 2-way set-associative 32 bytes 256 entries/way Operand Cache 32-kbyte cache or 16-kbyte cache + 16-kbyte RAM 2-way set-associative 32 bytes 512 entries/way Copy-back/write-through selectable LRU (least-recently-used) algorithm LRU algorithm Rev. 6.0, 07/02, page 95 of 986 Write method Replacement method Table 4.3 Item Capacity Addresses Write Write-back Access right Features of Store Queues Store Queues 2 x 32 bytes H'E000 0000 to H'E3FF FFFF Store instruction (1-cycle write) Prefetch instruction (PREF instruction) MMU off: according to MMUCR.SQMD MMU on: according to individual page PR 4.1.2 Register Configuration Table 4.4 shows the cache control registers. Table 4.4 Name Cache control register Queue address control register 0 Queue address control register 1 Cache Control Registers Abbreviation R/W CCR QACR0 QACR1 R/W R/W R/W Initial 1 Value* H'0000 0000 Undefined Undefined P4 2 Address* H'FF00 001C H'FF00 0038 H'FF00 003C Area 7 2 Address* H'1F00 001C H'1F00 0038 H'1F00 003C Access Size 32 32 32 Notes: *1 The initial value is the value after a power-on or manual reset. *2 This is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. Rev. 6.0, 07/02, page 96 of 986 4.2 Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. CCR 31 30 16 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 CB EMODE* QACR0 31 54 210 IIX ICI ICE OIX ORA OCI WT OCE AREA QACR1 31 54 210 AREA *: SH7750R only indicates reserved bits: 0 must be specified in a write; the read value is 0. Figure 4.1 Cache and Store Queue Control Registers (1) Cache Control Register (CCR): CCR contains the following bits: EMODE: IIX: ICI: ICE: OIX: ORA: OCI: CB: WT: OCE: Double-sized cache mode (Only for SH7750R; reserved bit for SH7750 and SH7750S) IC index enable IC invalidation IC enable OC index enable OC RAM enable OC invalidation Copy-back enable Write-through enable OC enable Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in area 7. The CCR bits are used for the cache settings described below. Consequently, CCR modifications must only be made by a program in the non-cached P2 area. After CCR is updated, an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or U0 area should be located at least eight instructions after the CCR update instruction. Rev. 6.0, 07/02, page 97 of 986 * EMODE: Double-sized cache mode bit In the SH7750R, this bit indicates whether the double-sized cache mode is used or not. This bit is reserved in the SH7750 and SH7750S. The EMODE bit must not be written to while the cache is being used. 0: SH7750/SH7750S-compatible mode* (initial value) 1: Double-sized cache mode * IIX: IC index enable bit 0: Effective address bits [12:5] used for IC entry selection 1: Effective address bits [25] and [11:5] used for IC entry selection * ICI: IC invalidation bit When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns 0 when read. * ICE: IC enable bit Indicates whether or not the IC is to be used. When address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1. 0: IC not used 1: IC used * OIX: OC index enable bit* 0: Effective address bits [13:5] used for OC entry selection 1: Effective address bits [25] and [12:5] used for OC entry selection 2 1 * ORA: OC RAM enable bit* 3 When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0. 0: Normal mode (the entire OC is used as a cache) 1: RAM mode (half of the OC is used as a cache and the other half is used as RAM) * OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. * CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode Rev. 6.0, 07/02, page 98 of 986 * WT: Write-through bit Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode * OCE: OC enable bit Indicates whether or not the OC is to be used. When address translation is performed, the OC cannot be used unless the C bit in the page management information is also 1. 0: OC not used 1: OC used Note: *1 No compatibility for RAM mode in OC index mode and address assignment in RAM mode. *2 When the ORA bit is 1 in the SH7750R, the OIX bit should be cleared to 0. *3 When the OIX bit in the SH7750R is 1, the ORA bit should be cleared to 0. (2) Queue Address Control Register 0 (QACR0): Longword access to QACR0 can be performed from H'FF00 0038 in the P4 area and H'1F00 0038 in area 7. QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is off. (3) Queue Address Control Register 1 (QACR1): Longword access to QACR1 can be performed from H'FF00 003C in the P4 area and H'1F00 003C in area 7. QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is off. 4.3 4.3.1 Operand Cache (OC) Configuration The operand cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 512 cache lines, each composed of a 19-bit tag, V bit, U bit, and 32-byte data. The SH7750R's operand cache is 2-way set-associative. Each way consists of 512 cache lines. Figure 4.2 shows the configuration of the operand cache for the SH7750 and SH7750S. Figure 4.3 shows the configuration of the operand cache for the SH7750R. Rev. 6.0, 07/02, page 99 of 986 Effective address 31 26 25 13 12 11 10 9 543210 RAM area determination [11:5] OIX [13] ORA [12] 22 9 Entry selection 0 Address array Tag U V 3 Longword (LW) selection Data array LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 MMU 19 511 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Read data Write data Hit signal Figure 4.2 Configuration of Operand Cache(SH7750, SH7750S) Rev. 6.0, 07/02, page 100 of 986 Effective address 31 26 25 13 12 10 54 2 0 RAM area judgment OIX ORA Entry selection 22 9 0 Address array (way 0, way 1) Tag address U V 3 [12:5] [13] Longword (LW) selection Data array (way 0, way 1) LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 LRU MMU 19 511 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit Compare Compare way 0 way 1 Read data Write data Hit signal Figure 4.3 Configuration of Operand Cache (SH7750R) Rev. 6.0, 07/02, page 101 of 986 * Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset. * V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. * U bit (dirty bit) The U bit is set to 1 if data is written to the cache line while the cache is being used in copyback mode. That is, the U bit indicates a mismatch between the data in the cache line and the data in external memory. The U bit is never set to 1 while the cache is being used in writethrough mode, unless it is modified by accessing the memory-mapped cache (see section 4.5, Memory-Mapped Cache Configuration). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. * Data field The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. * LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address (address: 13-5). When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its value is controlled by hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset. The LRU bits cannot be read or written by software. Rev. 6.0, 07/02, page 102 of 986 4.3.2 Read Operation When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: (3a) * If the tag matches and the V bit is 1 * If the tag matches and the V bit is 0 * If the tag does not match and the V bit is 0 (3b) (3b) * If the tag does not match, the V bit is 1, and the U bit is 0 (3b) * If the tag does not match, the V bit is 1, and the U bit is 1 (3c) 3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 3c. Cache miss (with write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the write-back buffer. Then data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back buffer is then written back to external memory. Rev. 6.0, 07/02, page 103 of 986 4.3.3 Write Operation When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: Copy-back Write-through * If the tag matches and the V bit is 1 * If the tag matches and the V bit is 0 (3a) (3c) (3b) (3d) (3d) (3d) (3d) (3c) * If the tag does not match and the V bit is 0 (3c) * If the tag does not match, the V bit is 1, and the U bit is 0 * If the tag does not match, the V bit is 1, and the U bit is 1 (3e) 3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. 3b. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. A write is also performed to the corresponding external memory using the specified access size. 3c. Cache miss (no copy-back/write-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. 3d. Cache miss (write-through) A write of the specified access size is performed to the external memory corresponding to the effective address. In this case, a write to cache is not performed. Rev. 6.0, 07/02, page 104 of 986 3e. Cache miss (with copy-back/write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written back to external memory. 4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, the SH7750 Series has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination. Physical address bits [28:5] LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 Figure 4.4 Configuration of Write-Back Buffer 4.3.5 Write-Through Buffer The SH7750 Series has a 64-bit buffer for holding write data when writing data in write-through mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory. Physical address bits [28:0] LW0 LW1 Figure 4.5 Configuration of Write-Through Buffer Rev. 6.0, 07/02, page 105 of 986 4.3.6 RAM Mode Setting CCR.ORA to 1 enables half of the operand cache to be used as RAM. In the SH7750 or SH7750S, the 8 kbytes of operand cache entries 128 to 255 and 384 to 511 are used as RAM. In the SH7750/SH7750S-compatible mode of the SH7750R, the 8-kbyte area otherwise used for OC entries 256 to 511 is designated as a RAM area. In the double-sized cache mode of the SH7750R, a total of 16 kbytes, comprising entries 256 to 511 in both of the ways of the operand cache, is designated as a RAM area. Other entries can still be used as cache. RAM can be accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadword-size data reads and writes can be performed in the operand cache RAM area. Instruction fetches cannot be performed in this area. With the SH7750R, the OC index mode is not available in RAM mode. An example of RAM use in the SH7750 or SH7750S is shown below. Here, the 4 kbytes comprising OC entries 128 to 255 are designated as RAM area 1, and the 4 kbytes comprising OC entries 384 to 511 as RAM area 2. * When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 2 H'7C00 3000 to H'7C00 3FFF (4 kB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 4FFF (4 kB): Corresponds to RAM area 1 : : : RAM areas 1 and 2 in the SH7750 or SH7750S then repeat every 8 kbytes up to H'7FFF FFFF. Thus, to secure a continuous 8-kbyte RAM area, the area from H'7C00 1000 to H'7C00 2FFF can be used, for example. * When OC index mode is on (CCR.OIX = 1) H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 1 : : : H'7DFF F000 to H'7DFF FFFF (4 kB): Corresponds to RAM area 1 H'7E00 0000 to H'7E00 0FFF (4 kB): Corresponds to RAM area 2 H'7E00 1000 to H'7E00 1FFF (4 kB): Corresponds to RAM area 2 : : : H'7FFF F000 to H'7FFF FFFF (4 kB): Corresponds to RAM area 2 As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-kbyte RAM area. Rev. 6.0, 07/02, page 106 of 986 Examples of RAM usage with the SH7750R is shown below. * In SH7750/SH7750S-compatible mode (CCR.EMODE = 0) H'7C00 0000 to H'7C00 1FFF (8 kB): RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 kB): RAM area (entries 256 to 511) : : : In the same pattern, shadows of the RAM area are created in 8-kbyte blocks until H'7FFF FFFF is reached. * In double-sized cache mode (CCR.EMODE = 1) In this mode, the 8 kbytes comprising entries 256 to 511 of OC way 0 are designated as RAM area 1 and the 8-kbytes comprising entries 256 to 511 of OC way 1 are designated as RAM area 2. H'7C00 0000 to H'7C00 1FFF (8 kB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 3FFF (8 kB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 5FFF (8 kB): Corresponds to RAM area 1 H'7C00 6000 to H'7C00 7FFF (8 kB): Corresponds to RAM area 2 : : : In the same pattern, shadows of the RAM area are created in 16-kbyte blocks until H'7FFF FFFF is reached. 4.3.7 OC Index Mode Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing is performed using bits [13:5] of the effective address. Using index mode allows the OC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. The SH7750R cannot be used in RAM mode when OC index mode is selected. 4.3.8 Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In the SH7750 Series, the following four new instructions are supported for cache operations. Details of these instructions are given in the Programming Manual. Invalidate instruction: Purge instruction: Write-back instruction: Allocate instruction: OCBI @Rn OCBP @Rn OCBWB @Rn MOVCA.L R0,@Rn Cache invalidation (no write-back) Cache invalidation (with write-back) Cache write-back Cache allocation Rev. 6.0, 07/02, page 107 of 986 4.3.9 Prefetch Operation The SH7750 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance. If a prefetch instruction is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or a protection violation, the result is no operation, and an exception is not generated. Details of the prefetch instruction are given in the Programming Manual. Prefetch instruction: PREF @Rn 4.4 4.4.1 Instruction Cache (IC) Configuration The instruction cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32-byte data (16 instructions). The SH7750R's instruction cache is 2-way set associative. Each way consists of 256 cache lines. Figure 4.6 shows the configuration of the instruction cache for the SH7750 and SH7750S. Figure 4.7 shows the configuration of the instruction cache for the SH7750R. Rev. 6.0, 07/02, page 108 of 986 Effective address 31 26 25 13 12 11 10 9 543210 [11:5] IIX [12] Longword (LW) selection 8 Entry selection 22 Address array 0 Tag V 3 Data array LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 MMU 19 255 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Read data Hit signal Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S) Rev. 6.0, 07/02, page 109 of 986 Effective address 31 25 13 12 11 10 54 2 0 [11:5] IIX [12] Entry selection 22 8 0 Address array (way 0, way1) Tag address V 3 Longword (LW) selection Data array (way 0, way 1) LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 LRU MMU 19 255 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit Compare Compare way 0 way 1 Read data Hit signal Figure 4.7 Configuration of Instruction Cache (SH7750R) * Tag Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is not initialized by a power-on or manual reset. * V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. * Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. Rev. 6.0, 07/02, page 110 of 986 * LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address (address: 12-5). When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset. The LRU bits cannot be read or written by software. 4.4.2 Read Operation When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an effective address from a cacheable area, the instruction cache operates as follows: 1. The tag and V bit are read from the cache line indexed by effective address bits [12:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: * * * * If the tag matches and the V bit is 1 If the tag matches and the V bit is 0 If the tag does not match and the V bit is 0 If the tag does not match and the V bit is 1 (3a) (3b) (3b) (3b) 3a. Cache hit The data indexed by effective address bits [4:2] is read as an instruction from the data field of the cache line indexed by effective address bits [12:5]. 3b. Cache miss Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU as an instruction. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. Rev. 6.0, 07/02, page 111 of 986 4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S) To enable the IC and OC to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and accesses are always longword-size. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. 4.5.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In Rev. 6.0, 07/02, page 112 of 986 other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. 24 23 31 Address field 1 1 1 1 0 0 0 0 31 Data field Tag V : Validity bit A : Association bit : Reserved bits (0 write value, undefined read value) 13 12 Entry 10 9 543210 A 10 V Figure 4.8 Memory-Mapped IC Address Array 4.5.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. Rev. 6.0, 07/02, page 113 of 986 31 24 23 Address field 1 1 1 1 0 0 0 1 31 Data field 13 12 Entry 54 L 210 0 Longword data L : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.9 Memory-Mapped IC Data Array 4.5.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. Rev. 6.0, 07/02, page 114 of 986 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If an UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 24 23 31 Address field 1 1 1 1 0 1 0 0 31 Data field Tag V : Validity bit U : Dirty bit A : Association bit : Reserved bits (0 write value, undefined read value) 14 13 Entry 10 9 543210 A 210 UV Figure 4.10 Memory-Mapped OC Address Array 4.5.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. Rev. 6.0, 07/02, page 115 of 986 The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the entry set in the address field. This write does not set the U bit to 1 on the address array side. 31 24 23 14 13 Entry 54 L 0 Longword data L : Longword specification bits : Reserved bits (0 write value, undefined read value) 210 Address field 1 1 1 1 0 1 0 1 31 Data field Figure 4.11 Memory-Mapped OC Data Array 4.6 Memory-Mapped Cache Configuration (SH7750R) To enable the management of the IC and OC by software, a program running in the privileged mode is allowed to access their contents. The contents of IC can be read and written by using MOV instructions in a P2-area program running in the privileged mode. Operation is not guaranteed for access from a program in some other area. Any branching to other areas must take place at least 8 instructions after this MOV instruction. The contents of IC can be read and written by using MOV instructions in a P1- or P2-area program running in the privileged mode. Operation is not guaranteed if access is attempted from a program running in some other area. A branch to the P0, U0, or P3 area must be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area of the physical memory space. The address and data arrays of both the IC and OC are only accessible by their data fields. Longword operations must be used. Instruction fetches from these areas are not possible. For reserved bits, a write value of 0 should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750Scompatible mode, the configuration of the SH7750R's memory-mapped cache is the same as that of the SH7750 or SH7750S. Rev. 6.0, 07/02, page 116 of 986 4.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the way and the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the way and the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set by bit [13] is not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit for that way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. Rev. 6.0, 07/02, page 117 of 986 31 24 23 Address field 1 1 1 1 0 0 0 0 13 12 Entry Way 543210 A 31 Data field Tag 10 9 10 V V : Validity bit A : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, the way is specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. Rev. 6.0, 07/02, page 118 of 986 31 24 23 Address field 1 1 1 1 0 0 0 1 13 12 Entry Way 54 L 210 31 Data field Longword data L : Longword specification bits : Reserved bits (0 write value, undefined read value) 0 Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry specification. In RAM mode (CCR.ORA = 1), the OC's address arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. For details about address mapping, see section 4.6.5. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the way and the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the way and the entry set in the address field. The A bit in the address field should be cleared to 0. Rev. 6.0, 07/02, page 119 of 986 When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set by bit [14] is not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit for that way is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If an UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 31 24 23 Address field 1 1 1 1 0 1 0 0 15 14 13 Entry Way 31 Data field Tag V : Validity bit U : Dirty bit A : Association bit : Reserved bits (0 write value, undefined read value) 10 9 210 UV 543210 A Figure 4.14 Memory-Mapped OC Address Array 4.6.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry specification. In RAM mode (CCR.ORA = 1), the OC's data arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. For details about address mapping, see section 4.6.5. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. Rev. 6.0, 07/02, page 120 of 986 The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the way and entry set in the address field. This write does not set the U bit to 1 on the address array side. 31 24 23 15 14 13 Entry Way Longword data L : Longword specification bits : Reserved bits (0 write value, undefined read value) 54 L 210 Address field 1 1 1 1 0 1 0 1 31 Data field 0 Figure 4.15 Memory-Mapped OC Data Array 4.6.5 Summary of the Memory-Mapping of the OC The address ranges to which the OC is memory-mapped in the double-sized cache mode of the SH7750R are summarized below, using examples of data-array access. * In normal mode (CCR.ORA = 0) H'F500 0000 to H'F500 3FFF (16 kB ): Way 0 (entries 0 to 511) H'F500 4000 to H'F500 7FFF (16 kB ): Way 1 (entries 0 to 511) : : : In the same pattern, shadows of the cache area are created in 32-kbyte blocks until H'F5FF FFFF. * In RAM mode (CCR. ORA = 1) H'F500 0000 to H'F500 1FFF (8 kB ): Way 0 (entries 0 to 255) H'F500 2000 to H'F500 3FFF (8 kB ): Way 1 (entries 0 to 255) : : : In the same pattern, shadows of the cache area are created in 16-kbyte blocks until H'F5FF FFFF. Rev. 6.0, 07/02, page 121 of 986 4.7 Store Queues The SH7750 Series supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. In the SH7750S or SH7750R, if the SQs are not used the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 9, PowerDown Modes, for the procedure for stopping SQ functions. 4.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store queues can be set independently. SQ0 SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7] SQ1 SQ1[0] 4B SQ1[1] 4B SQ1[2] 4B SQ1[3] 4B SQ1[4] 4B SQ1[5] 4B SQ1[6] 4B SQ1[7] 4B Figure 4.16 Store Queue Configuration 4.7.2 SQ Writes A write to the SQs can be performed using a store instruction (MOV) on P4 area H'E000 0000 to H'E3FF FFFC. A longword or quadword access size can be used. The meaning of the address bits is as follows: [31:26]: [25:6]: [5]: [4:2]: [1:0] 4.7.3 111000 Don't care 0/1 LW specification 00 Store queue specification Used for external memory transfer/access right 0: SQ0 specification 1: SQ1 specification Specifies longword position in SQ0/SQ1 Fixed at 0 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. While the contents of one SQ are being transferred to external Rev. 6.0, 07/02, page 122 of 986 memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. The SQ transfer destination external memory address bit [28:0] specification is as shown below, according to whether the MMU is on or off. * When MMU is on The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer destination external memory address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same meaning as for normal address translation, but the C and WT bits have no meaning with regard to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits also have no meaning. When a prefetch instruction is issued for the SQ area, address translation is performed and external memory address bits [28:10] are generated in accordance with the SZ bit specification. For external memory address bits [9:5], the address prior to address translation is generated in the same way as when the MMU is off. External memory address bits [4:0] are fixed at 0. Transfer from the SQs to external memory is performed to this address. * When MMU is off The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address to issue a PREF instruction. The meaning of address bits [31:0] is as follows: [31:26]: [25:6]: [5]: [4:2]: [1:0] 111000 Address 0/1 Don't care 00 Store queue specification External memory address bits [25:6] 0: SQ0 specification 1: SQ1 specification and external memory address bit [5] No meaning in a prefetch Fixed at 0 External memory address bits [28:26], which cannot be generated from the above address, are generated from the QACR0/1 registers. QACR0 [4:2]: QACR1 [4:2]: External memory address bits [28:26] corresponding to SQ0 External memory address bits [28:26] corresponding to SQ1 External memory address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. In the SH7750, data transfer to a PCMCIA interface area cannot be performed using an SQ. In the SH7750S or SH7750R, data transfer to a PCMCIA interface area is always performed using the SA and TC bits in the PTEA register. Rev. 6.0, 07/02, page 123 of 986 4.7.4 SQ Protection Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. In the SH7750 or SH7750S, if an exception occurs in an SQ write, the SQ contents may be corrupted. In the SH7750R, original SQ contents are guaranteed. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted. * When MMU is on Operation is in accordance with the address translation information recorded in the UTLB, and MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read type for transfer from the SQs to external memory (PREF instruction), and a TLB miss exception, protection violation exception, or initial page write exception is generated. However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address error will be flagged in user mode even if address translation is successful. * When MMU is off Operation is in accordance with MMUCR.SQMD. 0: Privileged/user access possible 1: Privileged access possible If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will be flagged. 4.7.5 Reading the SQs (SH7750R Only) In the SH7750R, a load instruction may be executed in the privileged mode to read the contents of the SQs from the address range of H'FF001000 to H'FF00103C in the P4 area. Only longword access is possible. [31:6] [5] [4:2] [1:0] : H'FF001000 : 0/1 : LW specification : 00 : Store queue specification : 0: SQ0 specification, 1: SQ1 specification : Specification of longword position in SQ0 or SQ1 : Fixed at 0 Rev. 6.0, 07/02, page 124 of 986 4.7.6 SQ Usage Notes If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7750 and SH7750S, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs. This may be due to the bug described in (1) or (2) below. (1) When SQ data is transferred to external memory within a normal program If a PREF instruction for transfer from an SQ to external memory is included in the three instructions preceding an SQ store instruction, the SQ is updated because the SQ write that should be suppressed when a branch is made to the exception handling routine is executed, and after returning from the exception handling routine the execution order of the PREF instruction and SQ store instruction is reversed, so that erroneous data may be transferred to external memory. (2) When SQ data is transferred to external memory in an exception handling routine If store queue contents are transferred to external memory within an exception handling routine, erroneous data may be transferred to external memory. Example 1: When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ to external memory PREF instruction ; PREF instruction for transfer from SQ to external memory ; Address of this instruction is saved to SPC when exception occurs. ; Instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling routine. Instruction 1 ; May be executed if an SQ store instruction. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; Not executed even if an SQ store instruction. Example 2: When an instruction that generates an exception branches using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if instruction 1 is a delay slot instruction and an instruction to store data to SQ. Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7 (branch destination of instruction 1) ; May be executed if an SQ access instruction. Instruction 8 ; May be executed if an SQ store instruction. Rev. 6.0, 07/02, page 125 of 986 Example 3: When an instruction that generates an exception does not branch using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; May be executed if an SQ store instruction. Instruction 5 To recover from this problem it is necessary that conditions A and B be satisfied. A: After the PREF instruction to transfer data from the store queue (SQ0, SQ1) to external memory, a store instruction for the same store queue must be executed, and conditions (1) and (2) below must be satisfied. 1 (1) Three NOP instructions* must be inserted between the above two instructions. (2) There must not be a PREF instruction to transfer data from the store queue to external memory in the delay slot of the branch instruction. B: There must be no PREF instruction to transfer data from the store queue to external memory executed in the exception handling routine. If such an instruction is executed, and if there is a store to the store queue instruction among 2 the four instructions* at the address referred to by SPC, the data transferred to external memory by the PREF instruction may indicate that execution of the store instruction has completed. Notes: *1 If there are other instructions between the above two instructions, the problem can be avoided if the other instructions and NOP instructions together total three or more instructions. *2 If the instruction at the address referred to by SPC is a branch instruction the two instructions at the branch destination may be affected. Rev. 6.0, 07/02, page 126 of 986 Section 5 Exceptions 5.1 5.1.1 Overview Features Exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing. The process of generating an exception handling request in response to abnormal termination, and passing control to a user-written exception handling routine, in order to support such functions, is given the generic name of exception handling. SH7750 Series exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1. Table 5.1 Name TRAPA exception register Exception event register Interrupt event register Exception-Related Registers Abbreviation R/W TRA EXPEVT INTEVT R/W R/W R/W Initial Value* Undefined H'0000 0000/ 1 H'0000 0020* Undefined 1 P4 2 Address* Area 7 2 Address* Access Size H'FF00 0020 H'1F00 0020 32 H'FF00 0024 H'1F00 0024 32 H'FF00 0028 H'1F00 0028 32 Notes: *1 H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset. *2 This is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. Rev. 6.0, 07/02, page 127 of 986 5.2 Register Descriptions There are three registers related to exception handling. Addresses are allocated to these registers, and they can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software. 2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 12bit exception code. The exception code set in INTEVT is that for an interrupt request. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. 3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1. EXPEVT and INTEVT 31 0 TRA 31 0 10 9 0 imm 210 00 12 11 0 Exception code 0 0: Reserved bits. These bits are always read as 0, and should only be written with 0. imm: 8-bit immediate data of the TRAPA instruction Figure 5.1 Register Bit Configurations Rev. 6.0, 07/02, page 128 of 986 5.3 5.3.1 Exception Handling Functions Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception. The exception handling routine is terminated and control returned to the original program by executing a return-from-exception instruction (RTE). This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred. The SGR contents are not written back to R15 by an RTE instruction. The basic processing flow is as follows. See section 2, Data Formats and Registers, for the meaning of the individual SR bits. 1. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR. 2. The block bit (BL) in SR is set to 1. 3. The mode bit (MD) in SR is set to 1. 4. The register bank bit (RB) in SR is set to 1. 5. In a reset, the FPU disable bit (FD) in SR is cleared to 0. 6. The exception code is written to bits 11-0 of the exception event register (EXPEVT) or interrupt event register (INTEVT). 7. The CPU branches to the determined exception handling vector address, and the exception handling routine begins. 5.3.2 Exception Handling Vector Addresses The reset vector address is fixed at H'A000 0000. Exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (VBR). In the case of the TLB miss exception, for example, the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses (P1, P2) should be specified for vector addresses. Rev. 6.0, 07/02, page 129 of 986 5.4 Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Priority Priority Vector Level Order Address 1 1 1 1 1 2 1 3 4 0 1 2 3 4 4 4 4 5 5 6 6 7 7 8 9 4 10 Offset Exception Code H'000 H'020 H'000 H'140 H'140 Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset H-UDI reset Instruction TLB multiple-hit exception H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- (VBR/DBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR/DBR) Data TLB multiple-hit exception 1 General exception ReUser break before instruction 1 execution execution* type Instruction address error Instruction TLB miss exception Instruction TLB protection violation exception General illegal instruction exception 2 2 2 2 2 H'100/-- H'1E0 H'100 H'400 H'100 H'100 H'100 H'100 H'100 H'100 H'100 H'400 H'400 H'100 H'100 H'100 H'100 H'100 H'0E0 H'040 H'0A0 H'180 H'1A0 H'800 H'820 H'0E0 H'100 H'040 H'060 H'0A0 H'0C0 H'120 H'080 H'160 Slot illegal instruction exception 2 General FPU disable exception 2 Slot FPU disable exception Data address error (read) Data address error (write) 2 2 2 Data TLB miss exception (read) 2 Data TLB miss exception (write) 2 Data TLB protection violation exception (read) Data TLB protection violation exception (write) FPU exception Initial page write exception Completion Unconditional trap (TRAPA) type User break after instruction 1 execution* 2 2 2 2 2 2 H'100/-- H'1E0 Rev. 6.0, 07/02, page 130 of 986 Table 5.2 Exceptions (cont) Priority Priority Vector Level Order Address 3 4 -- *2 (VBR) (VBR) Offset H'600 H'600 Exception Code H'1C0 H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 *2 (VBR) H'600 H'400 H'420 H'440 H'460 H'B00 H'B80 H'480 H'4A0 H'4C0 H'4E0 H'500 H'520 H'540 H'560 H'580 H'5A0 H'600 H'620 Exception Execution Category Mode Exception Interrupt Completion Nonmaskable interrupt type External IRL3-IRL0 0 interrupts 1 2 3 4 5 6 7 8 9 A B C D E Peripheral TMU0 module TMU1 interrupt (module/ TMU2 source) TMU3 TMU4 RTC TUNI0 4 TUNI1 TUNI2 TICPI2 TUNI3 TUNI4 ATI PRI CUI SCI ERI RXI TXI TEI WDT REF ITI RCMI ROVI H-UDI GPIO H-UDI GPIOI Rev. 6.0, 07/02, page 131 of 986 Table 5.2 Exceptions (cont) Priority Priority Vector Level Order Address DMTE0 4 DMTE1 DMTE2 DMTE3 DMTE4 *3 DMTE5 *3 DMTE6 *3 DMTE7 *3 DMAE SCIF ERI RXI BRI TXI *2 (VBR) Offset H'600 Exception Code H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 H'700 H'720 H'740 H'760 Exception Execution Category Mode Exception Interrupt Completion Peripheral DMAC type module interrupt (module/ source) Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases. Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt. IRL: Interrupt request level (pins IRL3-IRL0). Module/source: See the sections on the relevant peripheral modules. Notes: *1 When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100. *2 The priority order of external interrupts and peripheral module interrupts can be set by software. *3 SH7750R only. 5.5 5.5.1 Exception Flow Exception Flow Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an Rev. 6.0, 07/02, page 132 of 986 exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers may be set automatically by hardware, depending on the exception. For details, see section 5.6, Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, and in the case of instructions in which two data accesses are performed. Reset requested? No Execute next instruction Yes General exception requested? No Interrupt requested? No Yes Is highestYes priority exception re-exception type? Cancel instruction execution No result Yes SSR SR SPC PC SGR R15 EXPEVT/INTEVT exception code SR.{MD,RB,BL} 111 PC (BRCR.UBDE=1 && User_Break? DBR: (VBR + Offset)) EXPEVT exception code SR. {MD, RB, BL, FD, IMASK} 11101111 PC H'A000 0000 Figure 5.2 Instruction Execution and Exception Handling 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions--the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception--are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These exceptions therefore all have the same priority. General exceptions are detected in the order of instruction execution. However, exception handling is performed in the order of instruction flow (program order). Thus, an exception for an earlier instruction is accepted before that for a later instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3. Rev. 6.0, 07/02, page 133 of 986 Pipeline flow: Instruction n Instruction n+1 IF IF ID ID EX EX TLB miss (data access) MA WB MA WB General illegal instruction exception TLB miss (instruction access) IF ID EX MA WB IF: ID: EX: MA: WB: Instruction fetch Instruction decode Instruction execution Memory access Write-back Instruction n+2 Instruction n+3 IF ID EX MA WB Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling: TLB miss (instruction n) 1 Re-execution of instruction n General illegal instruction exception (instruction n+1) 2 Re-execution of instruction n+1 Program order TLB miss (instruction n+2) 3 Re-execution of instruction n+2 4 Execution of instruction n+3 Figure 5.3 Example of General Exception Acceptance Order Rev. 6.0, 07/02, page 134 of 986 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in the event of a user break, see section 20, User Break Controller. If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable multiple exception state acceptance. 5.5.4 Return from Exception Handling The RTE instruction is used to return from exception handling. When the RTE instruction is executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns from the exception handling routine by branching to the SPC address. If SPC and SSR were saved to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and issuing the RTE instruction. 5.6 Description of Exceptions The various exception handling operations are described here, covering exception sources, transition addresses, and processor operation when a transition is made. Rev. 6.0, 07/02, page 135 of 986 5.6.1 Resets (1) Power-On Reset * Sources: SCK2 pin high level and 5(6(7 pin low level When the watchdog timer overflows while the WT/,7 bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. * Transition address: H'A000 0000 * Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3-I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. For some CPU functions, the 7567 pin and 5(6(7 pin must be driven low. It is therefore essential to execute a power-on reset and drive the 7567 pin low when powering on. If the SCK2 pin is changed to the low level while the 5(6(7 pin is low, a manual reset may occur after the power-on reset operation. Do not drive the SCK2 pin low during this interval (see figure 22.3). Power_on_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD=0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } Rev. 6.0, 07/02, page 136 of 986 (2) Manual Reset * Sources: SCK2 pin low level and 5(6(7 pin low level When a general exception other than a user break occurs while the BL bit is set to 1 in SR When the watchdog timer overflows while the WT/,7 bit and RSTS bit are both set to 1 in WTCSR. For details, see section 10, Clock Oscillation Circuits. * Transition address: H'A000 0000 * Transition operations: Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3-I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. Manual_reset() { EXPEVT = H'00000020; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Table 5.3 Types of Reset Reset State Transition Conditions Internal States CPU Initialized Initialized On-Chip Peripheral Modules See Register Configuration in each section Type Power-on reset Manual reset SCK2 High Low 5(6(7 Low Low Rev. 6.0, 07/02, page 137 of 986 (3) H-UDI Reset * Source: SDIR.TI3-TI0 = B'0110 (negation) or B'0111 (assertion) * Transition address: H'A000 0000 * Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3-I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. H-UDI_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } Rev. 6.0, 07/02, page 138 of 986 (4) Instruction TLB Multiple-Hit Exception * Source: Multiple ITLB address matches * Transition address: H'A000 0000 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3-I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Rev. 6.0, 07/02, page 139 of 986 (5) Operand TLB Multiple-Hit Exception * Source: Multiple UTLB address matches * Transition address: H'A000 0000 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3-I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Rev. 6.0, 07/02, page 140 of 986 5.6.2 General Exceptions (1) Data TLB Miss Exception * Source: Address mismatch in UTLB address comparison * Transition address: VBR + H'0000 0400 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. Data_TLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'00000040 : H'00000060; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } Rev. 6.0, 07/02, page 141 of 986 (2) Instruction TLB Miss Exception * Source: Address mismatch in ITLB address comparison * Transition address: VBR + H'0000 0400 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. ITLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000040; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } Rev. 6.0, 07/02, page 142 of 986 (3) Initial Page Write Exception * Source: TLB is hit in a store access, but dirty bit D = 0 * Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Initial_write_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000080; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 143 of 986 (4) Data TLB Protection Violation Exception * Source: The access does not accord with the UTLB protection information (PR bits) shown below. PR 00 01 10 11 Privileged Mode Only read access possible Read/write access possible Only read access possible Read/write access possible User Mode Access not possible Access not possible Only read access possible Read/write access possible * Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Data_TLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'000000A0 : H'000000C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 144 of 986 (5) Instruction TLB Protection Violation Exception * Source: The access does not accord with the ITLB protection information (PR bits) shown below. PR 0 1 Privileged Mode Access possible Access possible User Mode Access not possible Access possible * Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 145 of 986 (6) Data Address Error * Sources: Word data access from other than a word boundary (2n +1) Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) Access to area H'8000 0000-H'FFFF FFFF in user mode * Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Data_address_error() { TEA = EXCEPTION_ADDRESS; PTEN.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access? H'000000E0: H'00000100; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 146 of 986 (7) Instruction Address Error * Sources: Instruction fetch from other than a word boundary (2n +1) Instruction fetch from area H'8000 0000-H'FFFF FFFF in user mode * Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Instruction_address_error() { TEA = EXCEPTION_ADDRESS; PTEN.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 147 of 986 (8) Unconditional Trap * Source: Execution of TRAPA instruction * Transition address: VBR + H'0000 0100 * Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. TRAPA_exception() { SPC = PC + 2; SSR = SR; SGR = R15; TRA = imm << 2; EXPEVT = H'00000160; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 148 of 986 (9) General Illegal Instruction Exception * Sources: Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR * Transition address: VBR + H'0000 0100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'180 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other than H'FFFD is decoded. General_illegal_instruction_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000180; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 149 of 986 (10) Slot Illegal Instruction Exception * Sources: Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR Decoding in user mode of a privileged instruction in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot * Transition address: VBR + H'0000 0100 * Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR. Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other than H'FFFD is decoded. Slot_illegal_instruction_exception() { SPC = PC - 2; SSR = SR; SGR = R15; EXPEVT = H'000001A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 150 of 986 (11) General FPU Disable Exception * Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 * Transition address: VBR + H'0000 0100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are F (but excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L instructions corresponding to FPUL and FPSCR. General_fpu_disable_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000800; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 151 of 986 (12) Slot FPU Disable Exception * Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 * Transition address: VBR + H'0000 0100 * Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR. Exception code H'820 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Slot_fpu_disable_exception() { SPC = PC - 2; SSR = SR; SGR = R15; EXPEVT = H'00000820; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 152 of 986 (13) User Breakpoint Trap * Source: Fulfilling of a break condition set in the user break controller * Transition address: VBR + H'0000 0100, or DBR * Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC. In the case of a pre-execution break, the PC contents for the instruction at which the breakpoint is set are set in SPC. The SR and R15 contents when the break occurred are saved in SSR and SGR. Exception code H'1E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. It is also possible to branch to PC = DBR. For details of PC, etc., when a data break is set, see section 20, User Break Controller (UBC). User_break_exception() { SPC = (pre_execution break? PC : PC + 2); SSR = SR; SGR = R15; EXPEVT = H'000001E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = (BRCR.UBDE==1 ? DBR : VBR + H'00000100); } Rev. 6.0, 07/02, page 153 of 986 (14) FPU Exception * Source: Exception due to execution of a floating-point operation * Transition address: VBR + H'0000 0100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'120 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. FPU_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000120; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 6.0, 07/02, page 154 of 986 5.6.3 (1) NMI Interrupts * Source: NMI pin edge detection * Transition address: VBR + H'0000 0600 * Transition operations: The contents of PC and SR immediately after the instruction at which this interrupt was accepted are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or accepted. For details, see section 19, Interrupt Controller (INTC). NMI() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'000001C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000600; } Rev. 6.0, 07/02, page 155 of 986 (2) IRL Interrupts * Source: The interrupt mask bit setting in SR is smaller than the IRL (3-0) level, and the BL bit in SR is 0 (accepted at instruction boundary). * Transition address: VBR + H'0000 0600 * Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR. The code corresponding to the IRL (3-0) level is set in INTEVT. See table 19.5, Interrupt Exception Handling Sources and Priority Order, for the corresponding codes. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. The acceptance level is not set in the interrupt mask bits in SR. When the BL bit in SR is 1, the interrupt is masked. For details, see section 19, Interrupt Controller (INTC). IRL() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'00000200 ~ H'000003C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000600; } Rev. 6.0, 07/02, page 156 of 986 (3) Peripheral Module Interrupts * Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary). * Transition address: VBR + H'0000 0600 * Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR. The code corresponding to the interrupt source is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. The module interrupt levels should be set as values between B'0000 and B'1111 in the interrupt priority registers (IPRA-IPRC) in the interrupt controller. For details, see section 19, Interrupt Controller (INTC). Module_interruption() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'00000400 ~ H'B80; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000600; } Rev. 6.0, 07/02, page 157 of 986 5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order. 1. Instructions that make two accesses to memory With MAC instructions, memory-to-memory arithmetic/logic instructions, and TAS instructions, two data transfers are performed by a single instruction, and an exception will be detected for each of these data transfers. In these cases, therefore, the following order is used to determine priority. a. Data address error in first data transfer b. TLB miss in first data transfer c. TLB protection violation in first data transfer d. Initial page write exception in first data transfer e. Data address error in second data transfer f. TLB miss in second data transfer g. TLB protection violation in second data transfer h. Initial page write exception in second data transfer 2. Indivisible delayed branch instruction and delay slot instruction As a delayed branch instruction and its associated delay slot instruction are indivisible, they are treated as a single instruction. Consequently, the priority order for exceptions that occur in these instructions differs from the usual priority order. The priority order shown below is for the case where the delay slot instruction has only one data transfer. a. A check is performed for the interrupt type and reexecution type exceptions of priority levels 1 and 2 in the delayed branch instruction. b. A check is performed for the interrupt type and reexecution type exceptions of priority levels 1 and 2 in the delay slot instruction. c. A check is performed for the completion type exception of priority level 2 in the delayed branch instruction. d. A check is performed for the completion type exception of priority level 2 in the delay slot instruction. e. A check is performed for priority level 3 in the delayed branch instruction and priority level 3 in the delay slot instruction. (There is no priority ranking between these two.) f. A check is performed for priority level 4 in the delayed branch instruction and priority level 4 in the delay slot instruction. (There is no priority ranking between these two.) If the delay slot instruction has a second data transfer, two checks are performed in step b, as in 1 above. Rev. 6.0, 07/02, page 158 of 986 If the accepted exception (the highest-priority exception) is a delay slot instruction reexecution type exception, the branch instruction PR register write operation (PC PR operation performed in BSR, BSRF, JSR) is inhibited. 5.7 Usage Notes 1. Return from exception handling a. Check the BL bit in SR with software. If SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR contents are set in SR, and branch is made to the SPC address to return from the exception handling routine. 2. If an exception or interrupt occurs when SR.BL = 1 a. Exception When an exception other than a user break occurs, a manual reset is executed. The value in EXPEVT at this time is H'0000 0020; the value of the SPC and SSR registers is undefined. b. Interrupt If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. In the sleep or standby state, however, an interrupt is accepted even if the BL bit in SR is set to 1. 3. SPC when an exception occurs a. Re-execution type exception The PC value for the instruction in which the exception occurred is set in SPC, and the instruction is re-executed after returning from exception handling. If an exception occurs in a delay slot instruction, however, the PC value for the delay slot instruction is saved in SPC regardless of whether or not the preceding delay slot instruction condition is satisfied. b. Completion type exception or interrupt The PC value for the instruction following that in which the exception occurred is set in SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value for the branch destination is saved in SPC. 4. An exception must not be generated in an RTE instruction delay slot, as the operation will be undefined in this case. Rev. 6.0, 07/02, page 159 of 986 5.8 Restrictions 1. Restrictions on first instruction of exception handling routine * Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600. * When the UBDE bit in the BRCR register is set to 1 and the user break debug support function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by the DBR register. Note: * See section 20.4, User Break Debug Support Function. Rev. 6.0, 07/02, page 160 of 986 Section 6 Floating-Point Unit 6.1 Overview The floating-point unit (FPU) has the following features: * Conforms to IEEE754 standard * 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) * Two rounding modes: Round to Nearest and Round to Zero * Two denormalization modes: Flush to Zero and Treat Denormalized Number * Six exception sources: FPU Error, Invalid Operation, Divide By Zero, Overflow, Underflow, and Inexact * Comprehensive instructions: Single-precision, double-precision, graphics support, system control When the FD bit in SR is set to 1, the FPU cannot be used, and an attempt to execute an FPU instruction will cause an FPU disable exception. 6.2 6.2.1 Data Formats Floating-Point Format A floating-point number consists of the following three fields: * Sign (s) * Exponent (e) * Fraction (f) The SH7750 Series can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 31 30 s e 23 22 f 0 Figure 6.1 Format of Single-Precision Floating-Point Number Rev. 6.0, 07/02, page 161 of 986 63 62 s e 52 51 f 0 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is Emin - 1 to Emax + 1. The two values Emin - 1 and Emax + 1 are distinguished as follows. Emin - 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). Table 6.1 shows bias, Emin, and Emax values. Table 6.1 Parameter Total bit width Sign bit Exponent field Fraction field Precision Bias Emax Emin Floating-Point Number Formats and Parameters Single-Precision 32 bits 1 bit 8 bits 23 bits 24 bits +127 +127 -126 Double-Precision 64 bits 1 bit 11 bits 52 bits 53 bits +1023 +1023 -1022 Floating-point number value v is determined as follows: If E = Emax + 1 and f 0, v is a non-number (NaN) irrespective of sign s s If E = Emax + 1 and f = 0, v = (-1) (infinity) [positive or negative infinity] sE If Emin E Emax , v = (-1) 2 (1.f) [normalized number] s Emin If E = Emin - 1 and f 0, v = (-1) 2 (0.f) [denormalized number] s If E = Emin - 1 and f = 0, v = (-1) 0 [positive or negative zero] Table 6.2 shows the ranges of the various numbers in hexadecimal notation. Rev. 6.0, 07/02, page 162 of 986 Table 6.2 Type Floating-Point Ranges Single-Precision H'7FFFFFFF to H'7FC00000 H'7FBFFFFF to H'7F800001 H'7F800000 H'7F7FFFFF to H'00800000 H'007FFFFF to H'00000001 H'00000000 H'80000000 H'80000001 to H'807FFFFF H'80800000 to H'FF7FFFFF H'FF800000 H'FF800001 to H'FFBFFFFF H'FFC00000 to H'FFFFFFFF Double-Precision H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 H'7FF00000 00000 H'7FEFFFFF FFFFFFFF to H'00100000 00000000 H'000FFFFF FFFFFFFF to H'00000000 00000001 H'00000000 00000000 H'80000000 00000000 H'80000000 00000001 to H'800FFFFF FFFFFFFF H'80100000 00000000 to H'FFEFFFFF FFFFFFFF H'FFF00000 00000000 H'FFF00000 00000001 to H'FFF7FFFF FFFFFFFF H'FFF80000 00000000 to H'FFFFFFFF FFFFFFFF Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized number Negative infinity Quiet non-number Signaling non-number 6.2.2 Non-Numbers (NaN) Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: * Sign bit: Don't care * Exponent field: All bits are 1 * Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0. Rev. 6.0, 07/02, page 163 of 986 31 30 x 11111111 23 22 Nxxxxxxxxxxxxxxxxxxxxxx 0 N = 1: sNaN N = 0: qNaN Figure 6.3 Single-Precision NaN Bit Pattern An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value. * When the EN.V bit in the FPSCR register is 0, the operation result (output) is a qNaN. * When the EN.V bit in the FPSCR register is 1, an invalid operation exception will be generated. In this case, the contents of the operation destination register are unchanged. If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit in the FPSCR register. An exception will not be generated in this case. The qNAN values generated by the SH7750 Series as operation results are as follows: * Single-precision qNaN: H'7FBFFFFF * Double-precision qNaN: H'7FF7FFFF FFFFFFFF See the individual instruction descriptions for details of floating-point operations when a nonnumber (NaN) is input. 6.2.3 Denormalized Numbers For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. When the DN bit in the FPU's status register FPSCR is 1, a denormalized number (source operand or operation result) is always flushed to 0 in a floating-point operation that generates a value (an operation other than copy, FNEG, or FABS). When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is processed as it is. See the individual instruction descriptions for details of floating-point operations when a denormalized number is input. Rev. 6.0, 07/02, page 164 of 986 6.3 6.3.1 Registers Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floatingpoint registers, referenced by specifying FR0-FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0- XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0-FPR15_BANK0 FPR0_BANK1-FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0-FR15 indicate FPR0_BANK0-FPR15_BANK0; when FPSCR.FR = 1, FR0-FR15 indicate FPR0_BANK1-FPR15_BANK1. 3. Double-precision floating-point registers, DRi (8 registers): A DR register comprises two FR registers DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} 4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} 5. Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0-XF15 indicate FPR0_BANK1-FPR15_BANK1; when FPSCR.FR = 1, XF0-XF15 indicate FPR0_BANK0-FPR15_BANK0. 6. Double-precision floating-point extended registers, XDi (8 registers): An XD register comprises two XF registers XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} 7. Single-precision floating-point extended register matrix: XMTRX XMTRX comprises all 16 XF registers XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 Rev. 6.0, 07/02, page 165 of 986 FPSCR.FR = 0 FV0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 DR0 XF0 XF1 XD2 XF2 XF3 XD4 XF4 XF5 XD6 XF6 XF7 XD8 XF8 XF9 XD10 XF10 XF11 XD12 XF12 XF13 XD14 XF14 XF15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 FPSCR.FR = 1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XMTRX FV4 FV8 FV12 XMTRX XD0 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 Figure 6.4 Floating-Point Registers Rev. 6.0, 07/02, page 166 of 986 6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 31 -- 22 21 20 19 18 17 FR SZ PR DN Cause 12 11 Enable 7 6 Flag 2 1 RM 0 Note: --: Reserved. These bits are always read as 0, and should only be written with 0. * FR: Floating-point register bank FR = 0: FPR0_BANK0-FPR15_BANK0 are assigned to FR0-FR15; FPR0_BANK1- FPR15_BANK1 are assigned to XF0-XF15. FR = 1: FPR0_BANK0-FPR15_BANK0 are assigned to XF0-XF15; FPR0_BANK1- FPR15_BANK1 are assigned to FR0-FR15. * SZ: Transfer size mode SZ = 0: The data size of the FMOV instruction is 32 bits. SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits). * PR: Precision mode PR = 0: Floating-point instructions are executed as single-precision operations. PR = 1: Floating-point instructions are executed as double-precision operations (graphics support instructions are undefined). Do not set SZ and PR to 1 simultaneously; this setting is reserved. [SZ, PR = 11]: Reserved (FPU operation instruction is undefined.) * DN: Denormalization mode DN = 0: A denormalized number is treated as such. DN = 1: A denormalized number is treated as zero. * Cause: FPU exception cause field * Enable: FPU exception enable field * Flag: FPU exception flag field FPU Error (E) Cause Enable Flag FPU exception cause field FPU exception enable field FPU exception flag field Bit 17 None None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2 Rev. 6.0, 07/02, page 167 of 986 When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared. * RM: Rounding mode RM = 00: Round to Nearest RM = 01: Round to Zero RM = 10: Reserved RM = 11: Reserved * Bits 22 to 31: Reserved These bits are always read as 0, and should only be written with 0. 6.3.3 Floating-Point Communication Register (FPUL) Information is transferred between the FPU and CPU via the FPUL register. The 32-bit FPUL register is a system register, and is accessed from the CPU side by means of LDS and STS instructions. For example, to convert the integer stored in general register R1 to a single-precision floating-point number, the processing flow is as follows: R1 (LDS instruction) FPUL (single-precision FLOAT instruction) FR1 6.4 Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL. There are two rounding methods, the method to be used being determined by the RM field in FPSCR. * RM = 00: Round to Nearest * RM = 01: Round to Zero Round to Nearest: The value is rounded to the nearest expressible value. If there are two nearest expressible values, the one with an LSB of 0 is selected. If the unrounded value is 2 (2 - 2 ) or more, the result will be infinity with the same sign as the unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. Emax -P Rev. 6.0, 07/02, page 168 of 986 Round to Zero: The digits below the round bit of the unrounded value are discarded. If the unrounded value is larger than the maximum expressible absolute value, the value will be the maximum expressible absolute value. 6.5 Floating-Point Exceptions FPU-related exceptions are as follows: * General illegal instruction/slot illegal instruction exception The exception occurs if an FPU instruction is executed when SR.FD = 1. * FPU exceptions The exception sources are as follows: FPU error (E): When FPSCR.DN = 0 and a denormalized number is input Invalid operation (V): In case of an invalid operation, such as NaN input Division by zero (Z): Division with a zero divisor Overflow (O): When the operation result overflows Underflow (U): When the operation result underflows Inexact exception (I): When overflow, underflow, or rounding occurs The FPSCR cause field contains bits corresponding to all of above sources E, V, Z, O, U, and I, and the FPSCR flag and enable fields contain bits corresponding to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled. When an exception source occurs, the corresponding bit in the cause field is set to 1, and 1 is added to the corresponding bit in the flag field. When an exception source does not occur, the corresponding bit in the cause field is cleared to 0, but the corresponding bit in the flag field remains unchanged. * Enable/disable exception handling The SH7750 Series supports enable exception handling and disable exception handling. Enable exception handling is initiated in the following cases: FPU error (E): FPSCR.DN = 0 and a denormalized number is input Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation) Division by zero (Z): FPSCR.EN.Z = 1 and division with a zero divisor Overflow (O): FPSCR.EN.O = 1 and instruction with possibility of operation result overflow Underflow (U): FPSCR.EN.U = 1 and instruction with possibility of operation result underflow Inexact exception (I): FPSCR.EN.I = 1 and instruction with possibility of inexact operation result Rev. 6.0, 07/02, page 169 of 986 These possibilities are shown in the individual instruction descriptions. All exception events that originate in the FPU are assigned as the same exception event. The meaning of an exception is determined by software by reading system register FPSCR and interpreting the information it contains. If no bits are set in the cause field of FPSCR when one or more of bits O, U, I, and V (in case of FTRV only) are set in the enable field, this indicates that an actual exception source is not generated. Also, the destination register is not changed by any enable exception handling operation. Except for the above, the FPU disables exception handling. In all processing, the bit corresponding to source V, Z, O, U, or I is set to 1, and disable exception handling is provided for each exception. Invalid operation (V): qNAN is generated as the result. Division by zero (Z): Infinity with the same sign as the unrounded value is generated. Overflow (O): When rounding mode = RZ, the maximum normalized number, with the same sign as the unrounded value, is generated. When rounding mode = RN, infinity with the same sign as the unrounded value is generated. Underflow (U): When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value, or zero with the same sign as the unrounded value, is generated. When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated. Inexact exception (I): An inexact result is generated. 6.6 Graphics Support Functions The SH7750 Series supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value computations. To enable high-speed computation with a minimum of hardware, the SH7750 Series ignores comparatively small values in the partial computation results of four multiplications. Consequently, the error shown below is produced in the result of the computation: Maximum error = MAX (individual multiplication result x -MIN (number of multiplier significant digits-1, number of multiplicand significant digits-1) -23 -149 2 ) + MAX (result value x 2 , 2 ) The number of significant digits is 24 for a normalized number and 23 for a denormalized number (number of leading zeros in the fractional part). Rev. 6.0, 07/02, page 170 of 986 In future version of SH series, the above error is guaranteed, but the same result as SH7750 is not guaranteed. FIPR FVm, FVn (m, n: 0, 4, 8, 12): This instruction is basically used for the following purposes: * Inner product (m n): This operation is generally used for surface/rear surface determination for polygon surfaces. * Sum of square of elements (m = n): This operation is generally used to find the length of a vector. Since approximate-value computations are performed to enable high-speed computation, the inexact exception (I) bit in the cause field and flag field is always set to 1 when an FIPR instruction is executed. Therefore, if the corresponding bit is set in the enable field, enable exception handling will be executed. FTRV XMTRX, FVn (n: 0, 4, 8, 12): This instruction is basically used for the following purposes: * Matrix (4 x 4) vector (4): This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 x 4 matrix, the SH7750 Series supports 4-dimensional operations. * Matrix (4 x 4) x matrix (4 x 4): This operation requires the execution of four FTRV instructions. Since approximate-value computations are performed to enable high-speed computation, the inexact exception (I) bit in the cause field and flag field is always set to 1 when an FTRV instruction is executed. Therefore, if the corresponding bit is set in the enable field, enable exception handling will be executed. For the same reason, it is not possible to check all data types in the registers beforehand when executing an FTRV instruction. If the V bit is set in the enable field, enable exception handling will be executed. FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is executed, matrix elements must be set in an array in the background bank. However, to create the actual elements of a translation matrix, it is easier to use registers in the foreground bank. When the LDC instruction is used on FPSCR, this instruction expends 4 to 5 cycles in order to maintain the FPU state. With the FRCHG instruction, an FPSCR.FR bit modification can be performed in one cycle. Rev. 6.0, 07/02, page 171 of 986 6.6.2 Pair Single-Precision Data Transfer In addition to the powerful new geometric operation instructions, the SH7750 Series also supports high-speed data transfer instructions. When FPSCR.SZ = 1, the SH7750 Series can perform data transfer by means of pair singleprecision data transfer instructions. * FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) * FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15) These instructions enable two single-precision (2 x 32-bit) data items to be transferred; that is, the transfer performance of these instructions is doubled. * FSCHG This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-precision data transfer. Programming Note: When FPSCR.SZ = 1 and big-endian mode is used, FMOV can be used for a double-precision floating-point load or store. In little-endian mode, a double-precision floating-point load or store requires execution of two 32-bit data size operations with FPSCR.SZ = 0. Rev. 6.0, 07/02, page 172 of 986 Section 7 Instruction Set 7.1 Execution Environment PC: At the start of instruction execution, PC indicates the address of the instruction itself. Data sizes and data types: The SH7750 Series' instruction set is implemented with 16-bit fixedlength instructions. The SH7750 Series can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and from memory using longword size. When a double-precision floating-point operation is specified (FPSCR.PR = 1), the result of an operation using quadword access will be undefined. When the SH7750 Series moves byte-size or word-size data from memory to a register, the data is sign-extended. Load-Store Architecture: The SH7750 Series features a load-store architecture in which operations are basically executed using registers. Except for bit-manipulation operations such as logical AND that are executed directly in memory, operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers. Delayed Branches: Except for the two branch instructions BF and BT, the SH7750 Series' branch instructions and RTE are delayed branches. In a delayed branch, the instruction following the branch is executed before the branch destination instruction. This execution slot following a delayed branch is called a delay slot. For example, the BRA execution sequence is as follows: Static Sequence BRA TARGET Dynamic Sequence BRA TARGET ADD in delay slot is executed before branching to TARGET ADD R1, R0 next_2 ADD R1, R0 target_instr Delay Slot: An illegal instruction exception may occur when a specific instruction is executed in a delay slot. See section 5, Exceptions. The instruction following BF/S or BT/S for which the branch is not taken is also a delay slot instruction. T Bit: The T bit in the status register (SR) is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below. ADD #1, R0 ; T bit is not changed by ADD operation CMP/EQ R1, R0 ; If R0 = R1, T bit is set to 1 BT TARGET ; Branches to TARGET if T bit = 1 (R0 = R1) Rev. 6.0, 07/02, page 173 of 986 In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits--S, T, M, Q, FD, BL, and RB--after modification are used for delay slot instruction execution. The STC and STC.L SR instructions access all SR bits after modification. Constant Values: An 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a PC-relative load instruction. MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn There are no PC-relative load instructions for floating-point operations. However, it is possible to set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point register. Rev. 6.0, 07/02, page 174 of 986 7.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID. See section 3, Memory Management Unit (MMU). Table 7.1 Addressing Mode Register direct Register indirect Register indirect with postincrement Addressing Modes and Effective Addresses Instruction Format Rn @Rn Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Calculation Formula -- Rn EA (EA: effective address) Rn EA After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Quadword: Rn + 8 Rn Rn @Rn+ Rn Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn + 1/2/4/8 1/2/4/8 + Rn Register indirect with predecrement @-Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn - 1/2/4/8 1/2/4/8 - Rn - 1/2/4/8 Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn Quadword: Rn - 8 Rn Rn EA (Instruction executed with Rn after calculation) Rev. 6.0, 07/02, page 175 of 986 Table 7.1 Addressing Mode Addressing Modes and Effective Addresses (cont) Instruction Format Effective Address Calculation Method Calculation Formula Byte: Rn + disp EA Word: Rn + disp x 2 EA Longword: Rn + disp x 4 EA Register @(disp:4, Rn) Effective address is register Rn contents with indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Indexed register indirect @(R0, Rn) Effective address is sum of register Rn and R0 contents. Rn + R0 Rn + R0 Rn + R0 EA GBR indirect @(disp:8, with GBR) displacement Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Byte: GBR + disp EA Word: GBR + disp x 2 EA Longword: GBR + disp x 4 EA Indexed @(R0, GBR) GBR indirect Effective address is sum of register GBR and R0 contents. GBR + R0 GBR + R0 GBR + R0 EA Rev. 6.0, 07/02, page 176 of 986 Table 7.1 Addressing Mode Addressing Modes and Effective Addresses (cont) Instruction Format Effective Address Calculation Method Calculation Formula Word: PC + 4 + disp x 2 EA Longword: PC & H'FFFFFFFC + 4 + disp x 4 EA PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC &* H'FFFFFFFC 4 + disp (zero-extended) x 2/4 * With longword operand + PC + 4 + disp x2 or PC & H'FFFFFFFC + 4 + disp x 4 PC-relative disp:8 Effective address is PC+4 with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC + 4 + disp (sign-extended) x 2 PC + 4 + disp x 2 PC + 4 + disp x 2 BranchTarget Rev. 6.0, 07/02, page 177 of 986 Table 7.1 Addressing Mode PC-relative Addressing Modes and Effective Addresses (cont) Instruction Format disp:12 Effective Address Calculation Method Effective address is PC+4 with 12-bit displacement disp added after being sign-extended and multiplied by 2. PC + 4 + disp (sign-extended) x 2 PC + 4 + disp x 2 Calculation Formula PC + 4 + disp x 2 BranchTarget Rn Effective address is sum of PC+4 and Rn. PC + 4 Rn + PC + 4 + Rn PC + 4 + Rn BranchTarget Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. -- -- -- Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed according to the operand size. This is done to clarify the operation of the chip. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative Rev. 6.0, 07/02, page 178 of 986 7.3 Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Item Instruction mnemonic Notation Used in Instruction List Format OP.Sz SRC, DEST Description OP: Sz: SRC: DEST: , : (xx): M/Q/T: &: |: Operation code Size Source Source and/or destination operand Summary of operation Transfer direction Memory operand SR flag bits Logical AND of individual bits Logical OR of individual bits : Logical exclusive-OR of individual bits ~: Logical NOT of individual bits < Instruction code Privileged mode T bit "Privileged" means the instruction can only be executed in privileged mode. Value of T bit after --: No change instruction execution Note: Scaling (x1, x2, x4, or x8) is executed according to the size of the instruction operand(s). Rev. 6.0, 07/02, page 179 of 986 Table 7.3 Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L Fixed-Point Transfer Instructions Operation #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn imm sign extension Rn (disp x 2 + PC + 4) sign extension Rn (disp x 4 + PC & H'FFFFFFFC + 4) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) sign extension Rn (Rm) sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) sign extension Rn, Rm + 1 Rm (Rm) sign extension Rn, Rm + 2 Rm (Rm) Rn, Rm + 4 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) sign extension R0 (disp x 2 + Rm) sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) sign extension Rn (R0 + Rm) sign extension Rn (R0 + Rm) Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 Privileged -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 6.0, 07/02, page 180 of 986 Table 7.3 Instruction MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT SWAP.B SWAP.W XTRCT Fixed-Point Transfer Instructions (cont) Operation R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 @(disp,PC),R0 Rn Rm,Rn Rm,Rn Rm,Rn R0 (disp + GBR) R0 (disp x 2 + GBR) R0 (disp x 4 + GBR) (disp + GBR) sign extension R0 (disp x 2 + GBR) sign extension R0 (disp x 4 + GBR) R0 disp x 4 + PC & H'FFFFFFFC + 4 R0 T Rn Rm swap lower 2 bytes Rn Rm swap upper/lower words Rn Rm:Rn middle 32 bits Rn Instruction Code 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101 Privileged -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- -- -- -- -- Rev. 6.0, 07/02, page 181 of 986 Table 7.4 Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS Arithmetic Operation Instructions Operation Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, carry T Rn + Rm Rn, overflow T When R0 = imm, 1 T Otherwise, 0 T When Rn = Rm, 1 T Otherwise, 0 T When Rn Rm (unsigned), 1T Otherwise, 0 T Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 Privileged -- -- -- -- -- -- -- T Bit -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 -- -- Comparison result -- CMP/GE CMP/HI Rm,Rn Rm,Rn When Rn Rm (signed), 1 T 0011nnnnmmmm0011 Otherwise, 0 T When Rn > Rm (unsigned), 1T Otherwise, 0 T 0011nnnnmmmm0110 -- -- CMP/GT CMP/PZ CMP/PL Rm,Rn Rn Rn When Rn > Rm (signed), 1 T 0011nnnnmmmm0111 Otherwise, 0 T When Rn 0, 1 T Otherwise, 0 T When Rn > 0, 1 T Otherwise, 0 T When any bytes are equal, 1T Otherwise, 0 T 1-step division (Rn / Rm) MSB of Rn Q, MSB of Rm M, M^Q T 0 M/Q/T Signed, Rn x Rm MAC, 32 x 32 64 bits Unsigned, Rn x Rm MAC, 32 x 32 64 bits Rn - 1 Rn; when Rn = 0, 1T When Rn 0, 0 T Rm sign-extended from byte Rn 0100nnnn00010001 0100nnnn00010101 0010nnnnmmmm1100 -- -- -- -- CMP/STR Rm,Rn DIV1 DIV0S DIV0U DMULS.L Rm,Rn Rm,Rn 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 0011nnnnmmmm0101 0100nnnn00010000 -- -- -- -- -- -- Rm,Rn DMULU.L Rm,Rn DT Rn EXTS.B Rm,Rn 0110nnnnmmmm1110 -- Rev. 6.0, 07/02, page 182 of 986 Table 7.4 Instruction EXTS.W EXTU.B EXTU.W MAC.L Arithmetic Operation Instructions (cont) Operation Rm,Rn Rm,Rn Rm,Rn Rm sign-extended from word Rn Rm zero-extended from byte Rn Rm zero-extended from word Rn Instruction Code 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 Privileged -- -- -- -- T Bit -- -- -- -- @Rm+,@Rn+ Signed, (Rn) x (Rm) + MAC MAC Rn + 4 Rn, Rm + 4 Rm 32 x 32 + 64 64 bits @Rm+,@Rn+ Signed, (Rn) x (Rm) + MAC MAC Rn + 2 Rn, Rm + 2 Rm 16 x 16 + 64 64 bits Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn x Rm MACL 32 x 32 32 bits Signed, Rn x Rm MACL 16 x 16 32 bits Unsigned, Rn x Rm MACL 16 x 16 32 bits 0 - Rm Rn 0 - Rm - T Rn, borrow T Rn - Rm Rn MAC.W 0100nnnnmmmm1111 -- -- MUL.L MULS.W MULU.W NEG NEGC SUB SUBC SUBV 0000nnnnmmmm0111 0010nnnnmmmm1111 0010nnnnmmmm1110 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 -- -- -- -- -- -- -- -- -- -- -- -- Borrow -- Borrow Underflow Rn - Rm - T Rn, borrow T 0011nnnnmmmm1010 Rn - Rm Rn, underflow T 0011nnnnmmmm1011 Rev. 6.0, 07/02, page 183 of 986 Table 7.5 Instruction AND AND Logic Operation Instructions Operation Rn & Rm Rn R0 & imm R0 Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii Privileged -- -- -- -- -- -- -- -- Test result T Bit -- -- -- -- -- -- Rm,Rn #imm,R0 AND.B #imm,@(R0,GBR) (R0 + GBR) & imm (R0 + GBR) NOT OR OR OR.B TAS.B Rm,Rn Rm,Rn #imm,R0 ~Rm Rn Rn | Rm Rn R0 | imm R0 #imm,@(R0,GBR) (R0 + GBR) | imm (R0 + GBR) @Rn 0100nnnn00011011 When (Rn) = 0, 1 T Otherwise, 0 T In both cases, 1 MSB of (Rn) Rn & Rm; when result = 0, 1T Otherwise, 0 T R0 & imm; when result = 0, 1T Otherwise, 0 T 0010nnnnmmmm1000 TST Rm,Rn -- Test result TST #imm,R0 11001000iiiiiiii -- Test result TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; when result 11001100iiiiiiii = 0, 1 T Otherwise, 0 T Rm,Rn #imm,R0 Rn Rm Rn R0 imm R0 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii -- Test result XOR XOR -- -- -- -- -- -- XOR.B #imm,@(R0,GBR) (R0 + GBR) imm (R0 + GBR) Rev. 6.0, 07/02, page 184 of 986 Table 7.6 Instruction ROTL ROTR ROTCL ROTCR SHAD Shift Instructions Operation Rn Rn Rn Rn Rm,Rn T Rn MSB LSB Rn T T Rn T T Rn T Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 Privileged -- -- -- -- -- T Bit MSB LSB MSB LSB -- When Rn 0, Rn << Rm Rn 0100nnnnmmmm1100 When Rn < 0, Rn >> Rm [MSB Rn] T Rn 0 MSB Rn T 0100nnnn00100000 0100nnnn00100001 SHAL SHAR SHLD Rn Rn Rm,Rn -- -- -- MSB LSB -- When Rn 0, Rn << Rm Rn 0100nnnnmmmm1101 When Rn < 0, Rn >> Rm [0 Rn] T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn -- -- -- -- -- -- -- -- MSB LSB -- -- -- -- -- -- Rev. 6.0, 07/02, page 185 of 986 Table 7.7 Instruction BF Branch Instructions Operation label When T = 0, disp x 2 + PC + 4 PC When T = 1, nop Delayed branch; when T = 0, disp x 2 + PC + 4 PC When T = 1, nop When T = 1, disp x 2 + PC + 4 PC When T = 0, nop Delayed branch; when T = 1, disp x 2 + PC + 4 PC When T = 0, nop Delayed branch, disp x 2 + PC + 4 PC Delayed branch, Rn + PC + 4 PC Instruction Code 10001011dddddddd Privileged -- T Bit -- BF/S label 10001111dddddddd -- -- BT label 10001001dddddddd -- -- BT/S label 10001101dddddddd -- -- BRA BRAF BSR BSRF JMP JSR RTS label Rn label Rn @Rn @Rn 1010dddddddddddd 0000nnnn00100011 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Delayed branch, PC + 4 PR, 1011dddddddddddd disp x 2 + PC + 4 PC Delayed branch, PC + 4 PR, 0000nnnn00000011 Rn + PC + 4 PC Delayed branch, Rn PC 0100nnnn00101011 Delayed branch, PC + 4 PR, 0100nnnn00001011 Rn PC Delayed branch, PR PC 0000000000001011 Rev. 6.0, 07/02, page 186 of 986 Table 7.8 Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L LDTLB System Control Instructions Operation 0 MACH, MACL 0S 0T Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,DBR Rm,Rn_BANK @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,SSR @Rm+,SPC @Rm+,DBR @Rm+,Rn_BANK Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Rm SR Rm GBR Rm VBR Rm SSR Rm SPC Rm DBR Rm Rn_BANK (n = 0 to 7) (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) DBR, Rm + 4 Rm (Rm) Rn_BANK, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACH, Rm + 4 Rm (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm PTEH/PTEL TLB R0 (Rn) (without fetching cache block) No operation @Rn @Rn @Rn @Rn Instruction Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 Privileged -- -- -- Privileged T Bit -- -- 0 LSB -- -- -- -- -- -- LSB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0100mmmm00011110 -- 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm11111010 0100mmmm1nnn1110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm11110110 0100mmmm1nnn0111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000nnnn11000011 0000000000001001 Privileged Privileged Privileged Privileged Privileged Privileged -- Privileged Privileged Privileged Privileged Privileged -- -- -- -- -- -- Privileged -- -- -- -- -- -- Privileged MOVCA.L R0,@Rn NOP OCBI OCBP OCBWB PREF RTE Invalidates operand cache block 0000nnnn10010011 Writes back and invalidates operand cache block Writes back operand cache block (Rn) operand cache Delayed branch, SSR/SPC SR/PC 0000nnnn10100011 0000nnnn10110011 0000nnnn10000011 0000000000101011 Rev. 6.0, 07/02, page 187 of 986 Table 7.8 Instruction SETS SETT SLEEP STC STC STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L TRAPA System Control Instructions (cont) Operation 1S 1T Sleep or standby SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn SGR,Rn DBR,Rn Rm_BANK,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn SSR,@-Rn SPC,@-Rn SGR,@-Rn DBR,@-Rn Rm_BANK,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm SR Rn GBR Rn VBR Rn SSR Rn SPC Rn SGR Rn DBR Rn Rm_BANK Rn (m = 0 to 7) Rn - 4 Rn, SR (Rn) Rn - 4 Rn, GBR (Rn) Rn - 4 Rn, VBR (Rn) Rn - 4 Rn, SSR (Rn) Rn - 4 Rn, SPC (Rn) Rn - 4 Rn, SGR (Rn) Rn - 4 Rn, DBR (Rn) Instruction Code 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn00111010 0000nnnn11111010 0000nnnn1mmm0010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn00110010 0100nnnn11110010 Privileged -- -- Privileged Privileged -- Privileged Privileged Privileged Privileged Privileged Privileged Privileged -- Privileged Privileged Privileged Privileged Privileged Privileged -- -- -- -- -- -- -- T Bit -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0100nnnn1mmm0011 Rn - 4 Rn, Rm_BANK (Rn) (m = 0 to 7) MACH Rn MACL Rn PR Rn Rn - 4 Rn, MACH (Rn) Rn - 4 Rn, MACL (Rn) Rn - 4 Rn, PR (Rn) PC + 2 SPC, SR SSR, #imm << 2 TRA, H'160 EXPEVT, VBR + H'0100 PC 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Rev. 6.0, 07/02, page 188 of 986 Table 7.9 Instruction FLDI0 FLDI1 FMOV FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV FMOV FMOV FMOV FMOV FMOV FMOV FLDS FSTS FABS FADD FCMP/EQ FCMP/GT FDIV FLOAT FMAC FMUL FNEG FSQRT FSUB FTRC Floating-Point Single-Precision Instructions Operation FRn FRn FRm,FRn @Rm,FRn @(R0,Rm),FRn @Rm+,FRn FRm,@Rn FRm,@-Rn FRm,@(R0,Rn) DRm,DRn @Rm,DRn @(R0,Rm),DRn @Rm+,DRn DRm,@Rn DRm,@-Rn DRm,@(R0,Rn) FRm,FPUL FPUL,FRn FRn FRm,FRn FRm,FRn FRm,FRn FRm,FRn FPUL,FRn FR0,FRm,FRn FRm,FRn FRn FRn FRm,FRn FRm,FPUL H'00000000 FRn H'3F800000 FRn FRm FRn (Rm) FRn (R0 + Rm) FRn FRm (Rn) Rn-4 Rn, FRm (Rn) FRm (R0 + Rn) DRm DRn (Rm) DRn (R0 + Rm) DRn DRm (Rn) Rn-8 Rn, DRm (Rn) DRm (R0 + Rn) FRm FPUL FPUL FRn FRn + FRm FRn When FRn = FRm, 1 T Otherwise, 0 T When FRn > FRm, 1 T Otherwise, 0 T FRn/FRm FRn (float) FPUL FRn FR0 * FRm + FRn FRn FRn * FRm FRn FRn H'80000000 FRn FRn FRn Instruction Code 1111nnnn10001101 1111nnnn10011101 1111nnnnmmmm1100 1111nnnnmmmm1000 1111nnnnmmmm0110 Privileged -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Comparison result Comparison result -- -- -- -- -- -- -- -- (Rm) FRn, Rm + 4 Rm 1111nnnnmmmm1001 1111nnnnmmmm1010 1111nnnnmmmm1011 1111nnnnmmmm0111 1111nnn0mmm01100 1111nnn0mmmm1000 1111nnn0mmmm0110 (Rm) DRn, Rm + 8 Rm 1111nnn0mmmm1001 1111nnnnmmm01010 1111nnnnmmm01011 1111nnnnmmm00111 1111mmmm00011101 1111nnnn00001101 FRn & H'7FFF FFFF FRn 1111nnnn01011101 1111nnnnmmmm0000 1111nnnnmmmm0100 1111nnnnmmmm0101 1111nnnnmmmm0011 1111nnnn00101101 1111nnnnmmmm1110 1111nnnnmmmm0010 1111nnnn01001101 1111nnnn01101101 1111nnnnmmmm0001 1111mmmm00111101 FRn - FRm FRn (long) FRm FPUL Rev. 6.0, 07/02, page 189 of 986 Table 7.10 Floating-Point Double-Precision Instructions Instruction FABS FADD FCMP/EQ FCMP/GT FDIV FCNVDS FCNVSD FLOAT FMUL FNEG FSQRT FSUB FTRC DRn DRm,DRn DRm,DRn DRm,DRn DRm,DRn DRm,FPUL FPUL,DRn FPUL,DRn DRm,DRn DRn DRn DRm,DRn DRm,FPUL Operation DRn & H'7FFF FFFF FFFF FFFF DRn DRn + DRm DRn When DRn = DRm, 1 T Otherwise, 0 T When DRn > DRm, 1 T Otherwise, 0 T DRn /DRm DRn Instruction Code 1111nnn001011101 1111nnn0mmm00000 1111nnn0mmm00100 1111nnn0mmm00101 1111nnn0mmm00011 Privileged -- -- -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- Comparison result Comparison result -- -- -- -- -- -- -- -- -- double_to_ float[DRm] FPUL 1111mmm010111101 float_to_ double [FPUL] DRn 1111nnn010101101 (float)FPUL DRn DRn * DRm DRn DRn ^ H'8000 0000 0000 0000 DRn DRn DRn 1111nnn000101101 1111nnn0mmm00010 1111nnn001001101 1111nnn001101101 1111nnn0mmm00001 1111mmm000111101 DRn - DRm DRn (long) DRm FPUL Table 7.11 Floating-Point Control Instructions Instruction LDS LDS LDS.L LDS.L STS STS STS.L STS.L Rm,FPSCR Rm,FPUL @Rm+,FPSCR @Rm+,FPUL FPSCR,Rn FPUL,Rn FPSCR,@-Rn FPUL,@-Rn Operation Rm FPSCR Rm FPUL (Rm) FPSCR, Rm+4 Rm (Rm) FPUL, Rm+4 Rm FPSCR Rn FPUL Rn Rn - 4 Rn, FPSCR (Rn) Rn - 4 Rn, FPUL (Rn) Instruction Code 0100mmmm01101010 0100mmmm01011010 0100mmmm01100110 0100mmmm01010110 0000nnnn01101010 0000nnnn01011010 0100nnnn01100010 0100nnnn01010010 Privileged -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- -- Rev. 6.0, 07/02, page 190 of 986 Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FIPR FTRV FRCHG FSCHG DRm,XDn XDm,DRn XDm,XDn @Rm,XDn @Rm+,XDn @(R0,Rm),XDn XDm,@Rn XDm,@-Rn XDm,@(R0,Rn) FVm,FVn XMTRX,FVn Operation DRm XDn XDm DRn XDm XDn (Rm) XDn (Rm) XDn, Rm + 8 Rm (R0 + Rm) XDn XDm (Rn) Rn - 8 Rn, XDm (Rn) XDm (R0+Rn) inner_product [FVm, FVn] FR[n+3] Instruction Code 1111nnn1mmm01100 1111nnn0mmm11100 1111nnn1mmm11100 1111nnn1mmmm1000 1111nnn1mmmm1001 1111nnn1mmmm0110 1111nnnnmmm11010 1111nnnnmmm11011 1111nnnnmmm10111 1111nnmm11101101 Privileged -- -- -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- transform_vector [XMTRX, FVn] 1111nn0111111101 FVn ~FPSCR.FR SPFCR.FR ~FPSCR.SZ SPFCR.SZ 1111101111111101 1111001111111101 Rev. 6.0, 07/02, page 191 of 986 Rev. 6.0, 07/02, page 192 of 986 Section 8 Pipelining The SH7750 Series is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7750 Series. 8.1 Pipelines Figure 8.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA), and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 8.2 shows the instruction execution patterns. Rev. 6.0, 07/02, page 193 of 986 1. General Pipeline I D EX NA * Non-memory data access S * Write-back * Instruction fetch * Instruction * Operation decode * Issue * Register read * Destination address calculation for PC-relative branch 2. General Load/Store Pipeline I D EX * Address calculation MA * Memory data access S * Write-back * Instruction fetch * Instruction decode * Issue * Register read 3. Special Pipeline I D SX * Operation NA * Non-memory data access S * Write-back * Instruction fetch * Instruction decode * Issue * Register read 4. Special Load/Store Pipeline I D SX * Address calculation MA * Memory data access S * Write-back * Instruction fetch * Instruction decode * Issue * Register read 5. Floating-Point Pipeline I D F1 * Computation 1 F2 * Computation 2 FS * Computation 3 * Write-back * Instruction fetch * Instruction decode * Issue * Register read 6. Floating-Point Extended Pipeline I D F0 * Computation 0 F1 * Computation 1 F2 * Computation 2 FS * Computation 3 * Write-back * Instruction fetch * Instruction decode * Issue * Register read 7. FDIV/FSQRT Pipeline F3 Computation: Takes several cycles Figure 8.1 Basic Pipelines Rev. 6.0, 07/02, page 194 of 986 1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG I D EX NA S 2. Load/store: 1 issue cycle MOV.[BWL]. FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR I D EX MA S 3. GBR-based load/store: 1 issue cycle MOV.[BWL]@(d,GBR) I D SX MA S 4. JMP, RTS, BRAF: 2 issue cycles I D EX D NA EX S NA S 5. TST.B: 3 issue cycles I D SX D MA SX D S NA SX S NA S 6. AND.B, OR.B, XOR.B: 4 issue cycles I D SX D MA SX D S NA SX D S NA SX S MA S 7. TAS.B: 5 issue cycles I D EX D MA EX D S MA EX D S NA EX D S NA EX S MA S 8. RTE: 5 issue cycles I D EX D NA EX D S NA EX D S NA EX D S NA EX S NA S 9. SLEEP: 4 issue cycles I D EX D NA EX D S NA EX D S NA EX S NA S Figure 8.2 Instruction Execution Patterns Rev. 6.0, 07/02, page 195 of 986 10. OCBI: 1 issue cycle I D EX MA S MA 11. OCBP, OCBWB: 1 issue cycle I D EX MA S MA MA MA MA 12. MOVCA.L: 1 issue cycle I D EX MA S MA MA MA MA MA MA 13. TRAPA: 7 issue cycles I D EX D NA EX D S NA EX D S NA EX D S NA EX D S NA EX D S NA EX S NA S 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle I D EX NA SX S SX 15. LDC to GBR: 3 issue cycles I D EX D NA SX D S SX 16. LDC to SR: 4 issue cycles I D EX D NA SX D S SX D SX 17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle I D EX MA SX S SX 18. LDC.L to GBR: 3 issue cycles I D EX D MA SX D S SX Figure 8.2 Instruction Execution Patterns (cont) Rev. 6.0, 07/02, page 196 of 986 19. LDC.L to SR: 4 issue cycles I D EX D MA SX D S SX D SX 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles I D SX D NA SX S NA S 21. STC.L from SGR: 3 issue cycles I D SX D NA SX D S NA SX S NA S 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles I D SX D NA SX S MA S 23. STC.L from SGR: 3 issue cycles I D SX D NA SX D S NA SX S MA S 24. LDS to PR, JSR, BSRF: 2 issue cycles I D EX D NA SX S SX 25. LDS.L to PR: 2 issue cycles I D EX D MA SX S SX 26. STS from PR: 2 issue cycles I D SX D NA SX S NA S 27. STS.L from PR: 2 issue cycles I D SX D NA SX S MA S 28. CLRMAC, LDS to MACH/L: 1 issue cycle I D EX NA F1 S F1 F2 FS 29. LDS.L to MACH/L: 1 issue cycle I D EX MA F1 S F1 F2 FS 30. STS from MACH/L: 1 issue cycle I D EX NA S Figure 8.2 Instruction Execution Patterns (cont) Rev. 6.0, 07/02, page 197 of 986 31. STS.L from MACH/L: 1 issue cycle I D EX MA S 32. LDS to FPSCR: 1 issue cycle I D EX NA F1 S F1 F1 33. LDS.L to FPSCR: 1 issue cycle I D EX MA F1 S F1 F1 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W I D EX D f1 f1 f1 f1 F2 FS NA EX S NA (CPU) S (FPU) 35. MAC.W, MAC.L: 2 issue cycles I D EX D f1 f1 f1 f1 F2 FS MA EX S MA (CPU) S (FPU) 36. Single-precision floating-point computation: 1 issue cycle FCMP/EQ,FCMP/GT, FADD,FLOAT,FMAC,FMUL,FSUB,FTRC,FRCHG,FSCHG I D F1 F2 FS 37. Single-precision FDIV/SQRT: 1 issue cycle I D F1 F2 FS F3 F1 F2 FS 38. Double-precision floating-point computation 1: 1 issue cycle FCNVDS, FCNVSD, FLOAT, FTRC I D F1 d F2 F1 FS F2 FS 39. Double-precision floating-point computation 2: 1 issue cycle FADD, FMUL, FSUB I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 FS F2 FS Figure 8.2 Instruction Execution Patterns (cont) Rev. 6.0, 07/02, page 198 of 986 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT I D F1 D F2 F1 FS F2 FS 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT I D F1 d F2 F1 FS F2 F3 F1 F2 F1 FS F2 F1 FS F2 42. FIPR: 1 issue cycle I D F0 F1 F2 FS FS 43. FTRV: 1 issue cycle I D F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0 FS F2 F1 FS F2 FS Notes: ?? : Cannot overlap a stage of the same kind, except when two instructions are executed in parallel. : Locks D-stage : Register read only : Locks, but no operation is executed. : Can overlap another f1, but not another F1. D d ?? f1 Figure 8.2 Instruction Execution Patterns (cont) Rev. 6.0, 07/02, page 199 of 986 8.2 Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1. MT Group CLRT CMP/EQ CMP/EQ CMP/GE CMP/GT 2. EX Group ADD ADD ADDC ADDV AND AND DIV0S DIV0U DIV1 DT EXTS.B EXTS.W EXTU.B EXTU.W MOV MOVA 3. BR Group BF BF/S disp disp BRA BSR disp disp BT BT/S disp disp Rm,Rn Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn #imm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn MOVT NEG NEGC NOT OR OR ROTCL ROTCR ROTL ROTR SHAD SHAL SHAR SHLD SHLL Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rn Rn Rn Rn Rm,Rn Rn Rn Rm,Rn Rn Rn SHLL2 SHLL8 SHLR SHLR16 SHLR2 SHLR8 SUB SUBC SUBV SWAP.B SWAP.W XOR XOR XTRCT Rn Rn Rn Rn Rn Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn CMP/HI CMP/HS CMP/PL CMP/PZ CMP/STR Rm,Rn Rm,Rn Rn Rn Rm,Rn MOV NOP SETT TST TST #imm,R0 Rm,Rn Rm,Rn @(disp,PC),R0 SHLL16 Rev. 6.0, 07/02, page 200 of 986 Table 8.1 Instruction Groups (cont) 4. LS Group FABS FABS FLDI0 FLDI1 FLDS FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV.S FMOV.S DRn FRn FRn FRn FRm,FPUL @(R0,Rm),DRn @(R0,Rm),XDn @Rm,DRn @Rm,XDn @Rm+,DRn @Rm+,XDn DRm,@(R0,Rn) DRm,@-Rn DRm,@Rn DRm,DRn DRm,XDn FRm,FRn XDm,@(R0,Rn) XDm,@-Rn XDm,@Rn XDm,DRn XDm,XDn @(R0,Rm),FRn @Rm,FRn FMOV.S FMOV.S FMOV.S FMOV.S FNEG FNEG FSTS LDS MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.L MOV.L MOV.L MOV.L MOV.L MOV.L @Rm+,FRn FRm,@(R0,Rn) FRm,@-Rn FRm,@Rn DRn FRn FPUL,FRn Rm,FPUL MOV.L MOV.L MOV.L MOV.L MOV.L MOV.W MOV.W MOV.W R0,@(disp,GBR) Rm,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn @(disp,GBR),R0 @(disp,PC),Rn @(disp,Rm),R0 @(R0,Rm),Rn @Rm,Rn @Rm+,Rn R0,@(disp,GBR) R0,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn R0,@Rn @Rn @Rn @Rn @Rn FPUL,Rn @(disp,GBR),R0 MOV.W @(disp,Rm),R0 @(R0,Rm),Rn @Rm,Rn @Rm+,Rn MOV.W MOV.W MOV.W MOV.W R0,@(disp,GBR) MOV.W R0,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn MOV.W MOV.W MOVCA.L OCBI @(disp,GBR),R0 OCBP @(disp,PC),Rn @(disp,Rm),Rn @(R0,Rm),Rn @Rm,Rn @Rm+,Rn OCBWB PREF STS Rev. 6.0, 07/02, page 201 of 986 Table 8.1 Instruction Groups (cont) 5. FE Group FADD FADD FCMP/EQ FCMP/GT FCNVDS FCNVSD FDIV FDIV DRm,DRn FRm,FRn FRm,FRn FRm,FRn DRm,FPUL FPUL,DRn DRm,DRn FRm,FRn FIPR FLOAT FLOAT FMAC FMUL FMUL FRCHG FSCHG FVm,FVn FPUL,DRn FPUL,FRn FSQRT FSQRT FSUB DRn FRn DRm,DRn FRm,FRn DRm,FPUL FRm,FPUL XMTRX,FVn FR0,FRm,FRn FSUB DRm,DRn FRm,FRn FTRC FTRC FTRV Rev. 6.0, 07/02, page 202 of 986 Table 8.1 Instruction Groups (cont) 6. CO Group AND.B BRAF BSRF CLRMAC CLRS DMULS.L DMULU.L FCMP/EQ FCMP/GT JMP JSR LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L Rm,Rn Rm,Rn DRm,DRn DRm,DRn @Rn @Rn Rm,DBR Rm,GBR Rm,Rp_BANK Rm,SPC Rm,SR Rm,SSR Rm,VBR @Rm+,DBR @Rm+,GBR #imm,@(R0,GBR) LDS Rm Rm LDS LDS LDS LDS.L LDS.L LDS.L LDS.L LDS.L LDTLB MAC.L MAC.W MUL.L MULS.W MULU.W OR.B RTE RTS SETS SLEEP DBR,Rn GBR,Rn Rp_BANK,Rn SGR,Rn SPC,Rn @Rm+,@Rn+ @Rm+,@Rn+ Rm,Rn Rm,Rn Rm,Rn Rm,FPSCR Rm,MACH Rm,MACL Rm,PR @Rm+,FPSCR @Rm+,FPUL @Rm+,MACH @Rm+,MACL @Rm+,PR STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS SR,Rn SSR,Rn VBR,Rn DBR,@-Rn GBR,@-Rn Rp_BANK,@-Rn SGR,@-Rn SPC,@-Rn SR,@-Rn SSR,@-Rn VBR,@-Rn FPSCR,Rn MACH,Rn MACL,Rn PR,Rn FPSCR,@-Rn FPUL,@-Rn MACH,@-Rn MACL,@-Rn PR,@-Rn @Rn #imm #imm,@(R0,GBR) #imm,@(R0,GBR) #imm,@(R0,GBR) STS.L STS.L STS.L STS.L STS.L TAS.B TRAPA TST.B XOR.B @Rm+,Rp_BANK STC @Rm+,SPC @Rm+,SR @Rm+,SSR @Rm+,VBR STC STC STC STC Rev. 6.0, 07/02, page 203 of 986 Table 8.2 Parallel-Executability 2nd Instruction MT EX O X O O O X BR O O X O O X LS O O O X O X FE O O O O X X CO X X X X X X 1st Instruction MT EX BR LS FE CO O O O O O X O: Can be executed in parallel X: Cannot be executed in parallel 8.3 Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: * I-clock: CPU, FPU, MMU, caches * B-clock: External bus controller * P-clock: Peripheral units The frequency ratios of the three clocks are determined with the frequency control register (FRQCR). In this section, machine cycles are based on the I-clock unless otherwise specified. For details of FRQCR, see section 10, Clock Oscillation Circuits. Instruction execution cycles are summarized in table 8.3. Penalty cycles due to a pipeline stall or freeze are not considered in this table. * Issue rate: Interval between the issue of an instruction and that of the next instruction * Latency: Interval between the issue of an instruction and the generation of its result (completion) * Instruction execution pattern (see figure 8.2) * Locked pipeline stages (see table 8.3) * Interval between the issue of an instruction and the start of locking (see table 8.3) * Lock time: Period of locking in machine cycle units (see table 8.3) Rev. 6.0, 07/02, page 204 of 986 The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction; the only exception is when two instructions are executed in parallel under parallel-executability conditions. Refer to (a) through (d) in figure 8.3 for some simple examples. Latency is the interval between issue and completion of an instruction, and is also the interval between the execution of two instructions with an interdependent relationship. When there is interdependency between two instructions fetched simultaneously, the latter of the two is stalled for the following number of cycles: * (Latency) cycles when there is flow dependency (read-after-write) * (Latency - 1) or (latency - 2) cycles when there is output dependency (write-after-write) Single/double-precision FDN, FSQRT is the preceding instruction (latency - 1) cycles The other FE group is the preceding instruction (latency - 2) cycles * 5 or 2 cycles when there is anti-flow dependency (write-after-read), as in the following cases: FTRV is the preceding instruction (5 cycle) A double-precision FADD, FSUB, or FMUL is the preceding instruction (2 cycles) In the case of flow dependency, latency may be exceptionally increased or decreased, depending on the combination of sequential instructions (figure 8.3 (e)). * When a floating-point (FP) computation is followed by an FP register store, the latency of the FP computation may be decreased by 1 cycle. * If there is a load of the shift amount immediately before an SHAD/SHLD instruction, the latency of the load is increased by 1 cycle. * If an instruction with a latency of less than 2 cycles, including write-back to an FP register, is followed by a double-precision FP instruction, FIPR, or FTRV, the latency of the first instruction is increased to 2 cycles. The number of cycles in a pipeline stall due to flow dependency will vary depending on the combination of interdependent instructions or the fetch timing (see figure 8.3. (e)). Output dependency occurs when the destination operands are the same in a preceding FE group instruction and a following LS group instruction. For the stall cycles of an instruction with output dependency, the longest latency to the last writeback among all the destination operands must be applied instead of "latency" (see figure 8.3 (f)). A stall due to output dependency with respect to FPSCR, which reflects the result of an FP operation, never occurs. For example, when FADD follows FDIV with no dependency between FP registers, FADD is not stalled even if both instructions update the cause field of FPSCR. Rev. 6.0, 07/02, page 205 of 986 Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource--i.e. a function block that performs a basic operation--a following instruction that happens to attempt to use the locked resource must be stalled (figure 8.3 (h)). This kind of stall can be compensated by inserting one or more instructions independent of the locked resource to separate the interfering instructions. For example, when a load instruction and an ADD instruction that references the loaded value are consecutive, the 2cycle stall of the ADD is eliminated by inserting three instructions without dependency. Software performance can be improved by such instruction scheduling. Other penalties arise in the event of exceptions or external data accesses, as follows. * Instruction TLB miss * Instruction access to external memory (instruction cache miss, etc.) * Data access to external memory (operand cache miss, etc.) * Data access to a memory-mapped control register. During the penalty cycles of an instruction TLB miss or external instruction access, no instruction is issued, but execution of instructions that have already been issued continues. The penalty for a data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted until the arrival of the requested data. The number of penalty cycles for instruction and data accesses is largely dependent on the user's memory subsystems. Rev. 6.0, 07/02, page 206 of 986 (a) Serial execution: non-parallel-executable instructions SHAD R0,R1 ADD R2,R3 next I I D 1 issue cycle EX NA EX D 1 stall cycle D ... S NA EX-group SHAD and EX-group ADD cannot be executed in parallel. Therefore, SHAD is issued first, and the following ADD is recombined with the next instruction. S I (b) Parallel execution: parallel-executable and no dependency ADD R2,R1 MOV.L @R4,R5 I I D D 1 issue cycle EX NA EX MA S S EX-group ADD and LS-group MOV.L can be executed in parallel. Overlapping of stages in the 2nd instruction is possible. (c) Issue rate: multi-step instruction 4 issue cycles AND.B#1,@(R0,GBR) I D SX D MA SX D S NA SX D i I S NA SX D ... AND.B and MOV are fetched simultaneously, but MOV is stalled due to resource locking. After the lock is released, MOV is refetched together with the next instruction. S MOV next R1,R2 I 4 stall cycles S MA E S A (d) Branch BT/S L_far ADD R0,R1 SUB R2,R3 I I D D I EX EX D NA NA EX S S NA No stall occurs if the branch is not taken. S BT/S L_far ADD R0,R1 L_far BT L_skip ADD #1,R0 L_skip: I I D D 2-cycle latency for I-stage of branch destination If the branch is taken, the I-stage of the EX NA S branch destination is stalled for the period EX NA S of latency. This stall can be covered with a 1 stall cycle delay slot instruction which is not parallelI D ... executable with the branch instruction. EX -- D NA -- ... S -- Even if the BT/BF branch is taken, the Istage of the branch destination is not stalled if the displacement is zero. I I D D I No stall Figure 8.3 Examples of Pipelined Execution Rev. 6.0, 07/02, page 207 of 986 (e) Flow dependency MOV ADD R0,R1 R2,R1 I I D D Zero-cycle latency EX NA S EX NA S 1-cycle latency EX NA S EX MA D ... The following instruction, ADD, is not stalled when executed after an instruction with zero-cycle latency, even if there is dependency. ADD and MOV.L are not executed in parallel, since MOV.L references the result of ADD as its destination address. ADD R2,R1 MOV.L @R1,R1 next D i I 1 stall cycle I I S MOV.L @R1,R1 ADD R0,R1 next I D I I EX D ... 2-cycle latency S EX NA 1 stall cycle MA S Because MOV.L and ADD are not fetched simultaneously in this example, ADD is stalled for only 1 cycle even though the latency of MOV.L is 2 cycles. 2-cycle latency 1-cycle increase MOV.L @R1,R1 SHAD R1,R2 next I D I I EX D ... MA S d EX NA S Due to the flow dependency between the load and the SHAD/SHLD shift amount, the latency of the load is increased to 3 cycles. 2 stall cycles 4-cycle latency for FPSCR FADD STS STS FR1,FR2 FPUL,R1 FPSCR,R2 I D I F1 D I F2 EX FS NA S D EX NA S 2 stall cycles 7-cycle latency for lower FR 8-cycle latency for upper FR FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 FMOV FMOV FR3,FR5 FR2,FR4 I I FS F2 D FR3 write FS FR2 write EX NA S EX D NA S 3-cycle latency for upper/lower FR FLOAT FPUL,DR0 FMOV.S FR0,@-R15 I I D D Zero-cycle latency 3-cycle increase FLDI1 FIPR FR3 FV0,FV4 I I D D EX NA S d F0 F1 3 stall cycles F2 FS F1 d F2 F1 FS F2 FR1 write FS FR0 write EX MA S 2-cycle latency 1-cycle increase FMOV FTRV @R1,XD14 XMTRX,FV0 I I D D EX MA S d F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0 3 stall cycles FS F2 F1 FS F2 FS Figure 8.3 Examples of Pipelined Execution (cont) Rev. 6.0, 07/02, page 208 of 986 (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions LDS FLOAT LDS FLOAT R0,FPUL FPUL,FR0 R1,FPUL FPUL,R1 I D I I EX D D I NA F1 EX D S F2 NA F1 FS S F2 FS FTRC STS FTRC STS FR0,FPUL FPUL,R0 FR1,FPUL FPUL,R1 I D I I F1 D D I F2 EX F1 D FS NA F2 EX S FS NA Effectively 1-cycle latency for consecutive FTRC/STS instructions S (f) Output dependency 11-cycle latency FSQRT FR4 I D F1 F2 FS F3 F1 F2 FS F1 FS F2 The registers are written-back in program order. 7-cycle latency for lower FR 8-cycle latency for upper FR FMOV FR0,FR4 I D 10 stall cycles = latency (11) - 1 FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 FS F2 EX FR3 write FS FR2 write NA S FMOV FR0,FR3 I D 6 stall cycles = longest latency (8) - 2 (g) Anti-flow dependency FTRV XMTRX,FV0 I D F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0 FS F2 F1 FMOV @R1,XD0 I D 5 stall cycles FS F2 EX FS MA S FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d NA FS F2 F1 S FS F2 F1 FS F2 FS FMOV FR4,FR1 I D 2 stall cycles EX Figure 8.3 Examples of Pipelined Execution (cont) Rev. 6.0, 07/02, page 209 of 986 (h) Resource conflict #1 #2 F2 #3 FS F3 F1 F2 FS .................................................. #8 #9 #10 #11 #12 1 cycle/issue FDIV FR6,FR7 I D F1 Latency F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 ... I D I F1 D F2 F1 FS F2 FS I D F1 F2 FS : 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 I D I F0 D F1 1 stall cycle F2 F1 FS F2 FS LDS.L @R15+,PR I D EX D MA SX D FS SX STC GBR,R2 I 3 stall cycles FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d SX D NA SX S NA S FS F2 F1 d FS F2 F1 FS F2 F1 MAC.W @R1+,@R2+ I D 5 stall cycles FS F2 EX f1 D FS MA EX f1 S MA f1 S F2 f1 FS F2 FS MAC.W @R1+,@R2+ I D EX f1 D MA EX f1 S MA f1 S F2 f1 MA EX f1 FS F2 S MA f1 f1 stage can overlap preceding f1, but F1 cannot overlap f1. FS MAC.W @R1+,@R2+ I 1 stall cycle D EX f1 D S F2 f1 FS F2 F1 d FADD DR4,DR6 I 3 stall cycles D 2 stall cycles FS F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 FS ... Figure 8.3 Examples of Pipelined Execution (cont) Rev. 6.0, 07/02, page 210 of 986 Table 8.3 Execution Cycles InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn @(disp,PC),R0 @(disp,PC),Rn @(disp,PC),Rn @Rm,Rn @Rm,Rn @Rm,Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 Rm,@Rn Rm,@Rn Rm,@Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn R0,@(disp,Rn) EX EX EX EX MT EX EX LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 2 2 2 2 2 1/2 1/2 1/2 2 2 2 2 2 2 2 2 2 1 1 1 1/1 1/1 1/1 1 #1 #1 #1 #1 #1 #1 #1 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #3 #3 #3 #2 #2 #2 #2 #2 #2 #2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Functional Category No. Data transfer 1 instructions 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Instruction EXTS.B EXTS.W EXTU.B EXTU.W MOV MOV MOVA MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B Rev. 6.0, 07/02, page 211 of 986 Table 8.3 Execution Cycles (cont) InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles R0,@(disp,Rn) Rm,@(disp,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) LS LS LS LS LS LS LS LS LS EX LS LS LS LS EX EX EX EX EX EX EX MT MT MT MT MT MT MT MT MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3-7 1 1-2 1-5 1-5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 #2 #2 #2 #2 #2 #3 #3 #3 #12 #1 #10 #11 #11 #2 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 -- -- -- -- -- -- -- -- MA -- MA MA MA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 -- 4 4 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3-7 -- 1-2 1-5 1-5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Functional Category No. Data transfer 32 instructions 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Fixed-point 49 arithmetic 50 instructions 51 52 53 54 55 56 57 58 59 60 61 62 Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVCA.L R0,@Rn MOVT OCBI OCBP OCBWB PREF SWAP.B SWAP.W XTRCT ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/GE CMP/GT CMP/HI CMP/HS CMP/PL CMP/PZ Rn @Rn @Rn @Rn @Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn CMP/STR Rm,Rn DIV0S Rm,Rn Rev. 6.0, 07/02, page 212 of 986 Table 8.3 Execution Cycles (cont) InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles EX Rm,Rn Rm,Rn EX CO CO EX CO CO CO CO CO EX EX EX EX EX EX EX 1 1 2 2 1 2 2 2 2 2 1 1 1 1 1 1 1 4 1 1 1 4 5 1 1 3 1 1 4 1 1 4/4 4/4 1 2/2/4/4 2/2/4/4 4/4 4/4 4/4 1 1 1 1 1 1 1 4 1 1 1 4 5 1 1 3 1 1 4 #1 #1 #34 #34 #1 #35 #35 #34 #34 #34 #1 #1 #1 #1 #1 #1 #1 #6 #1 #1 #1 #6 #7 #1 #1 #5 #1 #1 #6 -- -- F1 F1 -- F1 F1 F1 F1 F1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 4 -- 4 4 4 4 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 2 -- 2 2 2 2 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Functional Category No. Fixed-point 63 arithmetic 64 instructions 65 66 67 68 69 70 71 72 73 74 75 76 77 Logical 78 instructions 79 80 81 82 83 84 85 86 87 88 89 90 91 Instruction DIV0U DIV1 DMULS.L DMULU.L Rm,Rn DT MAC.L MAC.W MUL.L MULS.W MULU.W NEG NEGC SUB SUBC SUBV AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Rn @Rm+,@Rn+ @Rm+,@Rn+ Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) CO Rm,Rn Rm,Rn #imm,R0 EX EX EX #imm,@(R0,GBR) CO @Rn Rm,Rn #imm,R0 CO MT MT #imm,@(R0,GBR) CO Rm,Rn #imm,R0 EX EX #imm,@(R0,GBR) CO Rev. 6.0, 07/02, page 213 of 986 Table 8.3 Execution Cycles (cont) InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Rn Rn Rn Rn Rm,Rn Rn Rn Rm,Rn Rn Rn Rn Rn Rn Rn Rn Rn disp disp disp disp disp Rn disp Rn @Rn @Rn EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX BR BR BR BR BR CO BR CO CO CO CO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 (or 1) 2 (or 1) 2 (or 1) 2 (or 1) 2 3 2 3 3 3 3 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #4 #14 #24 #4 #24 #4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SX SX -- SX -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3 3 -- 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 2 -- 2 -- Functional Category No. Shift 92 instructions 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Branch 108 instructions 109 110 111 112 113 114 115 116 117 118 Instruction ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLL2 SHLL8 SHLL16 SHLR SHLR2 SHLR8 SHLR16 BF BF/S BT BT/S BRA BRAF BSR BSRF JMP JSR RTS Rev. 6.0, 07/02, page 214 of 986 Table 8.3 Execution Cycles (cont) InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles MT CO CO MT CO MT #imm CO CO CO CO Rm,DBR Rm,GBR Rm,Rp_BANK Rm,SR Rm,SSR Rm,SPC Rm,VBR @Rm+,DBR @Rm+,GBR CO CO CO CO CO CO CO CO CO 1 1 1 1 1 1 7 5 4 1 1 3 1 4 1 1 1 1 3 1 4 1 1 1 1 1 2 1 1 2 2 3 0 3 1 1 1 1 7 5 4 1 3 3 3 4 3 3 3 1/3 3/3 1/3 4/4 1/3 1/3 1/3 3 3 3 1/3 1/3 2/3 2 3 #1 #28 #1 #1 #1 #1 #13 #8 #9 #2 #14 #15 #14 #16 #14 #14 #14 #17 #18 #17 #19 #17 #17 #17 #28 #28 #24 #29 #29 #25 #20 #21 -- F1 -- -- -- -- -- -- -- -- SX SX SX SX SX SX SX SX SX SX SX SX SX SX F1 F1 SX F1 F1 SX -- -- -- 3 -- -- -- -- -- -- -- -- 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -- -- -- 2 -- -- -- -- -- -- -- -- 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- -- Functional Category No. System 119 control 120 instructions 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Instruction NOP CLRMAC CLRS CLRT SETS SETT TRAPA RTE SLEEP LDTLB LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L STC STC @Rm+,Rp_BANK CO @Rm+,SR @Rm+,SSR @Rm+,SPC @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR DBR,Rn SGR,Rn CO CO CO CO CO CO CO CO CO CO CO CO Rev. 6.0, 07/02, page 215 of 986 Table 8.3 Execution Cycles (cont) InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles GBR,Rn Rp_BANK,Rn SR,Rn SSR,Rn SPC,Rn VBR,Rn DBR,@-Rn SGR,@-Rn GBR,@-Rn Rp_BANK,@-Rn SR,@-Rn SSR,@-Rn SPC,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn FRn FRn FRm,FRn @Rm,FRn @Rm+,FRn @(R0,Rm),FRn FRm,@Rn FRm,@-Rn FRm,@(R0,Rn) FRm,FPUL FPUL,FRn CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO LS LS LS LS LS LS LS LS LS LS LS 2 2 2 2 2 2 2 3 2 2 2 2 2 2 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2/2 3/3 2/2 2/2 2/2 2/2 2/2 2/2 3 3 2 1/1 1/1 2/2 0 0 0 2 1/2 2 1 1/1 1 0 0 #20 #20 #20 #20 #20 #20 #22 #23 #22 #22 #22 #22 #22 #22 #30 #30 #26 #31 #31 #27 #1 #1 #1 #2 #2 #2 #2 #2 #2 #1 #1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Functional Category No. System 151 control 152 instructions 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 Single171 precision 172 floating-point instructions 173 174 175 176 177 178 179 180 181 Instruction STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L FLDI0 FLDI1 FMOV FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FLDS FSTS Rev. 6.0, 07/02, page 216 of 986 Table 8.3 Execution Cycles (cont) InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles FRn FRm,FRn LS FE FE FE FE 1 1 1 1 1 0 3/4 2/4 2/4 12/13 #1 #36 #36 #36 #37 -- -- -- -- F3 F1 187 188 189 190 191 FLOAT FMAC FMUL FNEG FSQRT FPUL,FRn FR0,FRm,FRn FRm,FRn FRn FRn FE FE FE LS FE 1 1 1 1 1 3/4 3/4 3/4 0 11/12 #36 #36 #36 #1 #37 -- -- -- -- F3 F1 192 193 194 195 196 197 198 199 200 FSUB FTRC FMOV FMOV FMOV FMOV FMOV FMOV FMOV FABS FADD FRm,FRn FRm,FPUL DRm,DRn @Rm,DRn @Rm+,DRn @(R0,Rm),DRn DRm,@Rn DRm,@-Rn DRm,@(R0,Rn) DRn DRm,DRn FE FE LS LS LS LS LS LS LS LS FE CO CO FE FE FE 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 3/4 3/4 0 2 1/2 2 1 1/1 1 0 (7, 8)/9 3/5 3/5 4/5 (3, 4)/5 #36 #36 #1 #2 #2 #2 #2 #2 #2 #1 #39 #40 #40 #38 #38 -- -- -- -- -- -- -- -- -- -- F1 F1 F1 F1 F1 F3 F1 F1 208 209 FLOAT FMUL FPUL,DRn DRm,DRn FE FE 1 1 (3, 4)/5 (7, 8)/9 #38 #39 F1 F1 -- -- -- -- 2 11 -- -- -- -- 2 10 -- -- -- -- -- -- -- -- -- -- 2 2 2 2 2 2 22 2 2 2 -- -- -- -- 10 1 -- -- -- -- 9 1 -- -- -- -- -- -- -- -- -- -- 6 2 2 2 2 23 3 2 2 6 Functional Category No. Single182 precision 183 floating-point instructions 184 185 186 Instruction FABS FADD FCMP/EQ FRm,FRn FCMP/GT FRm,FRn FDIV FRm,FRn Double201 precision 202 floating-point instructions 203 204 205 206 207 FCMP/EQ DRm,DRn FCMP/GT DRm,DRn FCNVDS FCNVSD FDIV DRm,FPUL FPUL,DRn DRm,DRn (24, 25)/ #41 26 Rev. 6.0, 07/02, page 217 of 986 Table 8.3 Execution Cycles (cont) InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles DRn DRn LS FE 1 1 0 #1 -- F3 F1 F1 212 213 FSUB FTRC LDS LDS LDS.L LDS.L STS STS STS.L STS.L FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FIPR FRCHG FSCHG FTRV XMTRX,FVn DRm,DRn DRm,FPUL Rm,FPUL Rm,FPSCR @Rm+,FPUL @Rm+,FPSCR FPUL,Rn FPSCR,Rn FPUL,@-Rn FPSCR,@-Rn DRm,XDn XDm,DRn XDm,XDn @Rm,XDn @Rm+,XDn @(R0,Rm),XDn XDm,@Rn XDm,@-Rm XDm,@(R0,Rn) FVm,FVn FE FE LS CO CO CO LS CO CO CO LS LS LS LS LS LS LS LS LS FE FE FE FE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (7, 8)/9 4/5 1 4 1/2 1/4 3 3 1/1 1/1 0 0 0 2 1/2 2 1 1/1 1 4/5 1/4 1/4 (5, 5, 6, 7)/8 #39 #38 #1 #32 #2 #33 #1 #1 #2 #2 #1 #1 #1 #2 #2 #2 #2 #2 #2 #42 #36 #36 #43 F1 F1 -- F1 -- F1 -- -- -- -- -- -- -- -- -- -- -- -- -- F1 -- -- F0 F1 -- 2 21 2 2 2 -- 3 -- 3 -- -- -- -- -- -- -- -- -- -- -- -- -- 3 -- -- 2 3 -- 22 3 2 6 2 -- 3 -- 3 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- 4 4 Functional Category No. Double210 precision 211 floating-point instructions Instruction FNEG FSQRT (23, 24)/ #41 25 FPU system 214 control 215 instructions 216 217 218 219 220 221 Graphics 222 acceleration 223 instructions 224 225 226 227 228 229 230 231 232 233 234 Notes: 1. See table 8.1 for the instruction groups. 2. Latency "L1/L2...": Latency corresponding to a write to each register, including MACH/MACL/FPSCR. Example: MOV.B @Rm+, Rn "1/2": The latency for Rm is 1 cycle, and the latency for Rn is 2 cycles. 3. Branch latency: Interval until the branch destination instruction is fetched Rev. 6.0, 07/02, page 218 of 986 4. Conditional branch latency "2 (or 1)": The latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency "(L1, L2)/L3": L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6. FTRV latency "(L1, L2, L3, L4)/L5": L1 is the latency for FR [n], L2 that for FR [n+1], L3 that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR. 7. Latency "L1/L2/L3/L4" of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2 that for Rn, L3 that for MACH, and L4 that for MACL. 8. Latency "L1/L2" of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions: L1 is the latency for MACH, and L2 that for MACL. 9. Execution pattern: The instruction execution pattern number (see figure 8.2) 10. Lock/stage: Stage locked by the instruction 11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction. 12. Lock/cycles: Number of cycles locked Exceptions: 1. When a floating-point computation instruction is followed by an FMOV store, an STS FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, the latency of the floatingpoint computation is decreased by 1 cycle. 2. When the preceding instruction loads the shift amount of the following SHAD/SHLD, the latency of the load is increased by 1 cycle. 3. When an LS group instruction with a latency of less than 3 cycles is followed by a double-precision floating-point instruction, FIPR, or FTRV, the latency of the first instruction is increased to 3 cycles. Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2 cycles. 4. When MAC/MUL/DMUL is followed by an STS.L MAC, @-Rn instruction, the latency of MAC/MUL/DMUL is 5 cycles. 5. In the case of consecutive executions of MAC/MUL/DMUL, the latency is decreased to 2 cycles. 6. When an LDS to MAC is followed by an STS.L MAC, @-Rn instruction, the latency of the LDS to MAC is 4 cycles. 7. When an LDS to MAC is followed by MAC/MUL/DMUL, the latency of the LDS to MAC is 1 cycle. 8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that reads or writes to a floating-point register, the aforementioned LS group instruction[s] cannot be executed in parallel. 9. When a single-precision FTRC instruction is followed by an "STS FPUL, Rn" instruction, the latency of the single-precision FTRC instruction is 1 cycle. Rev. 6.0, 07/02, page 219 of 986 Rev. 6.0, 07/02, page 220 of 986 Section 9 Power-Down Modes 9.1 Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: * Sleep mode * Deep sleep mode * Standby mode * Hardware standby mode* * Module standby function (TMU, RTC, SCI/SCIF, DMAC, SQ*, and UBC* on-chip peripheral modules) Note: * SH7750S, SH7750R only Table 9.1 shows the conditions for entering these modes from the program execution state, the status of the CPU and peripheral modules in each mode, and the method of exiting each mode. Rev. 6.0, 07/02, page 221 of 986 Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status PowerDown Mode Sleep Entering Conditions SLEEP instruction executed while STBY bit is 0 in STBCR SLEEP instruction executed while STBY bit is 0 in STBCR, and DSLP bit is 1 in STBCR2 SLEEP instruction executed while STBY bit is 1 in STBCR CPG CPU On-Chip Memory Held On-chip Peripheral Modules Pins Operating Held External Memory Exiting Method Operating Halted (registers held) Refreshing * Interrupt * Reset Deep sleep Operating Halted (registers held) Held Operating (DMA halted) Held Selfrefreshing * Interrupt * Reset Standby Halted Halted (registers held) Held Halted* Held Selfrefreshing * Interrupt * Reset Hardware Setting CA standby pin low (SH7750S, SH7750R) Module standby Setting MSTP bit to 1 in STBCR/ STBCR2 Halted Halted Undefined Halted* High Undefined impedance * Power-on reset Operating Operating Held Specified modules halted* Held Refreshing * Clearing MSTP bit to 0 * Reset Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock (RTC)). Rev. 6.0, 07/02, page 222 of 986 9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Name Standby control register Standby control register 2 Clock stop register 00* Clock release register 00* Power-Down Mode Registers Abbreviation STBCR STBCR2 CLKSTP00 CLKSTPCLR00 R/W R/W R/W R/W W Initial Value H'00 H'00 H'00000000 H'00000000 P4 Address H'FFC00004 H'FFC00010 H'FE0A0000 H'FE0A0008 Area 7 Address H'1FC00004 H'1FC00010 H'1E0A0000 H'1E0A0008 Access Size 8 8 32 32 Note: * SH7750R only 9.1.3 Pin Configuration Table 9.3 shows the pins used for power-down mode control. Table 9.3 Pin Name Processor status 1 Processor status 0 Power-Down Mode Pins Abbreviation STATUS1 STATUS0 I/O Output Function Indicate the processor's operating status. (STATUS1, STATUS0) HH: Reset HL: Sleep mode LH: Standby mode LL: Normal operation Hardware standby request (SH7750S and SH7750R only) Notes: H: High level L: Low level CA Input Transits to hardware standby mode by a low-level input to the pin. Rev. 6.0, 07/02, page 223 of 986 9.2 9.2.1 Register Descriptions Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that specifies the power-down mode status. It is initialized to H'00 by a power-on reset via the 5(6(7 pin or due to watchdog timer overflow. Bit: 7 STBY Initial value: R/W: 0 R/W 6 PHZ 0 R/W 5 PPU 0 R/W 4 MSTP4 0 R/W 3 MSTP3 0 R/W 2 MSTP2 0 R/W 1 MSTP1 0 R/W 0 MSTP0 0 R/W Bit 7--Standby (STBY): Specifies a transition to standby mode. Bit 7: STBY 0 1 Description Transition to sleep mode on execution of SLEEP instruction Transition to standby mode on execution of SLEEP instruction (Initial value) Bit 6--Peripheral Module Pin High Impedance Control (PHZ): Controls the state of peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module related pins go to the high-impedance state in standby mode. For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control. Bit 6: PHZ 0 1 Description Peripheral module related pins are in normal state Peripheral module related pins go to high-impedance state (Initial value) Bit 5--Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral module related pins in the input or high-impedance state. For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control. Bit 5: PPU 0 1 Description Peripheral module related pin pull-up resistors are on Peripheral module related pin pull-up resistors are off (Initial value) Bit 4--Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set Rev. 6.0, 07/02, page 224 of 986 to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again. Bit 4: MSTP4 0 1 Description DMAC operates DMAC clock supply is stopped (Initial value) Bit 3--Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is stopped when the MSTP3 bit is set to 1. Bit 3: MSTP3 0 1 Description SCIF operates SCIF clock supply is stopped (Initial value) Bit 2--Module Stop 2 (MSTP2): Specifies stopping of the clock supply to the timer unit (TMU) among the on-chip peripheral modules. The clock supply to the TMU is stopped when the MSTP2 bit is set to 1. Bit 2: MSTP2 0 1 Description TMU operates TMU clock supply is stopped (Initial value) Bit 1--Module Stop 1 (MSTP1): Specifies stopping of the clock supply to the realtime clock (RTC) among the on-chip peripheral modules. The clock supply to the RTC is stopped when the MSTP1 bit is set to 1. When the clock supply is stopped, RTC registers cannot be accessed but the counters continue to operate. Bit 1: MSTP1 0 1 Description RTC operates RTC clock supply is stopped (Initial value) Bit 0--Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is stopped when the MSTP0 bit is set to 1. Bit 0: MSTP0 0 1 Description SCI operates SCI clock supply is stopped (Initial value) Rev. 6.0, 07/02, page 225 of 986 9.2.2 Peripheral Module Pin High Impedance Control When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go to the high-impedance state in standby mode. * Relevant Pins SCI related pins MD0/SCK MD7/TXD CTS2 DMA related pins DACK0 DACK1 DRAK0 DRAK1 MD1/TXD2 MD8/RTS2 * Other Information The setting in this register is invalid when the above pins are used as port output pins. For details of pin states, see Appendix E, Pin Functions. 9.2.3 Peripheral Module Pin Pull-Up Control When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins are pulled up when in the input or high-impedance state. * Relevant Pins SCI related pins MD0/SCK MD7/TXD RXD DMA related pins '5(43 '5(44 TMU related pin TCLK MD1/TXD2 MD8/RTS2 CTS2 DACK0 DACK1 DRAK0 DRAK1 MD2/RXD2 SCK2/05(6(7 * Other Information The setting in this register is invalid in the hardware standby mode. For details of pin states, see Appendix E, Pin Functions. Rev. 6.0, 07/02, page 226 of 986 9.2.4 Standby Control Register 2 (STBCR2) Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via the 5(6(7 pin or due to watchdog timer overflow. Bit: 7 DSLP Initial value: R/W: 0 R/W 6 STHZ* 0 R/W 2 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 1 0 1 MSTP6* MSTP5* 0 R/W 0 R/W Notes: *1 Reserved bit in the SH7750. *2 Reserved bit in the SH7750 and SH7750S. Bit 7--Deep Sleep (DSLP): Specifies a transition to deep sleep mode Bit 7: DSLP 0 1 Description Transition to sleep mode or standby mode on execution of SLEEP instruction, according to setting of STBY bit in STBCR register (Initial value) Transition to deep sleep mode on execution of SLEEP instruction* Note: * When the STBY bit in the STBCR register is 0 Bit 6 (SH7750R Only)--STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0 and 1 pins are set to high-impedance when in hardware standby mode. Bit 6: STHZ 0 1 Description Sets STATUS0, 1 pins to high-impedance when in hardware standby mode (Initial value) Drives STATUS0, 1 pins to LH when in hardware standby mode Bit 6 (SH7750 and SH7750S)--Reserved: Only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. These bits are always read as 0. Bits 5 to 2--Reserved: Only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. These bits are always read as 0. Bits 1 and 0 (SH7750)--Reserved: Only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. These bits are always read as 0. Rev. 6.0, 07/02, page 227 of 986 Bit 1 (SH7750S and SH7750R)--Module Stop 6 (MSTP6): Specifies that the clock supply to the store queue (SQ) in the cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ, and the SQ functions are therefore unavailable. Bit 1: MSTP6 0 1 Description SQ operating Clock supply to SQ stopped (Initial value) Bit 0 (SH7750S and SH7750R)--Module Stop 5 (MSTP5): Specifies stopping of the clock supply to the user break controller (UBC) among the on-chip peripheral modules. See section 20.6, User Break Controller Stop Functions for how to set the clock supply. Bit 0: MSTP5 0 1 Description UBC operating Clock supply to UBC stopped (Initial value) 9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only) Clock-stop register 00 (CLKSTP00) controls the operation clock for peripheral modules. To resume supply of the clock signal, write a 1 to the corresponding bit in the CLKSTPCLR00 register. Writing a 0 to the CLKSTP00 register does not affect the register's value. The CLKSTP00 register is a 32-bit register that can be read from or written to. It is initialized to H'0000 0000 by a power-on reset, but not by a manual reset or when the device enters standby mode. Bit: 31 -- Initial value: R/W: 0 R 30 -- 0 R 29 -- 0 R 28 -- 0 R 27 -- 0 R 26 -- 0 R 25 -- 0 R 24 -- 0 R 23 -- 0 R 22 -- 0 R 21 -- 0 R 20 -- 0 R 19 -- 0 R 18 -- 0 R 17 -- 0 R 16 -- 0 R Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 0 CSTP1 CSTP0 Initial value: R/W: 0 R 0 0 R/W R/W Bits 31 to 2--Reserved: Any data written to these bits should always be 0. These bits are always read as 0. Rev. 6.0, 07/02, page 228 of 986 Bit 1--Clock stop 1 (CSTP1): This bit specifies stopping of the peripheral clock supply to channels 3 and 4 of the timer unit (TMU). Bit 1: CSTP1 0 1 Description Peripheral clock is supplied to TMU channels 3 and 4 Peripheral clock supply to TMU channels 3 and 4 is stopped (Initial value) Bit 0Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt controller (INTC). If this bit is set, INTC does not detect interrupts on the TMU's channels 3 and 4. Bit 0: CSTP0 0 1 Description INTC detects interrupts on channels 3 and 4 of the TMU (Initial value) INTC does not detect interrupts on channels 3 and 4 of the TMU 9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only) The clock-stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that clears the corresponding bits of the CLKSTP00 register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Bits 31 to 0Clock-Stop Clear: Specify whether or not to clear the corresponding bit of the clock-stop setting. See section 9.2.5, Clock-Stop Register 00 (LKSTP00) (SH7750R only), for the correspondence between the bits and the clocks that are stopped. Bits 31 to 0 0 1 Description Does not change the clock-stop setting for the corresponding clock Clears the clock-stop setting for the corresponding clock Rev. 6.0, 07/02, page 229 of 986 9.3 9.3.1 Sleep Mode Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. The on-chip peripheral modules continue to operate, and the clock continues to be output from the CKIO pin. In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin. 9.3.2 Exit from Sleep Mode Sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset. In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction. Exit by Interrupt: When an NMI, IRL, or on-chip peripheral module interrupt is generated, sleep mode is exited and interrupt exception handling is executed. The code corresponding to the interrupt source is set in the INTEVT register. Exit by Reset: Sleep mode is exited by means of a power-on or manual reset via the 5(6(7 pin, or a power-on or manual reset executed when the watchdog timer overflows. 9.4 9.4.1 Deep Sleep Mode Transition to Deep Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. Except for the DMAC*, on-chip peripheral modules continue to operate. The clock continues to be output to the CKIO pin, but all bus access (including auto refresh) stops. When using memory that requires refreshing, set the self-refresh function prior to making the transition to deep sleep mode. In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin. Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you make a transition to deep sleep mode while DMA transfers are in progress, the results of those transfers cannot be guaranteed. Rev. 6.0, 07/02, page 230 of 986 9.4.2 Exit from Deep Sleep Mode As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset. 9.5 9.5.1 Standby Mode Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to standby mode. In standby mode, the on-chip peripheral modules halt as well as the CPU. Clock output from the CKIO pin is also stopped. The CPU and cache register contents are retained. Some on-chip peripheral module registers are initialized. The state of the peripheral module registers in standby mode is shown in table 9.4. Table 9.4 Module Interrupt controller User break controller Bus state controller On-chip oscillation circuits Timer unit Realtime clock Direct memory access controller Serial communication interface State of Registers in Standby Mode Initialized Registers -- -- -- -- TSTR register* -- -- Registers That Retain Their Contents All registers All registers All registers All registers All registers except TSTR All registers All registers See Appendix A, Address List See Appendix A, Address List Notes: DMA transfer should be terminated before making a transition to standby mode. Transfer results are not guaranteed if standby mode is entered during transfer. * Not initialized when the realtime clock (RTC) is in use (see section 12, Timer Unit (TMU)). The procedure for a transition to standby mode is shown below. 1. Clear the TME bit in the WDT timer control register (WTCSR) to 0, and stop the WDT. Set the initial value for the up-count in the WDT timer counter (WTCNT), and set the clock to be used for the up-count in bits CKS2-CKS0 in the WTCSR register. 2. Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction. 3. When standby mode is entered and the chip's internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin. Rev. 6.0, 07/02, page 231 of 986 9.5.2 Exit from Standby Mode Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset via the 5(6(7 pin. Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI, 1 2 IRL* , RTC, or GPIO* interrupt is detected, the WDT starts counting. After the count overflows, clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0 pins both go low. Interrupt exception handling is then executed, and the code corresponding to the interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction. The phase of the CKIO pin clock output may be unstable immediately after an interrupt is detected, until standby mode is exited. Notes: *1 Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL Interrupts), standby mode can be exited by means of IRL3-IRL0 (when the IRL3- IRL0 level is higher than the SR register I3-I0 mask level). *2 GPIO can be used to cancel standby mode when the RTC clock (32.768 kHz) is operating (when the GPIO level is higher than the SR register I3-I0 mask level). Exit by Reset: Standby mode is exited by means of a reset (power-on or manual) via the 5(6(7 pin. The 5(6(7 pin should be held low until clock oscillation stabilizes. The internal clock continues to be output at the CKIO pin. 9.5.3 Clock Pause Function In standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL pin. This function is used as follows. 1. Enter standby mode following the transition procedure described above. 2. When standby mode is entered and the chip's internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin. 3. The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the STATUS0 pin high. 4. When the frequency is changed, input an NMI or IRL interrupt after the change. When the clock is stopped, input an NMI or IRL interrupt after applying the clock. 5. After the time set in the WDT, clock supply begins inside the chip, the STATUS1 and STATUS0 pins both go low, and operation is resumed from interrupt exception handling. Rev. 6.0, 07/02, page 232 of 986 9.6 9.6.1 Module Standby Function Transition to Module Standby Function Setting the MSTP6-MSTP0, CSTP1, and CSTP0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced. In the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules. Rev. 6.0, 07/02, page 233 of 986 Bit CSTP1* 6 Description 0 1 Peripheral clock is supplied to TMU channels 3 and 4 Peripheral clock supplied to TMU channels 3 and 4 is stopped INTC detects interrupts on TMU channels 3 and 4 INTC does not detect interrupts on TMU channels 3 and 4 SQ operates Clock supplied to SQ is stopped UBC operates Clock supplied to UBC is stopped* DMAC operates Clock supplied to DMAC is stopped* SCIF operates Clock supplied to SCIF is stopped TMU operates Clock supplied to TMU is stopped, and register is initialized* RTC operates Clock supplied to RTC is stopped* SCI operates Clock supplied to SCI is stopped 2 1 3 5 CSTP0* 6 0 1 MSTP6* 4 0 1 MSTP5* 4 0 1 MSTP4 0 1 MSTP3 0 1 MSTP2 0 1 MSTP1 0 1 MSTP0 0 1 Notes: *1 The register initialized is the same as in standby mode, but initialization is not performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)). *2 The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock (RTC)). *3 Terminate DMA transfers prior to making the transition to module standby mode. If you make a transition to module standby mode while DMA transfers are in progress, the results of those transfers cannot be guaranteed. *4 SH7750S, SH7750R only *5 For details, see section 20.6, User Break Controller Stop Functions. *6 SH7750R only 9.6.2 Exit from Module Standby Function The module standby function is exited by clearing the MSTP6-MSTP0, CSTP1, and CSTP0 bits to 0, or by a power-on reset via the 5(6(7 pin or a power-on reset caused by watchdog timer overflow. Rev. 6.0, 07/02, page 234 of 986 9.7 9.7.1 Hardware Standby Mode (SH7750S, SH7750R Only) Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all modules other than the RTC stop, as in the standby mode selected using the SLEEP command. Hardware standby mode differs from standby mode as follows: 1. Interrupts and manual resets are not available; 2. All output pins other than the STATUS pin are in the high-impedance state and the pull-up resistance is off. 3. Even when no power is supplied to power pins other than the RTC power supply pin, the RTC continues to operate. The status of the STATUS pin is determined by the STHZ bit of STBCR2. See appendix E, Pin Functions, for details of output pin states. Operation when a low-level is input to the CA pin when in the standby mode depends on the CPG status, as follows: 1. In standby mode The clock remains stopped and a transition is made to the hardware standby state. 2. When WDT is operating when standby mode is exited by interrupt Standby mode is momentarily exited, the CPU restarts, and then a transition is made to hardware standby mode. Note that the level of the CA pin must be kept low while in hardware standby mode. 9.7.2 Exit from Hardware Standby Mode Hardware standby mode can only be exited by effecting a power-on reset. Setting the CA pin level high after the 5(6(7 pin level has been set low and the SCK2 pin high starts the clock to oscillate. The 5(6(7 pin level should be kept low until the clock has stabilized, then set high so that the CPU starts the power-on reset procedure. Note that hardware standby mode cannot be exited using interrupts or a manual reset. 9.7.3 Usage Notes The CA pin level must be kept high during the power-on oscillation settling period when the RTC power supply is started (figure 9.15). Rev. 6.0, 07/02, page 235 of 986 9.8 STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timing is shown below. The meaning of the STATUS pin settings is as follows: Reset: Sleep: Standby: Normal: HH (STATUS1 high, STATUS0 high) HL (STATUS1 high, STATUS0 low) LH (STATUS1 low, STATUS0 high) LL (STATUS1 low, STATUS0 low) The meaning of the clock units is as follows: Bcyc: Bus clock cycle Pcyc: Peripheral clock cycle Rev. 6.0, 07/02, page 236 of 986 9.8.1 In Reset Power-On Reset CKIO PLL stabilization time SCK2 STATUS Normal Reset 0-30 Bcyc 0-5 Bcyc Normal Figure 9.1 STATUS Output in Power-On Reset Manual Reset CKIO * SCK2 STATUS Normal Reset 0-30 Bcyc 0 Bcyc Normal Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle. Figure 9.2 STATUS Output in Manual Reset Rev. 6.0, 07/02, page 237 of 986 9.8.2 In Exit from Standby Mode Standby Interrupt Oscillation stops Interrupt request WDT overflow CKIO WDT count STATUS Normal Standby Normal Figure 9.3 STATUS Output in Standby Interrupt Sequence Standby Power-On Reset Oscillation stops Reset CKIO *1 SCK2 STATUS Normal Standby *2 Reset Normal 0-10 Bcyc 0-30 Bcyc Notes: *1 When standby mode is exited by means of a power-on reset, a WDT count is not low for the PLL oscillation stabilization time. performed. Hold *2 Undefined Figure 9.4 STATUS Output in Standby Power-On Reset Sequence Rev. 6.0, 07/02, page 238 of 986 Standby Manual Reset Oscillation stops Reset CKIO *1 SCK2 STATUS Normal Standby *2 Reset Normal 0-10 Bcyc 0-30 Bcyc Notes: *1 When standby mode is exited by means of a manual reset, a WDT count is not low for the PLL oscillation stabilization time. performed. Hold *2 Undefined Figure 9.5 STATUS Output in Standby Manual Reset Sequence Rev. 6.0, 07/02, page 239 of 986 9.8.3 In Exit from Sleep Mode Sleep Interrupt Interrupt request CKIO STATUS Normal Sleep Normal Figure 9.6 STATUS Output in Sleep Interrupt Sequence Sleep Power-On Reset Reset CKIO *1 SCK2 STATUS Normal Sleep *2 Reset Normal 0-10 Bcyc 0-30 Bcyc low for the Notes: *1 When sleep mode is exited by means of a power-on reset, hold oscillation stabilization time. *2 Undefined Figure 9.7 STATUS Output in Sleep Power-On Reset Sequence Rev. 6.0, 07/02, page 240 of 986 Sleep Manual Reset Reset CKIO * SCK2 STATUS Normal Sleep Reset Normal 0-30 Bcyc Note: * Hold low until STATUS = reset. 0-30 Bcyc Figure 9.8 STATUS Output in Sleep Manual Reset Sequence Rev. 6.0, 07/02, page 241 of 986 9.8.4 In Exit from Deep Sleep Mode Deep Sleep Interrupt Interrupt request CKIO STATUS Normal Sleep Normal Figure 9.9 STATUS Output in Deep Sleep Interrupt Sequence Deep Sleep Power-On Reset Reset CKIO *1 SCK2 STATUS Normal Sleep *2 Reset Normal 0-10 Bcyc 0-30 Bcyc low for the Notes: *1 When deep sleep mode is exited by means of a power-on reset, hold oscillation stabilization time. *2 Undefined Figure 9.10 STATUS Output in Deep Sleep Power-On Reset Sequence Rev. 6.0, 07/02, page 242 of 986 Deep Sleep Manual Reset Reset CKIO * SCK2 STATUS Normal Sleep Reset Normal 0-30 Bcyc Note: * Hold low until STATUS = reset. 0-30 Bcyc Figure 9.11 STATUS Output in Deep Sleep Manual Reset Sequence Rev. 6.0, 07/02, page 243 of 986 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. The CA pin level must be kept low while in hardware standby mode. After setting the 5(6(7 pin level low, the clock starts when the CA pin level is switched to high. CKIO CA SCK2 (High) STATUS Normal*1 Standby*3 *2 Reset 0-10 Bcyc Waiting for end of bus cycle Notes: *1 Same at sleep and reset. *2 Undefined *3 High impedance when STBCR2. STHZ = 0 0-10 Bcyc Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) Rev. 6.0, 07/02, page 244 of 986 Interrupt request WDT overflow CKIO CA (High) SCK2 (High) STATUS Standby Normal 0-10 Bcyc Standby* WDT count Note: * High impedance when STBCR2. STHZ = 0 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) Rev. 6.0, 07/02, page 245 of 986 VDDQ* VDD VDD min CA SCK2 Min 0s Min 0s Max 50 s Note: * VDDQ, VDD-CPG, VDD-PLL1, VDD-PLL2 Figure 9.14 Timing When Power Other than VDD-RTC is Off VDD-RTC Power-on oscillation setting time CA VDD, VDDQ* Min 0s SCK2 Note: * VDD, VDD-PLL1/2, VDDQ, VDD-CPG Figure 9.15 Timing When VDD-RTC Power is Off On Rev. 6.0, 07/02, page 246 of 986 Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control. The WDT is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed. It can be used as a normal watchdog timer or an interval timer. 10.1.1 Features The CPG has the following features: * Three clocks The CPG can generate independently the CPU clock (I) used by the CPU, FPU, caches, and TLB, the peripheral module clock (P) used by the peripheral modules, and the bus clock (CKIO) used by the external bus interface. * Six clock modes Any of six clock operating modes can be selected, with different combinations of CPU clock, bus clock, and peripheral module clock division ratios after a power-on reset. * Frequency change function PLL (phase-locked loop) circuits and a frequency divider in the CPG enable the CPU clock, bus clock, and peripheral module clock frequencies to be changed independently. Frequency changes are performed by software in accordance with the settings in the frequency control register (FRQCR). * PLL on/off control Power consumption can be reduced by stopping the PLL circuits during low-frequency operation. * Power-down mode control It is possible to stop the clock in sleep mode and standby mode, and to stop specific modules with the module standby function. Rev. 6.0, 07/02, page 247 of 986 The WDT has the following features * Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed. * Can be switched between watchdog timer mode and interval timer mode * Internal reset generation in watchdog timer mode An internal reset is executed on counter overflow. Power-on reset or manual reset can be selected. * Interrupt generation in interval timer mode An interval timer interrupt is generated on counter overflow. * Selection of eight counter input clocks Any of eight clocks can be selected, scaled from the x1 clock of frequency divider 2 shown in figure 10.1. The CPG is described in sections 10.2 to 10.6, and the WDT in sections 10.7 to 10.9. Rev. 6.0, 07/02, page 248 of 986 10.2 10.2.1 Overview of CPG Block Diagram of CPG Figure 10.1 (1) shows a block diagram of the CPG in the SH7750 and SH7750S, and figure 10.1 (2) a block diagram of the CPG in the SH7750R. Oscillator circuit Frequency divider 2 x1 x 1/2 x 1/3 x 1/4 x 1/6 x 1/8 PLL circuit 1 x6 CPU clock (Io) cycle Icyc XTAL EXTAL MD8 Crystal oscillator Frequency divider 1 x 1/2 Peripheral module clock (Po) cycle Pcyc Bus clock (Bo) cycle Bcyc PLL circuit 2 x1 CKIO CPG control unit MD2 MD1 MD0 Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 Bus interface Internal bus FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) Rev. 6.0, 07/02, page 249 of 986 Oscillator circuit Frequency divider 2 PLL circuit 1 x6 x 12 x1 x 1/2 x 1/3 x 1/4 x 1/6 x 1/8 CPU clock (Io) cycle Icyc XTAL EXTAL MD8 Crystal oscillator Peripheral module clock (Po) cycle Pcyc Bus clock (Bo) cycle Bcyc PLL circuit 2 x1 CKIO CPG control unit MD2 MD1 MD0 Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 Bus interface Internal bus FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 Figure 10.1 (2) Block Diagram of CPG (SH7750R) Rev. 6.0, 07/02, page 250 of 986 The function of each of the CPG blocks is described below. PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillator by 6 with the SH7750 and SH7750S, and by 6 or 12 with the SH7750R. Starting and stopping is controlled by a frequency control register setting. Control is performed so that the internal clock rising edge phase matches the input clock rising edge phase. PLL Circuit 2: PLL circuit 2 coordinates the phases of the bus clock and the CKIO pin output clock. Starting and stopping is controlled by a frequency control register setting. Crystal Oscillator: This is the oscillator circuit used when a crystal resonator is connected to the XTAL and EXTAL pins. Use of the crystal oscillator can be selected with the MD8 pin. Frequency Divider 1 (SH7750 and SH7750S only): Frequency divider 1 has a function for adjusting the clock waveform duty to 50% by halving the input clock frequency when clock input from the EXTAL pin is supplied internally without using PLL circuit 1. Frequency Divider 2: Frequency divider 2 generates the CPU clock (I), bus clock (B), and peripheral module clock (P). The division ratio is set in the frequency control register. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency by means of the MD pins and frequency control register. Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillation circuits and other modules when the clock is switched and in sleep and standby modes. Frequency Control Register (FRQCR): The frequency control register contains control bits for clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios. Standby Control Register (STBCR): The standby control register contains power save mode control bits. For further information on the standby control register, see section 9, Power-Down Modes. Standby Control Register 2 (STBCR2): Standby control register 2 contains a power save mode control bit. For further information on standby control register 2, see section 9, Power-Down Modes. Rev. 6.0, 07/02, page 251 of 986 10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Mode control pins Abbreviation MD0 MD1 MD2 Crystal I/O pins (clock input pins) XTAL EXTAL MD8 Output Input Input Connects crystal resonator Connects crystal resonator, or used as external clock input pin Selects use/non-use of crystal resonator When MD8 = 0, external clock is input from EXTAL When MD8 = 1, crystal resonator is connected directly to EXTAL and XTAL Clock output pin CKIO enable pin CKIO CKE Output Output Used as external clock output pin Level can also be fixed 0 when CKIO output clock is unstable and in case of synchronous DRAM self-refreshing* I/O Input Function Set clock operating mode Note: * Set to 1 in a power-on reset. For details of synchronous DRAM self-refreshing, see section 13.3.5, Synchronous DRAM Interface. 10.2.3 CPG Register Configuration Table 10.2 shows the CPG register configuration. Table 10.2 CPG Register Name Frequency control register Abbreviation FRQCR R/W R/W Initial Value Undefined* P4 Address H'FFC00000 Area 7 Address H'1FC00000 Access Size 16 Note: * Depends on the clock operating mode set by pins MD2-MD0. Rev. 6.0, 07/02, page 252 of 986 10.3 Clock Operating Modes Tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various combinations of mode control pin (MD2-MD0) settings (initial settings such as the frequency division ratio). Table 10.4 shows FRQCR settings and internal clock frequencies. Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S) External Pin Combination Clock Operating Mode 0 1 2 3 4 5 1 0 1 1/2 Frequency Divider Off Off On Off On Off CPU Clock 6 6 3 6 3 6 Frequency (vs. Input Clock) Bus Clock 3/2 1 1 2 3/2 3 Peripheral Module Clock 3/2 1 1/2 1 3/4 3/2 FRQCR Initial Value H'0E1A H'0E23 H'0E13 H'0E13 H'0E0A H'0E0A MD2 0 MD1 0 MD0 0 1 0 1 0 1 PLL1 On On On On On On PLL2 On On On On On On Notes: 1. Turning on/off of the 1/2 frequency divider is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. Table 10.3 (2) Clock Operating Modes (SH7750R) External Pin Combination MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 PLL1 On (x12) On (x12) On (x6) On (x12) On (x6) On (x12) Off (x6) PLL2 On On On On On On Off CPU Clock 12 12 6 12 6 12 1 Frequency (vs. Input Clock) Bus Clock 3 3/2 2 4 3 6 1/2 Peripheral Module Clock 3 3/2 1 2 3/2 3 1/2 FRQCR Initial Value H'0E1A H'0E2C H'0E13 H'0E13 H'0E0A H'0E0A H'0808 Clock Operating Mode 0 1 2 3 4 5 6 Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. Rev. 6.0, 07/02, page 253 of 986 Table 10.4 FRQCR Settings and Internal Clock Frequencies FRQCR (Lower 9 Bits) H'008 H'00A H'00C H'011 H'013 H'01A H'01C H'023 H'02C H'05A H'05C H'063 H'06C H'0A3 H'0EC 1/3 1/4 1/6 1/8 1/6 1/8 1/2 1/6 1/8 1/4 1/4 1/3 Frequency Division Ratio CPU Clock 1 Bus Clock 1/2 Peripheral Module Clock 1/2 1/4 1/8 1/3 1/6 1/4 1/8 1/6 1/8 1/4 1/8 1/6 1/8 1/6 1/8 Note: For the lower 9 bits of FRQCR, do not set values other than those shown in the table. 10.4 10.4.1 CPG Register Description Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be used on FRQCR. FRQCR is initialized only by a power-on reset via the 5(6(7 pin. The initial value of each bit is determined by the clock operating mode. Rev. 6.0, 07/02, page 254 of 986 Bit: 15 -- 14 -- 0 R/W 6 IFC0 -- R/W 13 -- 0 R/W 5 BFC2 -- R/W 12 -- 0 R 4 BFC1 -- R/W 11 10 9 8 IFC2 -- R/W 0 PFC0 -- R/W CKOEN PLL1EN PLL2EN 1 R/W 3 BFC0 -- R/W 1 R/W 2 PFC2 -- R/W 1 R/W 1 PFC1 -- R/W Initial value: R/W: Bit: 0 R/W 7 IFC1 Initial value: R/W: -- R/W Bits 15 to 12--Reserved: These bits are always read as 0, and should only be written with 0. Bit 11--Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the high-impedance state. When the CKIO pin goes to the highimpedance state, operation continues at the operating frequency before this state was entered. When the CKIO pin becomes high-impedance, it is pulled up. Bit 11: CKOEN 0 1 Description CKIO pin goes to high-impedance state (pulled up*) Clock is output from CKIO pin (Initial value) Note: * It is not pulled up in hardware standby mode. Bit 10--PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off. Bit 10: PLL1EN 0 1 Description PLL circuit 1 is not used PLL circuit 1 is used (Initial value) Bit 9--PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off. Bit 9: PLL2EN 0 1 Description PLL circuit 2 is not used PLL circuit 2 is used (Initial value) Rev. 6.0, 07/02, page 255 of 986 Bits 8 to 6--CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 8: IFC2 0 Bit 7: IFC1 0 Bit 6: IFC0 0 1 1 0 1 1 0 0 1 Other than the above Description x1 x 1/2 x 1/3 x 1/4 x 1/6 x 1/8 Setting prohibited (Do not set) Bits 5 to 3--Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 5: BFC2 0 Bit 4: BFC1 0 Bit 3: BFC0 0 1 1 0 1 1 0 0 1 Other than the above Description x1 x 1/2 x 1/3 x 1/4 x 1/6 x 1/8 Setting prohibited (Do not set) Bits 2 to 0--Peripheral Module Clock Frequency Division Ratio (PFC): These bits specify the peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 2: PFC2 0 Bit 1: PFC1 0 Bit 0: PFC0 0 1 1 0 1 1 0 0 Description x 1/2 x 1/3 x 1/4 x 1/6 x 1/8 Setting prohibited (Do not set) Other than the above Rev. 6.0, 07/02, page 256 of 986 10.5 Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register. These methods are described below. 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off) When PLL circuit 1 is changed from the stopped to started state, a PLL stabilization time is required. The oscillation stabilization time count is performed by the on-chip WDT. 1. Set a value in WDT to provide the specified oscillation stabilization time, and stop the WDT. The following settings are necessary: WTCSR register TME bit = 0: WDT stopped WTCSR register CKS2-CKS0 bits: WDT count clock division ratio WTCNT counter: Initial counter value 2. Set the PLL1EN bit to 1. 3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On) When PLL circuit 2 is on, a PLL circuit 1 and PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in 10.5.1. 2. Set the PLL1EN bit to 1. 3. Internal processor operation stops temporarily, PLL circuit 1 oscillates, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, PLL circuit 2 starts oscillating. The WDT resumes its upcount from the value set in step 1 above. During this time, also, the internal clock is stopped and an unstable clock is output to the CKIO pin. 5. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. Rev. 6.0, 07/02, page 257 of 986 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On) If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in 10.5.1. 2. Set the BFC2-BFC0 bits to the desired value. 3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off) If PLL circuit 2 is off when the bus clock frequency division ratio is changed, a WDT count is not performed. 1. Set the BFC2-BFC0 bits to the desired value. 2. The set clock is switched to immediately. 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio When the CPU or peripheral module clock frequency division ratio is changed, a WDT count is not performed. 1. Set the IFC2-IFC0 or PFC2-PFC0 bits to the desired value. 2. The set clock is switched to immediately. 10.6 Output Clock Control The CKIO pin can be switched between clock output and a fixed level setting by means of the CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is pulled up. Rev. 6.0, 07/02, page 258 of 986 10.7 10.7.1 Overview of Watchdog Timer Block Diagram Figure 10.2 shows a block diagram of the WDT. WDT Standby release Standby control Standby mode Frequency divider 2 x1 clock Internal reset request Reset control Clock selection Frequency divider Clock selector Interrupt request Interrupt control Overflow Clock WTCSR WTCNT Bus interface WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter Figure 10.2 Block Diagram of WDT Rev. 6.0, 07/02, page 259 of 986 10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Name Watchdog timer counter Watchdog timer control/status register Abbreviation WTCNT WTCSR R/W R/W* R/W* Initial Value H'00 H'00 P4 Address H'FFC00008 H'FFC0000C Area 7 Address H'1FC00008 H'1FC0000C Access Size R: 8, W: 16* R: 8, W: 16* Note: * Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte access when reading. 10.8 10.8.1 WDT Register Descriptions Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that counts up on the selected clock. When WTCNT overflows, a reset is generated in watchdog timer mode, or an interrupt in interval timer mode. WTCNT is initialized to H'00 only by a power-on reset via the 5(6(7 pin. To write to the WTCNT counter, use a word-size access with the upper byte set to H'5A. To read WTCNT, use a byte-size access. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 6.0, 07/02, page 260 of 986 10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the 5(6(7 pin. It retains its value in an internal reset due to WDT overflow. When used to count the clock stabilization time when exiting standby mode, WTCSR retains its value after the counter overflows. To write to the WTCSR register, use a word-size access with the upper byte set to H'A5. To read WTCSR, use a byte-size access. Bit: 7 TME Initial value: R/W: 0 R/W 6 WT/,7 0 R/W 5 RSTS 0 R/W 4 WOVF 0 R/W 3 IOVF 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7--Timer Enable (TME): Specifies starting and stopping of timer operation. Clear this bit to 0 when using the WDT in standby mode or to change a clock frequency. Bit 7: TME 0 1 Description Up-count stopped, WTCNT value retained Up-count started (Initial value) Bit 6--Timer Mode Select (WT/,7 Specifies whether the WDT is used as a watchdog timer or ,7): ,7 interval timer. Bit 6: WT/,7 ,7 0 1 Description Interval timer mode Watchdog timer mode (Initial value) Note: The up-count may not be performed correctly if WT/,7 is modified while the WDT is running. Bit 5--Reset Select (RSTS): Specifies the kind of reset to be performed when WTCNT overflows in watchdog timer mode. This setting is ignored in interval timer mode. Bit 5: RSTS 0 1 Description Power-on reset Manual reset (Initial value) Rev. 6.0, 07/02, page 261 of 986 Bit 4--Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. Bit 4: WOVF 0 1 Description No overflow WTCNT has overflowed in watchdog timer mode (Initial value) Bit 3--Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. Bit 3: IOVF 0 1 Description No overflow WTCNT has overflowed in interval timer mode (Initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2-CKS0): These bits select the clock used for the WTCNT count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1 off, and PLL circuit 1 on (x6). Note: * When PLL1 is switched on or off, the clock following the switch is used. Description Bit 2: CKS2 0 Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Division Ratio 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096 (Initial value) Overflow Period 41 s 82 s 164 s 328 s 656 s 1.31 ms 2.62 ms 5.25 ms Note: The up-count may not be performed correctly if bits CKS2-CKS0 are modified while the WDT is running. Always stop the WDT before modifying these bits. Rev. 6.0, 07/02, page 262 of 986 10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to with a word transfer instruction. They cannot be written to with a byte or longword transfer instruction. When writing to WTCNT, perform the transfer with the upper byte set to H'5A and the lower byte containing the write data. When writing to WTCSR, perform the transfer with the upper byte set to H'A5 and the lower byte containing the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. The write formats are shown in figure 10.3. WTCNT write 15 Address: H'FFC00008 (H'1FC00008) H'5A 8 7 Write data 0 WTCSR write 15 Address: H'FFC0000C (H'1FC0000C) H'A5 8 7 Write data 0 Figure 10.3 Writing to WTCNT and WTCSR 10.9 10.9.1 Using the WDT Standby Clearing Procedure The WDT is used when clearing standby mode by means of an NMI or other interrupt. The procedure is shown below. (As the WDT does not operate when standby mode is cleared with a reset, the 5(6(7 pin should be held low until the clock stabilizes.) 1. Be sure to clear the TME bit in the WTCSR register to 0 before making a transition to standby mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. Select the count clock to be used with bits CKS2-CKS0 in the WTCSR register, and set the initial value in the WTCNT counter. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time. For details of the clock oscillation stabilization time, see section 22.3.1, Clock and Control Signal Timing. 3. Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction. Rev. 6.0, 07/02, page 263 of 986 4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt. 5. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. 6. The counter stops at a value of H'00-H'01. The value at which the counter stops depends on the clock ratio. 10.9.2 Frequency Changing Procedure The WDT is used in a frequency change using the PLL. It is not used when the frequency is changed simply by making a frequency divider switch. 1. Be sure to clear the TME bit in the WTCSR register to 0 before making a frequency change. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. Select the count clock to be used with bits CKS2-CKS0 in the WTCSR register, and set the initial value in the WTCNT counter. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time. For details of the clock oscillation stabilization time, see section 22.3.1, Clock and Control Signal Timing. 3. When the frequency control register (FRQCR) is modified, the clock stops, and the standby state is entered temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. 5. 6. The counter stops at a value of H'00-H'01. The value at which the counter stops depends on the clock ratio. When re-setting WTCNT immediately after modifying the frequency control register (FRQCR), first read the counter and confirm that its value is as described in step 5 above. Using Watchdog Timer Mode 10.9.3 1. Set the WT/,7 bit in the WTCSR register to 1, select the type of reset with the RSTS bit, and the count clock with bits CKS2-CKS0, and set the initial value in the WTCNT counter. 2. When the TME bit in the WTCSR register is set to 1, the count starts in watchdog timer mode. 3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does not overflow. 4. When the counter overflows, the WDT sets the WOVF flag in the WTCSR register to 1, and generates a reset of the type specified by the RSTS bit. The counter then continues counting. Rev. 6.0, 07/02, page 264 of 986 10.9.4 Using Interval Timer Mode When the WDT is operating in interval timer mode, an interval timer interrupt is generated each time the counter overflows. This enables interrupts to be generated at fixed intervals. 1. Clear the WT/,7 bit in the WTCSR register to 0, select the count clock with bits CKS2-CKS0, and set the initial value in the WTCNT counter. 2. When the TME bit in the WTCSR register is set to 1, the count starts in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in the WTCSR register to 1, and sends an interval timer interrupt request to INTC. The counter continues counting. 10.10 Notes on Board Design When Using a Crystal Resonator: Place the crystal resonator and capacitors close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins. CL1 CL2 Avoid crossing signal lines R Recommended values CL1 = CL2 = 0-33 pF R = 0 EXTAL XTAL SH7750 Series Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. Figure 10.4 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin. Rev. 6.0, 07/02, page 265 of 986 When Using a PLL Oscillator Circuit: Separate VDD-CPG and VSS-CPG from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and RB and bypass capacitors CPB and CB close to the pins as noise filters. RCB1 VDD-PLL1 CPB1 VSS-PLL1 Recommended values RCB1 = RCB2 = 10 CPB1 = CPB2 = 10 F RB = 10 CB = 10 F RCB2 VDD-PLL2 SH7750 Series CPB2 VSS-PLL2 RB VDD-CPG CB VSS-CPG 3.3 V Figure 10.5 Points for Attention when Using PLL Oscillator Circuit Rev. 6.0, 07/02, page 266 of 986 Section 11 Realtime Clock (RTC) 11.1 Overview The SH7750 Series includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC. 11.1.1 Features The RTC has the following features. * Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years. * 1 to 64 Hz timer (binary display) The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider * Start/stop function * 30-second adjustment function * Alarm interrupts Comparison with second, minute, hour, day-of-week, day, month, or year (year is available only with the SH7750R) can be selected as the alarm interrupt condition * Periodic interrupts An interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds can be selected * Carry interrupt Carry interrupt function indicating a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read * Automatic leap year adjustment Rev. 6.0, 07/02, page 267 of 986 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. ATI RTCCLK 16.384 kHz PRI CUI RESET, STBY, etc Prescaler 128 Hz 32.768 kHz RTC crystal oscillator RTC operation control unit RCR1 RCR2 Counter unit R64CNT Interrupt control unit RCR3* RSECCNT RMINCNT RHRCNT RDAYCNT RWKCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR RYRAR* To registers Bus interface Internal peripheral module bus Note: * SH7750R only Figure 11.1 Block Diagram of RTC Rev. 6.0, 07/02, page 268 of 986 11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name RTC oscillator crystal pin RTC oscillator crystal pin Clock input/clock output Abbreviation EXTAL2 XTAL2 TCLK I/O Input Output I/O Function Connects crystal to RTC oscillator Connects crystal to RTC oscillator External clock input pin/input capture control input pin/RTC output pin (shared with TMU) RTC oscillator power supply pin* RTC oscillator GND pin* Dedicated RTC power supply Dedicated RTC GND pin VDD-RTC VSS-RTC -- -- Note: * Power must be supplied to the RTC power supply pins even when the RTC is not used. 11.1.4 Register Configuration Table 11.2 summarizes the RTC registers. Table 11.2 RTC Registers Initialization Abbreviation R64CNT RSECCNT RMINCNT RHRCNT RWKCNT PowerOn Reset Manual Standby Initial Reset Mode Value Area 7 P4 Address Address Access Size Name 64 Hz counter Second counter Minute counter Hour counter Day-ofweek counter Day counter R/W R R/W R/W R/W R/W Counts Counts Counts Undefined Counts Counts Counts Undefined Counts Counts Counts Undefined Counts Counts Counts Undefined Counts Counts Counts Undefined H'FFC80000 H'1FC80000 8 H'FFC80004 H'1FC80004 8 H'FFC80008 H'1FC80008 8 H'FFC8000C H'1FC8000C 8 H'FFC80010 H'1FC80010 8 RDAYCNT R/W Counts Counts Counts Undefined H'FFC80014 H'1FC80014 8 Rev. 6.0, 07/02, page 269 of 986 Table 11.2 RTC Registers (cont) Initialization Name Abbreviation R/W Power-On Manual Reset Reset Counts Counts Counts Counts Standby Initial Mode Value Counts Counts Held Undefined Undefined 1 Area 7 P4 Address Address Access Size Month RMONCNT R/W counter Year RYRCNT counter Second RSECAR alarm register Minute RMINAR alarm register Hour RHRAR alarm register Day-of- RWKAR week alarm register Day RDAYAR alarm register Month RMONAR alarm register RTC RCR1 control register 1 RTC RCR2 control register 2 RTC RCR3 control register 5 3* Year RYRAR alarm 5 register* R/W R/W H'FFC80018 H'1FC80018 8 H'FFC8001C H'1FC8001C 16 1 Initialized* Held Undefined* H'FFC80020 H'1FC80020 8 R/W 1 Initialized* Held Held Undefined* H'FFC80024 H'1FC80024 8 1 R/W 1 Initialized* Held Held Undefined* H'FFC80028 H'1FC80028 8 1 R/W 1 Initialized* Held Held Undefined* H'FFC8002C H'1FC8002C 8 1 R/W 1 Initialized* Held Held Undefined* H'FFC80030 H'1FC80030 8 1 R/W 1 Initialized* Held Held Undefined* H'FFC80034 H'1FC80034 8 1 R/W Initialized Initialized Held 3 H'00* H'FFC80038 H'1FC80038 8 R/W 2 Initialized Initialized* Held 4 H'09* H'FFC8003C H'1FC8003C 8 R/W Initialized Held Held H'00 H'FFC80050 H'1FC80050 8 R/W Held Held Held Undefined H'FFC80054 H'1FC80054 16 Notes: *1 *2 *3 *4 *5 The ENB bit in each register is initialized. Bits other than the RTCEN bit and START bit are initialized. The value of the CF bit and AF bit is undefined. The value of the PEF bit is undefined. SH7750R only Rev. 6.0, 07/02, page 270 of 986 11.2 11.2.1 Register Descriptions 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read. In this case, the read value is not valid, and so R64CNT must be read again after first writing 0 to the CF bit in RCR1 to clear it. When the RESET bit or ADJ bit in RTC control register 2 (RCR2) is set to 1, the RTC frequency divider is initialized and R64CNT is initialized to H'00. R64CNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0 and cannot be modified. Bit: 7 -- Initial value: R/W: 0 R 6 1 Hz R 5 2 Hz R 4 4 Hz R 3 8 Hz R 2 16 Hz R 1 32 Hz R 0 64 Hz R Undefined Undefined Undefined Undefined Undefined Undefined Undefined 11.2.2 Second Counter (RSECCNT) RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded second value in the RTC. It counts on the carry (transition of the R64CNT.1Hz bit from 0 to 1) generated once per second by the 64 Hz counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RSECCNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 -- Initial value: R/W: 0 R 6 5 10-second units R/W R/W R/W R/W 4 3 2 1 0 1-second units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.0, 07/02, page 271 of 986 11.2.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RMINCNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 -- Initial value: R/W: 0 R 6 5 10-minute units 4 3 2 1 0 1-minute units Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W 11.2.4 Hour Counter (RHRCNT) RHRCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute counter. The setting range is decimal 00 to 23. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RHRCNT is not initialized by a power-on or manual reset, or in standby mode. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0 10-hour units R/W R/W R/W 1-hour units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.0, 07/02, page 272 of 986 11.2.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RWKCNT is not initialized by a power-on or manual reset, or in standby mode. Bits 7 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 -- Initial value: R/W: Day-of-week code Day of week 0 R 0 Sun 6 -- 0 R 1 Mon 5 -- 0 R 2 Tue 4 -- 0 R 3 Wed 3 -- 0 R 4 Thu 2 1 Day of week code Undefined Undefined Undefined 0 R/W 5 Fri R/W 6 R/W Sat Rev. 6.0, 07/02, page 273 of 986 11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RDAYCNT is not initialized by a power-on or manual reset, or in standby mode. The setting range for RDAYCNT depends on the month and whether the year is a leap year, so care is required when making the setting. Taking the year counter (RYRCNT) value as the year, leap year calculation is performed according to whether or not the value is divisible by 400, 100, and 4. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0 10-day units 1-day units Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W 11.2.7 Month Counter (RMONCNT) RMONCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded month value in the RTC. It counts on the carry generated once per month by the day counter. The setting range is decimal 01 to 12. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RMONCNT is not initialized by a power-on or manual reset, or in standby mode. Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Rev. 6.0, 07/02, page 274 of 986 Bit: 7 -- 6 -- 0 R 5 -- 0 R 4 10-month unit R/W 3 2 1 0 1-month units Initial value: R/W: 0 R Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W 11.2.8 Year Counter (RYRCNT) RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter. The setting range is decimal 0000 to 9999. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RYRCNT is not initialized by a power-on or manual reset, or in standby mode. Bit: 15 14 13 12 11 10 9 8 1000-year units R/W: Bit: R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 100-year units R/W 2 R/W 1 R/W 0 Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 10-year units 1-year units Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W Rev. 6.0, 07/02, page 275 of 986 11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RSECAR is initialized to 0 by a power-on reset. The other fields in RSECAR are not initialized by a power-on or manual reset, or in standby mode. Bit: 7 ENB Initial value: R/W: 0 R/W 6 5 10-second units 4 3 2 1 0 1-second units Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W 11.2.10 Minute Alarm Register (RMINAR) RMINAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCDcoded minute value counter, RMINCNT. When the ENB bit is set to 1, the RMINAR value is compared with the RMINCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RMINAR is initialized by a power-on reset. The other fields in RMINAR are not initialized by a power-on or manual reset, or in standby mode. Bit: 7 ENB Initial value: R/W: 0 R/W R/W 6 5 10-minute units R/W R/W R/W 4 3 2 1 0 1-minute units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.0, 07/02, page 276 of 986 11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 23 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RHRAR is initialized by a power-on reset. The other fields in RHRAR are not initialized by a power-on or manual reset, or in standby mode. Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 4 3 2 1 0 10-hour units 1-hour units Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W 11.2.12 Day-of-Week Alarm Register (RWKAR) RWKAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded day-of-week value counter, RWKCNT. When the ENB bit is set to 1, the RWKAR value is compared with the RWKCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 0 to 6 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RWKAR is initialized by a power-on reset. The other fields in RWKAR are not initialized by a power-on or manual reset, or in standby mode. Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Rev. 6.0, 07/02, page 277 of 986 Bit: 7 ENB 6 -- 0 R 1 Mon 5 -- 0 R 2 Tue 4 -- 0 R 3 Wed 3 -- 0 R 4 Thu 2 1 Day of week code 0 Initial value: R/W: Day-of-week code Day of week 0 R/W 0 Sun Undefined Undefined Undefined R/W 5 Fri R/W 6 R/W Sat 11.2.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCDcoded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is compared with the RDAYCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 01 to 31 + ENB bit. The RTC will not operate normally if any other value is set. The setting range for RDAYAR depends on the month and whether the year is a leap year, so care is required when making the setting. The ENB bit in RDAYAR is initialized by a power-on reset. The other fields in RDAYAR are not initialized by a power-on or manual reset, or in standby mode. Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 4 3 2 1 0 10-day units R/W R/W R/W 1-day units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.0, 07/02, page 278 of 986 11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCDcoded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 01 to 12 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RMONAR is initialized by a power-on reset. The other fields in RMONAR are not initialized by a power-on or manual reset, or in standby mode. Bits 6 and 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 10-month unit 3 2 1 0 1-month units Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W 11.2.15 RTC Control Register 1 (RCR1) RCR1 is an 8-bit readable/writable register containing a carry flag and alarm flag, plus flags to enable or disable interrupts for these flags. The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value of bits other than CIE and AIE is undefined. In standby mode RCR1 is not initialized, and retains its current value. Bit: 7 CF R/W: R/W 6 -- R 5 -- R 4 CIE 0 R/W 3 AIE 0 R/W 2 -- R 1 -- R 0 AF R/W Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.0, 07/02, page 279 of 986 Bit 7--Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again. Bit 7: CF 0 Description No second counter carry, or 64 Hz counter carry when 64 Hz counter is read [Clearing condition] When 0 is written to CF 1 Second counter carry, or 64 Hz counter carry when 64 Hz counter is read [Setting conditions] * * Generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read When 1 is written to CF Bit 4--Carry Interrupt Enable Flag (CIE): Enables or disables interrupt generation when the carry flag (CF) is set to 1. Bit 4: CIE 0 1 Description Carry interrupt is not generated when CF flag is set to 1 Carry interrupt is generated when CF flag is set to 1 (Initial value) Bit 3--Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the alarm flag (AF) is set to 1. Bit 3: AIE 0 1 Description Alarm interrupt is not generated when AF flag is set to 1 Alarm interrupt is generated when AF flag is set to 1 (Initial value) Rev. 6.0, 07/02, page 280 of 986 Bit 0--Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. Bit 0: AF 0 Description Alarm registers and counter values do not match [Clearing condition] When 0 is written to AF 1 Alarm registers and counter values match* [Setting condition] When alarm registers in which the ENB bit is set to 1 and counter values match* Note: * Writing 1 does not change the value. (Initial value) Bits 6, 5, 2, and 1--Reserved. The initial value of these bits is undefined. A write to these bits is invalid, but the write value should always be 0. 11.2.16 RTC Control Register 2 (RCR2) RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second adjustment, and frequency divider RESET and RTC count control. RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value. Bit: 7 PEF Initial value: Undefined R/W: R/W 6 PES2 0 R/W 5 PES1 0 R/W 4 PES0 0 R/W 3 RTCEN 1 R/W 2 ADJ 0 R/W 1 RESET 0 R/W 0 START 1 R/W Rev. 6.0, 07/02, page 281 of 986 Bit 7--Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2-PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF 0 Description Interrupt is not generated at interval specified by bits PES2-PES0 [Clearing condition] When 0 is written to PEF 1 Interrupt is generated at interval specified by bits PES2-PES0 [Setting conditions] * * Generation of interrupt at interval specified by bits PES2-PES0 When 1 is written to PEF Bits 6 to 4--Periodic Interrupt Enable (PES2-PES0): These bits specify the period for periodic interrupts. Bit 6: PES2 0 Bit 5: PES1 0 Bit 4: PES0 0 1 1 0 1 1 0 0 1 1 0 1 Description No periodic interrupt generation (Initial value) Periodic interrupt generated at 1/256-second intervals Periodic interrupt generated at 1/64-second intervals Periodic interrupt generated at 1/16-second intervals Periodic interrupt generated at 1/4-second intervals Periodic interrupt generated at 1/2-second intervals Periodic interrupt generated at 1-second intervals Periodic interrupt generated at 2-second intervals Bit 3--Oscillator Enable (RTCEN): Controls the operation of the RTC's crystal oscillator. Bit 3: RTCEN 0 1 Description RTC crystal oscillator is halted RTC crystal oscillator is operated (Initial value) Rev. 6.0, 07/02, page 282 of 986 Bit 2--30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also reset at this time. This bit always returns 0 if read. Bit 2: ADJ 0 1 Description Normal clock operation 30-second adjustment performed (Initial value) Bit 1--Reset (RESET): The frequency divider circuits are initialized by writing 1 to this bit. When 1 is written to the RESET bit, the frequency divider circuits (RTC prescaler and R64CNT) are reset and the RESET bit is automatically cleared to 0 (i.e. does not need to be written with 0). Bit 1: RESET 0 1 Description Normal clock operation Frequency divider circuits are reset (Initial value) Bit 0--Start Bit (START): Stops and restarts counter (clock) operation. Bit 0: START 0 1 Description Second, minute, hour, day, day-of-week, month, and year counters are stopped* Second, minute, hour, day, day-of-week, month, and year counters operate normally* (Initial value) Note: * The 64 Hz counter continues to operate unless stopped by means of the RTCEN bit. 11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR) (SH7750R Only) RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC's BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT value is compared with the RYRAR value. Comparison between the counter and the alarm register only takes place with the alarm registers in which the ENB and YENB bits are set to 1. The alarm flag of RCR1 is only set to 1 when the respective values all match. The setting range of RYRAR is decimal 0000 to 9999, and normal operation is not obtained if a value beyond this range is set here. RCR3 is initialized by a power-on reset, but RYRAR will not be initialized by a power-on or manual reset, or by the device entering standby mode. Rev. 6.0, 07/02, page 283 of 986 Bits 6 to 0 of RCR3 are always read as 0. Writing to these bits is invalid. If a value is written to these bits, it should always be 0. RCR3 Bit: 7 YENB Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R RYRAR Bit: 15 14 13 12 11 10 9 8 1000 years R/W: Bit: R/W 7 R/W 6 10 years R/W 5 R/W 4 R/W 3 100 years R/W 2 1 year R/W 1 R/W 0 Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W Rev. 6.0, 07/02, page 284 of 986 11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Stop clock Reset frequency divider Set RCR2.RESET to 1 Clear RCR2.START to 0 Set second/minute/hour/day/ day-of-week/month/year In any order Start clock operation Set RCR2.START to 1 (a) Setting time after stopping clock Clear carry flag Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Set RYRCNT first and RSECCNT last Write to counter register Yes Carry flag = 1? No Read RCR1 register and check CF bit (b) Setting time while clock is running Figure 11.2 Examples of Time Setting Procedures The procedure for setting the time after stopping the clock is shown in (a). The programming for this method is simple, and it is useful for setting all the counters, from second to year. Rev. 6.0, 07/02, page 285 of 986 The procedure for setting the time while the clock is running is shown in (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data. The carry flag should therefore be used to check the write status. If the carry flag (RCR1.CF) is set to 1, the write must be repeated. The interrupt function can also be used to determine the carry flag status. 11.3.2 Time Reading Procedures Figure 11.3 shows examples of the time reading procedures. Rev. 6.0, 07/02, page 286 of 986 Disable carry interrupts Clear RCR1.CIE to 0 Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Clear carry flag Read counter register Yes Carry flag = 1? No Read RCR1 register and check CF bit (a) Reading time without using interrupts Clear carry flag Enable carry interrupts Set RCR1.CIE to 1 Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Clear carry flag Read counter register Yes Interrupt generated? No Disable carry interrupts Clear RCR1.CIE to 0 (b) Reading time using interrupts Figure 11.3 Examples of Time Reading Procedures If a carry occurs while the time is being read, the correct time will not be obtained and the read must be repeated. The procedure for reading the time without using interrupts is shown in (a), and the procedure using carry interrupts in (b). The method without using interrupts is normally used to keep the program simple. Rev. 6.0, 07/02, page 287 of 986 11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4. Clock running Disable alarm interrupts Clear RCR1.AIE to prevent erroneous interrupts Set alarm time Clear alarm flag Be sure to reset the flag as it may have been set during alarm time setting Enable alarm interrupts Set RCR1.AIE to 1 Monitor alarm time (Wait for interrupt or check alarm flag) Figure 11.4 Example of Use of Alarm Function An alarm can be generated by the second, minute, hour, day-of-week, day, month, or year (year is available only with the SH7750R) value, or a combination of these. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting. When the counter and the alarm time match, RCR1.AF is set to 1. Alarm detection can be confirmed by reading this bit, but normally an interrupt is used. If 1 has been written to RCR1.AIE, an alarm interrupt is generated in the event of alarm, enabling the alarm to be detected. The alarm flag remains set while the counter and alarm time match. If the alarm flag is cleared by writing 0 during this period, it will therefore be set again immediately afterward. This needs to be taken into consideration when writing the program. Rev. 6.0, 07/02, page 288 of 986 11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1. A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2- PES0) in RCR2 are set to a value other than 000 and the periodic interrupt flag (PEF) is set to 1. A carry interrupt request (CUI) is generated when the carry flag (CF) in RCR1 is set to 1 while the carry interrupt enable bit (CIE) is also set to 1. 11.5 11.5.1 Usage Notes Register Initialization After powering on and making the RCR1 register settings, reset the frequency divider (by setting RCR2.RESET to 1) and make initial settings for all the other registers. 11.5.2 Carry Flag and Interrupt Flag in Standby Mode When the carry flag or interrupt flag is set to 1 at the same time this LSI transits to normal mode from standby mode by a reset or interrupt, the flag may not be set to 1. After exiting standby mode, check the counters to judge the flag states if necessary. 11.5.3 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 11.3, and the RTC crystal oscillator circuit in figure 11.5. Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values) fosc 32.768 kHz Cin 10-22 pF Cout 10-22 pF Rev. 6.0, 07/02, page 289 of 986 SH7750 Series VDD-RTC Noise filter CRTC Cin RRTC 3.3 V VSS-RTC EXTAL2 Rf RD XTAL2 XTAL Cout Notes: 1. Select either the Cin or Cout side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. Built-in resistance value Rf (typ. value) = 10 M, RD (typ. value) = 400 k 3. Cin and Cout values include floating capacitance due to the wiring. Take care when using a solidearth board. 4. The crystal oscillation stabilization time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) 6. Ensure that the crystal resonator connection pin (EXTAL2 and XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines. 7. Insert a noise filter in the RTC power supply. Figure 11.5 Example of Crystal Oscillator Circuit Connection Rev. 6.0, 07/02, page 290 of 986 Section 12 Timer Unit (TMU) 12.1 Overview The SH7750 Series of microprocessors include an on-chip 32-bit timer unit (TMU). The TMU of the SH7750 or SH7750S has three 32-bit timer channels (channels 0 to 2), and the TMU of the SH7750R has five channels (channels 0 to 4). 12.1.1 Features The TMU has the following features. * Auto-reload type 32-bit down-counter provided for each channel * Input capture function provided in channel 2 * Selection of rising edge or falling edge as external clock input edge when external clock is selected or input capture function is used * 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit down-counter provided for each channel * For channels 0 to 2, selection of seven counter input clocks for each channel External clock (TCLK), on-chip RTC output clock, five internal clocks (P/4, P/16, P/64, P/256, P/1024) (P is the peripheral module clock) * For channels 3 and 4, selection is made among five internal clocks (SH7750R only). * Channels 0 to 2 can also operate in module standby mode when the on-chip RTC output clock is selected as the counter input clock; that is, timer operation continues even when the clock has been stopped for the TMU. Timer count operations using an external or internal clock are only possible when a clock is supplied to the timer unit. * Two interrupt sources One underflow source (each channel) and one input capture source (channel 2) * DMAC data transfer request capability On channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is generated. Rev. 6.0, 07/02, page 291 of 986 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. PCLK/4,16, 64*1 TUNI3, 4*2 RESET, STBY, TUNE0,TUNE1 etc. TUNI2 ICPI2 TCLK RTCCLK TMU control unit Prescaler To each To channels channel 0 to 2 TCLK control unit TOCR TSTR TSTR2*2 Ch 0, 1 Interrupt contrun unit Ch 2 Interrupt contrun unit Ch 3, 4*2 Interrupt contrun unit Counter unit Counter unit Counter unit TCR TCOR TCNT TCR2 TCOR2 TCNT2 TCPR2 TCR TCOR TCNT Bus interface Internal peripheral module bus Notes: *1 Signals with 1/4, 1/16, and 1/64 the P frequency, supplied to the on-chip peripheral functions. *2 SH7750R only Figure 12.1 Block Diagram of TMU 12.1.3 Pin Configuration Table 12.1 shows the TMU pins. Table 12.1 TMU Pins Pin Name Clock input/clock output Abbreviation TCLK I/O I/O Function External clock input pin/input capture control input pin/RTC output pin (shared with RTC) Rev. 6.0, 07/02, page 292 of 986 12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization Channel Name Com- Timer mon output control register Timer start register Abbreviation TOCR PowerStandOn Manual by Area 7 R/W Reset Reset Mode Initial Value P4 Address Address R/W IniIniHeld tialized tialized H'00 Access Size H'FFD80000 H'1FD80000 8 TSTR R/W IniIniIniH'00 1 tialized tialized tialized* Held H'00 H'FFD80004 H'1FD80004 8 3 Timer TSTR2* R/W IniHeld start tialized register 2 H'FE100004 H'1E100004 8 0 Timer TCOR0 R/W IniIniHeld constant tialized tialized register 0 Timer TCNT0 counter 0 Timer TCR0 control register 0 2 R/W IniIniHeld* tialized tialized H'FFFFFFFF H'FFD80008 H'1FD80008 32 H'FFFFFFFF H'FFD8000C H'1FD8000C 32 H'0000 H'FFD80010 H'1FD80010 16 R/W IniIniHeld tialized tialized 1 Timer TCOR1 R/W IniIniHeld constant tialized tialized register 1 Timer TCNT1 counter 1 Timer TCR1 control register 1 2 R/W IniIniHeld* tialized tialized H'FFFFFFFF H'FFD80014 H'1FD80014 32 H'FFFFFFFF H'FFD80018 H'1FD80018 32 H'0000 H'FFD8001C H'1FD8001C 16 R/W IniIniHeld tialized tialized 2 Timer TCOR2 R/W IniIniHeld constant tialized tialized register 2 Timer TCNT2 counter 2 Timer TCR2 control register 2 Input capture register 2 R/W IniIniHeld* tialized tialized H'FFFFFFFF H'FFD80020 H'1FD80020 32 H'FFFFFFFF H'FFD80024 H'1FD80024 32 H'0000 H'FFD80028 H'1FD80028 16 R/W IniIniHeld tialized tialized Held Held Held TCPR2 R Undefined H'FFD8002C H'1FD8002C 32 Rev. 6.0, 07/02, page 293 of 986 Initialization Channel Name 3 3* Abbreviation PowerStandOn Manual by Area 7 R/W Reset Reset Mode Initial Value P4 Address Address Held Access Size Held Timer TCOR3 R/W Initialized constant register 3 Timer TCNT3 counter 3 Timer TCR3 control register 3 Held R/W Initialized Held R/W Initialized H'FFFFFFFF H'FE100008 H'1E100008 32 Held Held H'FFFFFFFF H'FE10000C H'1E10000C 32 H'0000 H'FE100010 H'1E100010 16 3 4* Held Timer TCOR4 R/W Initialized constant register 4 Timer TCNT4 counter 4 Timer TCR4 control register 4 Held R/W Initialized Held R/W Initialized Held H'FFFFFFFF H'FE100014 H'1E100014 32 Held Held H'FFFFFFFF H'FE100018 H'1E100018 32 H'0000 H'FE10001C H'1E10001C 16 Notes: *1 Not initialized in module standby mode when the input clock is the on-chip RTC output clock. *2 Counts in module standby mode when the input clock is the on-chip RTC output clock. *3 SH7750R only Rev. 6.0, 07/02, page 294 of 986 12.2 12.2.1 Register Descriptions Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin. TOCR is initialized to H'00 by a power-on or manual reset, but is not initialized in standby mode. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 TCOE 0 R/W Bits 7 to 1--Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 0--Timer Clock Pin Control (TCOE): Specifies whether timer clock pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin. Bit 0: TCOE 0 1 Description Timer clock pin (TCLK) is used as external clock input or input capture control input pin (Initial value) Timer clock pin (TCLK) is used as on-chip RTC output clock output pin* Note: * Low level output in standby mode. Rev. 6.0, 07/02, page 295 of 986 12.2.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that specifies whether the channel 0-2 timer counters (TCNT) are operated or stopped. TSTR is initialized to H'00 by a power-on or manual reset, or standby mode. In module standby mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal clock (P). Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Bits 7 to 3--Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 2--Counter Start 2 (STR2): Specifies whether timer counter 2 (TCNT2) is operated or stopped. Bit 2: STR2 0 1 Description TCNT2 count operation is stopped TCNT2 performs count operation (Initial value) Bit 1--Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or stopped. Bit 1: STR1 0 1 Description TCNT1 count operation is stopped TCNT1 performs count operation (Initial value) Bit 0--Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or stopped. Bit 0: STR0 0 1 Description TCNT0 count operation is stopped TCNT0 performs count operation (Initial value) Rev. 6.0, 07/02, page 296 of 986 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) TSTR2 is an 8-bit readable/writable register that specifies whether the channels 3-4 timer counters (TSTR2) run or are stopped. TSTR2 is initialized to H'00 by a power-on reset and retains its value in standby mode. If standby mode is entered when the STR3 or STR4 bit is set to 1, counting is halted at the same time as the peripheral module clock is stopped. Counting is restarted on resumption of the clock-signal supply. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 STR4 0 R/W 0 STR3 0 R/W Bits 7 to 2--Reserved: These bits are always read as 0. Writing to these bits is invalid. If a value is written to these bits, it should always be 0. Bit 1--Counter Start 4 (STR4): Specifies whether timer counter 4 (TCNT4) runs or is stopped. Bit 1: STR4 0 1 Description Counting by TCNT4 is stopped Counting by TCNT4 proceeds (Initial value) Bit 0--Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) runs or is stopped. Bit 0: STR3 0 1 Description Counting by TCNT3 is stopped Counting by TCNT3 proceeds (Initial value) Rev. 6.0, 07/02, page 297 of 986 12.2.4 Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers. There are TCOR registers, one for each channel. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value. The TCOR registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode. The TCOR registers for channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode. Bit: 31 30 29 ************* Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 2 1 0 12.2.5 Timer Counters (TCNT) The TCNT registers are 32-bit readable/writable registers. There are TCNT registers, one for each channel. Each TCNT counts down on the input clock selected by TPSC2-TPSC0 in the timer control register (TCR). When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the corresponding timer control register (TCR). At the same time, the timer constant register (TCOR) value is set in TCNT, and the count-down operation continues from the set value. The TCNT registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode. The TCNT registers for channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode. Bit: 31 30 29 ************* Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 2 1 0 When the input clock is the on-chip RTC output clock (RTCCLK) in channels 0 to 2, TCNT counts even in module standby mode (that is, when the clock for the TMU is stopped). When the Rev. 6.0, 07/02, page 298 of 986 input clock is the external clock (TCLK) or internal clock (P), TCNT contents are retained in standby mode. 12.2.6 Timer Control Registers (TCR) The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for each channel. Each TCR selects the count clock, specifies the edge when an external clock is selected in channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT) underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of interrupt generation in the event of input capture. The TCR registers for channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but are not initialized and retain their contents in standby mode. The TCR registers for channels 3 and 4 of the SH7750R are initialized to H'0000 by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode. 1. Channel 0 and 1 TCR bit configuration Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 UNIE 0 R/W 12 -- 0 R 4 CKEG1 0 R/W 11 -- 0 R 3 CKEG0 0 R/W 10 -- 0 R 2 TPSC2 0 R/W 9 -- 0 R 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W Rev. 6.0, 07/02, page 299 of 986 2. Channel 2 TCR bit configuration Bit: 15 -- Initial value: R/W: Bit: 0 R 7 ICPE1 Initial value: R/W: 0 R/W 14 -- 0 R 6 ICPE0 0 R/W 13 -- 0 R 5 UNIE 0 R/W 12 -- 0 R 4 CKEG1 0 R/W 11 -- 0 R 3 CKEG0 0 R/W 10 -- 0 R 2 TPSC2 0 R/W 9 ICPF 0 R/W 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W 3. TCR bit configuration for channels 3 and 4 (SH7750R only) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 UNIE 0 R/W 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 TPSC2 0 R/W 9 -- 0 R 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)--Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 9--Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in channel 2 only, that indicates the occurrence of input capture. Bit 9: ICPF 0 Description Input capture has not occurred [Clearing condition] When 0 is written to ICPF 1 Input capture has occurred [Setting condition] When input capture occurs* Note: * Writing 1 does not change the value. (Initial value) Rev. 6.0, 07/02, page 300 of 986 Bit 8--Underflow Flag (UNF): Status flag that indicates the occurrence of underflow. Bit 8: UNF 0 Description TCNT has not underflowed [Clearing condition] When 0 is written to UNF 1 TCNT has underflowed [Setting condition] When TCNT underflows* Note: * Writing 1 does not change the value. (Initial value) Bits 7 and 6--Input Capture Control (ICPE1, ICPE0) (Channel 2 Only): These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. When the input capture function is used, a data transfer request is sent to the DMAC in the event of input capture. When using the input capture function, the TCLK pin must be designated as an input pin with the TCOE bit in the TOCR register. The CKEG bits specify whether the rising edge or falling edge of the TCLK signal is used to set the TCNT2 value in the input capture register (TCPR2). The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is 1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC transfer request is not generated until processing of the previous request is finished. Bit 7: ICPE1 0 Bit 6: ICPE0 0 1 1 0 Description Input capture function is not used Reserved (Do not set) Input capture function is used, but interrupt due to input capture (TICPI2) is not enabled Data transfer request is sent to DMAC in the event of input capture 1 Input capture function is used, and interrupt due to input capture (TICPI2) is enabled Data transfer request is sent to DMAC in the event of input capture (Initial value) Rev. 6.0, 07/02, page 301 of 986 Bit 5--Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow. Bit 5: UNIE 0 1 Description Interrupt due to underflow (TUNI) is not enabled Interrupt due to underflow (TUNI) is enabled (Initial value) Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the external clock input edge when an external clock is selected or the input capture function is used in channels 0 to 2. Bit 4: CKEG1 0 Bit 3: CKEG0 0 1 1 X Note: X: 0 or 1 (don't care) Description Count/input capture register set on rising edge Count/input capture register set on falling edge Count/input capture register set on both rising and falling edges (Initial value) Bits 2 to 0--Timer Prescaler 2 to 0 (TPSC2-TPSC0): These bits select the TCNT count clock. With channels 0 to 2, when the on-chip RTC output clock is selected as the count clock for a channel, that channel can operate even in module standby mode. When another clock is selected, the channel does not operate in standby mode. Bit 2: TPSC2 0 Bit 1: TPSC1 0 Bit 0: TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Counts on P/4 Counts on P/16 Counts on P/64 Counts on P/256 Counts on P/1024 Reserved (Do not set) Counts on on-chip RTC output clock (Do not set this pattern for channel 3 or 4) Counts on external clock (Do not set this pattern for channel 3 or 4) (Initial value) Rev. 6.0, 07/02, page 302 of 986 12.2.7 Input Capture Register (TCPR2) TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. The input capture function is controlled by means of the input capture control bits (ICPE) and clock edge bits (CKEG) in TCR2. When input capture occurs, the TCNT2 value is copied into TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0. TCPR2 is not initialized by a power-on or manual reset, or in standby mode. Bit: 31 30 29 ************* Initial value: R/W: R R R Undefined R R R 2 1 0 Rev. 6.0, 07/02, page 303 of 986 12.3 Operation Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function. 12.3.1 Counter Operation When one of bits STR0-STR4 is set to 1 in the timer start register (TSTR, TSTR2), the timer counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF flag is set in the corresponding timer control register (TCR). If the UNIE bit in TCR is set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied from TCOR into TCNT, and the count-down continues (auto-reload function). Example of Count Operation Setting Procedure: Figure 12.2 shows an example of the count operation setting procedure. 1. Select the count clock, for channel 0, 1, or 2, with bits TPSC2-TPSC0 in the timer control register (TCR). When an external clock is selected, set the TCLK pin to input mode with the TCOE bit in TOCR, and select the external clock edge with bits CKEG1 and CKEG0 in TCR. 2. Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR. 3. When the input capture function is used, set the ICPE bits in TCR, including specification of whether the interrupt function is to be used. 4. Set a value in the timer constant register (TCOR). 5. Set the initial value in the timer counter (TCNT). 6. Set the STR bit to 1 in the timer start register (TSTR, TSTR2) to start the count. Rev. 6.0, 07/02, page 304 of 986 Operation selection Select count clock 1 Underflow interrupt generation setting 2 When input capture function is used Input capture interrupt generation setting 3 Timer constant register setting Set initial timer counter value 4 5 Start count 6 Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated. Figure 12.2 Example of Count Operation Setting Procedure Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCNT value TCOR TCOR value set in TCNT on underflow H'00000000 STR0-STR2 Time UNF Figure 12.3 TCNT Auto-Reload Operation Rev. 6.0, 07/02, page 305 of 986 TCNT Count Timing: * Operating on internal clock Any of five count clocks (P/4, P/16, P/64, P/256, or P/1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2-TPSC0 bits in TCR. Figure 12.4 shows the timing in this case. P Internal clock TCNT N+1 N N-1 Figure 12.4 Count Timing when Operating on Internal Clock * Operating on external clock For channels 0 to 2, external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2-TPSC0 bits in TCR. The rising edge, falling edge, or both edges can be selected as the detected edge of the external clock with the CKEG1 and CKEG0 bits in TCR. Figure 12.5 shows the timing for both-edge detection. P External clock input pin TCNT N+1 N N-1 Figure 12.5 Count Timing when Operating on External Clock Rev. 6.0, 07/02, page 306 of 986 * Operating on on-chip RTC output clock The on-chip RTC output clock can be selected as the timer clock in channels 0 to 2 by means of the TPSC2-TPSC0 bits in TCR. Figure 12.6 shows the timing in this case. RTC output clock TCNT N+1 N N-1 Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock 12.3.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use the TCOE bit in the timer output control register (TOCR) to set the TCLK pin to input mode. 2. Use bits TPSC2-TPSC0 in the timer control register (TCR) to set an internal clock or the onchip RTC output clock as the timer operating clock. 3. Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function, and whether interrupts are to generated when this function is used. 4. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK signal is to be used to set the timer counter (TCNT) value in the input capture register (TCPR2). This function cannot be used in standby mode. When input capture occurs, the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0. Also, a new DMAC transfer request is not generated until processing of the previous request is finished. Figure 12.7 shows the operation timing when the input capture function is used (with TCLK rising edge detection). Rev. 6.0, 07/02, page 307 of 986 TCNT value TCOR TCOR value set in TCNT on underflow H'00000000 TCLK Time TCPR2 TCNT value set TICPI2 Figure 12.7 Operation Timing when Using Input Capture Function 12.4 Interrupts There are four TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when the UNF bit in TCR is 1 and the interrupt enable bit for the corresponding channel is 1. When the input capture function is used and an input capture request is generated, an interrupt is requested if the input capture input flag (ICPF) in TCR2 is 1 and the input capture control bits (ICPE1, ICPE0) in TCR2 are 11. The TMU interrupt sources are summarized in table 12.3. Rev. 6.0, 07/02, page 308 of 986 Table 12.3 TMU Interrupt Sources Channel 0 1 2 Interrupt Source TUNI0 TUNI1 TUNI2 TICPI2 3* 4* TUNI3 TUNI4 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Input capture interrupt 2 Underflow interrupt 3 Underflow interrupt 4 Low Priority High Note: * SH7750R only 12.5 12.5.1 Usage Notes Register Writes When performing a register write, timer count operation must be stopped by clearing the start bit (STR0-STR4) for the relevant channel in the timer start register (TSTR, TSTR2). Note that the timer start register (TSTR, TSTR2) can be written to, and the underflow flag (UNF) and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared while the count is in progress. When the flags (UNF, ICPF) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared. 12.5.2 TCNT Register Reads When performing a TCNT register read, processing for synchronization with the timer count operation is performed. If a timer count operation and register read processing are performed simultaneously, the TCNT counter value prior to the count-down operation is read by means of the synchronization processing. 12.5.3 Resetting the RTC Frequency Divider When the on-chip RTC output clock is selected as the count clock, the RTC frequency divider should be reset. 12.5.4 External Clock Frequency Ensure that the external clock frequency for any channel does not exceed P/4. Rev. 6.0, 07/02, page 309 of 986 Rev. 6.0, 07/02, page 310 of 986 Section 13 Bus State Controller (BSC) 13.1 Overview The functions of the bus state controller (BSC) include division of the external memory space, and output of control signals in accordance with various types of memory and bus interface specifications. The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be connected to the SH7750 Series, and also support the PCMCIA interface protocol, enabling system design to be simplified and data transfers to be carried out at high speed by a compact system. 13.1.1 Features The BSC has the following features: * External memory space is managed as 7 independent areas Maximum 64 Mbytes for each of areas 0 to 6 Bus width of each area can be set in a register (except area 0, which uses an external pin setting) Wait state insertion by 5'< pin Wait state insertion can be controlled by program Specification of types of memory connectable to each area Output the control signals of memory to each area Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different areas, or a read access followed by a write access to the same area Write strobe setup time and hold time periods can be inserted in a write cycle to enable connection to low-speed memory * SRAM interface Wait state insertion can be controlled by program Wait state insertion by 5'< pin Connectable areas: 0 to 6 Settable bus widths: 64, 32, 16, 8 * DRAM interface Row address/column address multiplexing according to DRAM capacity Burst operation (fast page mode, EDO mode) CAS-before-RAS refresh and self-refresh 8-CAS byte control for power-down operation DRAM control signal timing can be controlled by register settings Rev. 6.0, 07/02, page 311 of 986 Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 64, 32, 16 * Synchronous DRAM interface Row address/column address multiplexing according to synchronous DRAM capacity Burst operation Auto-refresh and self-refresh Synchronous DRAM control signal timing can be controlled by register settings Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 64, 32 * Burst ROM interface Wait state insertion can be controlled by program Burst operation, executing the number of transfers set in a register Connectable areas: 0, 5, 6 Settable bus widths: 64*, 32, 16, 8 * MPX interface Address/data multiplexing Connectable areas: 0 to 6 Settable bus widths: 64, 32 * Byte control SRAM interface SRAM interface with byte control Connectable areas: 1, 4 Settable bus widths: 64, 32, 16 * PCMCIA interface Wait state insertion can be controlled by program Bus sizing function for I/O bus width * Fine refreshing control Supports refresh operation immediately after self-refresh operation in low-power DRAM by means of refresh counter overflow interrupt function * Refresh counter can be used as interval timer Interrupt request generated by compare-match Interrupt request generated by refresh counter overflow Note: * SH7750R only Rev. 6.0, 07/02, page 312 of 986 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the BSC. Bus interface WCR1 Wait control unit WCR2 WCR3 - - Area control unit BCR1 BCR2 BCR3* RD/ - , CKE , Memory control unit BCR4* MCR PCR RFCR Peripheral bus RTCNT Refresh control unit Comparator Interrupt controller RTCOR RTCSR BSC WCR: BCR: MCR: PCR: Wait control register Bus control register Memory control register PCMCIA control register RFCR: RTCNT: RTCOR: RTCSR: Refresh count register Refresh timer count register Refresh time constant register Refresh timer control/status register Note: * SH7750R only Figure 13.1 Block Diagram of BSC Rev. 6.0, 07/02, page 313 of 986 Module bus Internal bus 13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Address bus Data bus Signals A25-A0 D63-D52, D31-D0 I/O O I/O Description Address output Data input/output When port functions are used and DDT mode is selected, input the DTR format. Otherwise, when port functions are used, D60-D52 cannot be used and should be left open. I/O When port functions are not used: data input/output When port functions are used: input/output port (input or output set for each bit by register) O Signal that indicates the start of a bus cycle When setting synchronous DRAM interface: asserted once for a burst transfer For other burst transfers: asserted each data cycle Chip select 6-0 &69-&63 O Chip select signals that indicate the area being accessed &68 and &69 are also used as PCMCIA &(4$ and &(4% Read/write RD/:5 O Data bus input/output direction designation signal Also used as the DRAM/synchronous DRAM/PCMCIA interface write designation signal Row address strobe Read/column address strobe/ cycle frame 5$6 5'/&$66/ )5$0( O O 5$6 signal when setting DRAM/synchronous DRAM interface Strobe signal that indicates a read cycle When setting synchronous DRAM interface: &$6 signal When setting MPX interface: )5$0( signal Data enable 0 :(3/&$63/ DQM0 O When setting synchronous DRAM interface: selection signal for D7-D0 When setting DRAM interface: &$6 signal for D7-D0 When setting MPX interface: high-level output In other cases: write strobe signal for D7-D0 Data bus/port D51-D32/ PORT19- PORT0 %6 Bus cycle start Rev. 6.0, 07/02, page 314 of 986 Table 13.1 BSC Pins (cont) Name Data enable 1 Signals :(4/&$64/ DQM1 I/O O Description When setting synchronous DRAM interface: selection signal for D15-D8 When setting DRAM interface: &$6 signal for D15-D8 When setting PCMCIA interface: write strobe signal When setting MPX interface: high-level output In other cases: write strobe signal for D15-D8 Data enable 2 :(5/&$65/ DQM2/,&,25' O When setting synchronous DRAM interface: selection signal for D23-D16 When setting DRAM interface: &$6 signal for D23-D16 When setting PCMCIA interface: ,&,25' signal When setting MPX interface: high-level output In other cases: write strobe signal for D23-D16 Data enable 3 :(6/&$66/ O DQM3/,&,2:5 When setting synchronous DRAM interface: selection signal for D31-D24 When setting DRAM interface: &$6 signal for D31-D24 When setting PCMCIA interface: ,&,2:5 signal When setting MPX interface: high-level output In other cases: write strobe signal for D31-D24 Data enable 4 :(7/&$67/ DQM4 O When setting synchronous DRAM interface: selection signal for D39-D32 When setting DRAM interface: &$6 signal for D39-D32 When setting MPX interface: high-level output In other cases: write strobe signal for D39-D32 Data enable 5 :(8/&$68/ DQM5 O When setting synchronous DRAM interface: selection signal for D47-D40 When setting DRAM interface: &$6 signal for D47-D40 When setting MPX interface: high-level output In other cases: write strobe signal for D47-D40 Rev. 6.0, 07/02, page 315 of 986 Table 13.1 BSC Pins (cont) Name Data enable 6 Signals :(9/&$69/ DQM6 I/O O Description When setting synchronous DRAM interface: selection signal for D55-D48 When setting DRAM interface: &$6 signal for D55-D48 When setting MPX interface: high-level output In other cases: write strobe signal for D55-D48 Data enable 7 :(:/&$6:/ DQM7/5(* O When setting synchronous DRAM interface: selection signal for D63-D56 When setting DRAM interface: &$6 signal for D63-D56 When setting PCMCIA interface: 5(* signal When setting MPX interface: high-level output In other cases: write strobe signal for D63-D56 Ready Area 0 MPX interface specification/ 16-bit I/O Clock enable Bus release request Bus use permission Area 0 bus width/PCMCIA card select 5'< MD6/,2,649 I I Wait state request signal In power-on reset: Designates area 0 bus as MPX interface (1: SRAM, 0: MPX) When setting PCMCIA interface: 16-bit I/O designation signal. Valid only in little-endian mode. CKE %5(4/ %6$&. %$&./ %65(4 1 MD3/&(5$* 2 MD4/&(5%* O I O I/O Synchronous DRAM clock enable control signal Bus release request signal/bus acknowledge signal Bus use permission signal/bus request In power-on reset* : external space area 0 bus width specification signal When setting PCMCIA interface: &(5$, &(5% Endian specification in a power-on reset.* 4 4 3 Endian switchover/ MD5/5$65* row address strobe I/O I/O 5$65 when DRAM is connected to area 2 Indicates master/slave status in a power-on reset.* Serial interface TXD 4 Master/slave switchover DMAC0 acknowledge signal DMAC1 acknowledge signal MD7/TXD DACK0 O DMAC channel 0 data acknowledge DACK1 O DMAC channel 1 data acknowledge Rev. 6.0, 07/02, page 316 of 986 Table 13.1 BSC Pins (cont) Name Read/column address strobe/ cycle frame 2 Read/write 2 Signals 5'5 I/O O Description Same signal as 5'/&$66/)5$0( This signal is used when the 5'/&$66/)5$0( signal load is heavy. RD/:55 O Same signal as RD/:5 This signal is used when the RD/:5 signal load is heavy. Notes: *1 MD3/&(5$ input/output switching is performed by BCR1.A56PCM. Output is selected when BCR1.A56PCM = 1. *2 MD4/&(5% input/output switching is performed by BCR1.A56PCM. Output is selected when BCR1.A56PCM = 1. *3 MD5/5$65 input/output switching is performed by BCR1.DRAMTP. Output is selected when BCR1.DRAMTP (2-0) = 101. *4 In a power-on reset by means of the 5(6(7 pin. Rev. 6.0, 07/02, page 317 of 986 13.1.4 Register Configuration The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode register incorporated in synchronous DRAM can also be accessed as an SH7750 Series register. The functions of these registers include control of interfaces to various types of memory, wait states, and refreshing. Table 13.2 BSC Registers Name Bus control register 1 Bus control register 2 Bus control register 3* Bus control register 4* Wait state control register 1 Wait state control register 2 Wait state control register 3 2 2 Abbrevia- R/W tion BCR1 BCR2 BCR3 BCR4 WCR1 WCR2 WCR3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Initial Value P4 Address Area 7 Address Access Size H'0000 0000 H'FF80 0000 H'1F80 0000 32 H'3FFC H'0000 H'FF80 0004 H'1F80 0004 16 H'FF80 0050 H'1F80 0050 16 H'0000 0000 H'FE0A 00F0 H'1E0A 00F0 32 H'7777 7777 H'FF80 0008 H'1F80 0008 32 H'FFFE EFFF H'FF80 000C H'1F80 000C 32 H'0777 7777 H'FF80 0010 H'1F80 0010 32 H'0000 0000 H'FF80 0014 H'1F80 0014 32 H'0000 H'0000 H'0000 H'0000 H'0000 -- H'FF80 0018 H'1F80 0018 16 H'FF80 001C H'1F80 001C 16 H'FF80 0020 H'1F80 0020 16 H'FF80 0024 H'1F80 0024 16 H'FF80 0028 H'1F80 0028 16 H'FF90 xxxx* H'1F90 xxxx H'FF94 xxxx* H'1F94 xxxx 1 1 Memory control register MCR PCMCIA control register PCR Refresh timer control/status register Refresh timer counter Refresh time constant counter Refresh count register Synchronous DRAM mode registers For area 2 For area 3 RTCSR RTCNT RTCOR RFCR SDMR2 SDMR3 8 Notes: *1 For details, see section 13.2.10, Synchronous DRAM Mode Registers (SDMR). *2 Settable only for SH7750R. Rev. 6.0, 07/02, page 318 of 986 13.1.5 Overview of Areas Space Divisions: The architecture of the SH7750 Series provides a 32-bit virtual address space. The virtual address is divided into five areas according to the upper address value. External memory space comprises a 29-bit address space, divided into eight areas. The virtual address can be allocated to any external address by means of the memory management unit (MMU). Details are given in section 3, Memory Management Unit (MMU). This section describes the areas into which the external address is divided. With the SH7750 Series, various kinds of memory or PC cards can be connected to the seven areas of external address as shown in table 13.3, and chip select signals (&63-&69, &(5$, &(5%) are output for each of these areas. &63 is asserted when accessing area 0, and &69 when accessing area 6. When DRAM or synchronous DRAM is connected to area 2 or 3, signals such as 5$6, &$6, RD/:5, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or 6, &(5$, &(5% is asserted in addition to &68, &69 for the byte to be accessed. 256 H'0000 0000 Area 0 ( Area 1 ( P0 and U0 areas P0 and U0 areas Area 2 ( Area 3 ( Area 4 ( H'8000 0000 P1 area H'A000 0000 H'C000 0000 P2 area P3 area P1 area P2 area P3 area Store queue area P4 area Area 5 ( Area 6 ( ) ) ) ) ) ) ) H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF Area 7 (reserved area) H'E000 0000 Store queue area H'E400 0000 P4 area H'FFFF FFFF Physical address space (MMU off) Virtual address space (MMU on) External memory space Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and memory is mapped onto a fixed 29-bit external address. 2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be mapped onto any external address using the TLB. For details, see section 3, Memory Management Unit (MMU). Figure 13.2 Correspondence between Virtual Address Space and External Memory Space Rev. 6.0, 07/02, page 319 of 986 Table 13.3 External Memory Space Map Area 0 External Addresses H'00000000- H'03FFFFFF Size 64 Mbytes Connectable Memory SRAM Burst ROM MPX 1 H'04000000- H'07FFFFFF 64 Mbytes SRAM MPX Byte control SRAM 2 H'08000000- H'0BFFFFFF 64 Mbytes SRAM Settable Bus Widths 1 8, 16, 32, 64* 8, 16, 32* , 64* 1 32, 64* 8, 16, 32, 64* 2 32, 64* 2 16, 32, 64* 2 2 1 7 Access Size 8,16,32, 6 64* bits, 32 bytes 8,16,32, 6 64* bits, 32 bytes 8,16,32, 6 64* bits, 32 bytes 8, 16, 32, 64* 23 Synchronous DRAM 32, 64* * 23 DRAM 16, 32* * MPX 32, 64* 2 3 H'0C000000- H'0FFFFFFF 64 Mbytes 8, 16, 32, 64* 23 Synchronous DRAM 32, 64* * 23 DRAM 16, 32, 64* * SRAM MPX 32, 64* 2 2 8,16,32, 6 64* bits, 32 bytes 4 H'10000000- H'13FFFFFF 64 Mbytes SRAM MPX Byte control RAM 8, 16, 32, 64* 2 32, 64* 16, 32, 64* 2 2 8,16,32, 6 64* bits, 32 bytes 8,16,32, 6 64* bits, 32 bytes 5 H'14000000- H'17FFFFFF 64 Mbytes SRAM MPX Burst ROM PCMCIA 8, 16, 32, 64* 2 32, 64* 2 2 8, 16, 32* , 64* 24 8, 16* * 8, 16, 32, 64* 2 32, 64* 2 7 6 H'18000000- H'1BFFFFFF 64 Mbytes SRAM MPX Burst ROM PCMCIA 2 7 8,16, 32* , 64* 24 8,16* * 8,16,32, 6 64* bits, 32 bytes 7* 5 H'1C000000- H'1FFFFFFF 64 Mbytes -- -- Notes: *1 Memory bus width specified by external pins *2 Memory bus width specified by register *3 With synchronous DRAM interface, bus width is 32 or 64 bits only. With DRAM interface, bus width is 16 or 32 bits only for area 2, and 16, 32, or 64 bits only for area 3. Bus width of area 2 is as same as that of area 3 which is specified by MCR. *4 With PCMCIA interface, bus width is 8 or 16 bits only. *5 Do not access a reserved area, as operation cannot be guaranteed in this case. *6 64-bit access applies only to transfer by the DMAC. (CHCRn. TS = 000) In a transfer to an external memory by FMOV (FPSCR.SZ = 1), two transfer operations, each with an access size of 32 bits, are conducted. *7 Settable only for SH7750R. Rev. 6.0, 07/02, page 320 of 986 Area 0: H'00000000 Area 1: H'04000000 Area 2: H'08000000 Area 3: H'0C000000 Area 4: H'10000000 Area 5: H'14000000 Area 6: H'18000000 SRAM/burst ROM/MPX SRAM/MPX/byte control SRAM SRAM/synchronous DRAM/DRAM/ MPX SRAM/synchronous DRAM/DRAM/ MPX SRAM/MPX/byte control SRAM SRAM/burst ROM/PCMCIA/MPX SRAM/burst ROM/PCMCIA/MPX The PCMCIA interface is for memory and I/O card use Figure 13.3 External Memory Space Allocation Memory Bus Width: In the SH7750 Series, the memory bus width can be set independently for each space. For area 0, a bus size of 8, 16, 32, or 64 bits can be selected in a power-on reset by the 5(6(7 pin, using external pins. The relationship between the external pins (MD4 and MD3) and the bus width in a power-on reset is shown below. MD4 0 MD3 0 1 1 0 1 Bus Width 64 bits 8 bits 16 bits 32 bits When SRAM interface or ROM is used in areas 1 to 6, a bus width of 8, 16, 32, or 64 bits can be selected with bus control register 2 (BCR2). When burst ROM is used, a bus width of 8, 16, 32, or 64* bits can be selected. When byte control SRAM interface is used, a bus width of 16, 32, or 64 bits can be selected. When the MPX interface is used, a bus width of 32 or 64 bits can be selected. When the DRAM interface is used, a bus width of 16, 32, or 64 bits can be selected with the memory control register (MCR). When the DRAM interface is used for area 2 or 3, a bus width of 16 or 32 bits should be set. For the synchronous DRAM interface, set a bus width of 32 or 64 bits in the MCR register. Rev. 6.0, 07/02, page 321 of 986 When using the PCMCIA interface, set a bus width of 8 or 16 bits. For details, see section 13.3.7, PCMCIA Interface. When using port functions, set a bus width of 8, 16, or 32 bits for all areas. For details, see section 13.2.2, Bus Control Register 2 (BCR2), and section 13.2.7, Memory Control Register (MCR). The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used. Note: * SH7750R only 13.1.6 PCMCIA Support The SH7750 Series supports PCMCIA compliant interface specifications for external memory space areas 5 and 6. The interfaces supported are the IC memory card interface and I/O card interface stipulated in JEIDA specifications version 4.2 (PCMCIA2.1). External memory space areas 5 and 6 support both the IC memory card interface and the I/O card interface. The PCMCIA interface is supported only in little-endian mode. Table 13.4 PCMCIA Interface Features Item Access Data bus Memory type Common memory capacity Attribute memory capacity Others Features Random access 8/16 bits Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Max. 64 Mbytes Max. 64 Mbytes Dynamic bus sizing for I/O bus width, access to PCMCIA interface from address translation areas Rev. 6.0, 07/02, page 322 of 986 Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface Signal Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND D3 D4 D5 D6 D7 &(4 A10 2( A11 A9 A8 A13 A14 :(/3*0 5'19 20 21 22 23 24 25 26 27 28 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 Rev. 6.0, 07/02, page 323 of 986 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface Signal Pin Name 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A0 D0 D1 D2 :3* GND GND &'4 D11 D12 D13 D14 D15 &(5 RFSH RFU RFU A17 A18 A19 A20 A21 VCC VPP2 I I I I I O I/O Function I Address Signal Name A0 D0 D1 D2 ,2,649 GND GND &'4 D11 D12 D13 D14 D15 &(5 RFSH ,25' ,2:5 A17 A18 A19 A20 A21 VCC VPP2 O I/O Card Interface I/O Function I Address Corresponding SH7750 Series Pin A0 D0 D1 D2 ,2,649 -- -- Sensed on port D11 D12 D13 D14 D15 &(5$ or &(5% Output from port ,&,25' ,&,2:5 A17 A18 A19 A20 A21 -- -- I/O Data I/O Data I/O Data O Write protect Ground Ground Card detection I/O Data I/O Data I/O Data O 16-bit I/O port Ground Ground Card detection I/O Data I/O Data I/O Data I/O Data I/O Data I I Card enable Refresh request Reserved Reserved Address Address Address Address Address Power supply Programming power supply I I I I Address Address Address Address I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I Card enable Refresh request I/O read I/O write Address Address Address Address Address Power supply Programming/ peripheral power supply I I I I Address Address Address Address 53 54 55 56 A22 A23 A24 A25 A22 A23 A24 A25 A22 A23 A24 A25 Rev. 6.0, 07/02, page 324 of 986 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface Signal Pin Name 57 58 59 60 61 62 63 64 65 66 67 68 RFU RESET :$,7 RFU 5(* BVD2 BVD1 D8 D9 D10 &'5 GND I O O I O I/O Function Reserved Reset Wait request Reserved Attribute memory space select Battery voltage detection Battery voltage detection Signal Name RFU RESET :$,7 ,13$&. 5(* 63.5 676&+* D8 D9 D10 &'5 GND I O O I O O I/O Card Interface I/O Function Reserved Reset Wait request Corresponding SH7750 Series Pin -- Output from port 5'< :(: Sensed on port Sensed on port D8 D9 D10 Sensed on port -- Input acknowledge -- Attribute memory space select Digital speech signal Card status change I/O Data I/O Data I/O Data O Card detection Ground I/O Data I/O Data I/O Data O Card detection Ground Note: * :3 is not supported. Rev. 6.0, 07/02, page 325 of 986 13.2 13.2.1 Register Descriptions Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. External memory space other than area 0 should not be accessed until register initialization is completed. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 ENDIAN 30 MASTER 1 29 A0MPX 1 28 -- 0 R 20 A4MBC 0 R/W 12 A0BST1 1 27 -- 0 R 19 BREQEN 26 2 DPUP* 25 IPUP 0 R/W 17 0 R/W 9 A5BST1 24 OPUP 0 R/W 16 2 0/1* R 23 -- 0 R 15 0/1* R 22 -- 0 R 14 0/1* R 21 0 R 18 PSHR 0 R/W 10 A5BST2 A1MBC 0 R/W 13 A0BST2 MEMMPX DMABST* 0 R/W 11 A0BST0 0 R 8 A5BST0 HIZMEM HIZCNT 0 R/W 7 A6BST2 0 R/W 6 A6BST1 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 -- 0 R/W 0 A56PCM A6BST0 DRAMTP2 DRAMTP1 DRAMTP0 0 R/W 0 R/W 0 R 0 R/W Notes: *1 These bits sample external pin values in a power-on reset by means of the 5(6(7 pin. *2 SH7750R only. Rev. 6.0, 07/02, page 326 of 986 Bit 31--Endian Flag (ENDIAN): Samples the value of the endian specification external pin (MD5) in a power-on reset by the 5(6(7 pin. The endian mode of all spaces is determined by this bit. ENDIAN is a read-only bit. Bit 31: ENDIAN 0 1 Description In a power-on reset, the endian setting external pin (MD5) is low, designating big-endian mode In a power-on reset, the endian setting external pin (MD5) is high, designating little-endian mode Bit 30--Master/Slave Flag (MASTER): Samples the value of the master/slave specification external pin (MD7) in a power-on reset by the 5(6(7 pin. The master/slave status of all spaces is determined by this bit. MASTER is a read-only bit. Bit 30: MASTER 0 1 Description In a power-on reset, the master/slave setting external pin (MD7) is high, designating master mode In a power-on reset, the master/slave setting external pin (MD7) is low, designating slave mode Bit 29--Area 0 Memory Type (A0MPX): Samples the value of the area 0 memory type specification external pin (MD6) in a power-on reset by the 5(6(7 pin. The memory type of area 0 is determined by this bit. A0MPX is a read-only bit. Bit 29: A0MPX 0 1 Description In a power-on reset, the external pin specifying the area 0 memory type (MD6) is high, designating the area 0 as SRAM interface In a power-on reset, the external pin specifying the area 0 memory type (MD6) is low, designating the area 0 as MPX interface Bits 28, 27, 26*, 23, 22, 16*, and 1--Reserved: These bits are always read as 0, and should only be written with 0. Note: * SH7750, SH7750S only. Rev. 6.0, 07/02, page 327 of 986 Bit 26--Data pin Pullup Resistor Control (DPUP) (SH7750R only): Controls the pullup resistance of the data pins (D63 to D0). It is initialized at a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the ON setting is selected. Bit 26: DPUP 0 1 Description Sets pullup resistance of data pins (D63 to D0) ON Sets pullup resistance of data pins (D63 to D0) OFF (Initial value) Bit 25--Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor status for control input pins (NMI, ,5/3-,5/6, %5(4, MD6/,2,649, 5'<). IPUP is initialized by a power-on reset. Bit 25: IPUP 0 1 Description Pull-up resistor is on for control input pins (NMI, ,5/3-,5/6, %5(4, MD6/,2,649, 5'<) (Initial value) Pull-up resistor is off for control input pins (NMI, ,5/3-,5/6, %5(4, MD6/,2,649, 5'<) Bit 24--Control Output Pin Pull-Up Resistor Control (OPUP): Specifies the pull-up resistor status for control output pins (A[25:0], %6, &6Q, 5', :(Q, RD/:5, 5$6, 5$65, &(5$, &(5%, 5'5, RD/:55) when high-impedance. OPUP is initialized by a power-on reset. Bit 24: OPUP 0 1 Description Pull-up resistor is on for control output pins (A[25:0], %6, &6Q, 5', :(Q, RD/:5, 5$6, 5$65, &(5$, &(5%, 5'5, RD/:55) (Initial value) Pull-up resistor is off for control output pins (A[25:0], %6, &6Q, 5', :(Q, RD/:5, 5$6, 5$65, &(5$, &(5%, 5'5, RD/:55) Bit 21--Area 1 SRAM Byte Control Mode (A1MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 21: A1MBC 0 1 Description Area 1 SRAM is set to normal mode Area 1 SRAM is set to byte control mode (Initial value) Rev. 6.0, 07/02, page 328 of 986 Bit 20--Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 20: A4MBC 0 1 Description Area 4 SRAM is set to normal mode Area 4 SRAM is set to byte control mode (Initial value) Bit 19--BREQ Enable (BREQEN): Indicates whether external requests can be accepted. BREQEN is initialized to the external request acceptance disabled state by a power-on reset. It is ignored in the case of a slave mode startup. Bit 19: BREQEN 0 1 Description External requests are not accepted External requests are accepted (Initial value) Bit 18--Partial-Sharing Bit (PSHR): Sets partial-sharing mode. PSHR is valid only in the case of a master mode startup. Bit 18: PSHR 0 1 Description Master mode Partial-sharing mode (Initial value) Bit 17--Area 1 to 6 MPX Interface Specification (MEMMPX): Sets the MPX interface when areas 1 to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a power-on reset. Bit 17: MEMMPX 0 1 Description SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are set as SRAM interface (or burst ROM interface) (Initial value) MPX interface is selected when areas 1 to 6 are set as SRAM interface (or burst ROM interface) Rev. 6.0, 07/02, page 329 of 986 Bit 16--DMAC Burst Mode Transfer Priority Setting (DMABST) (SH7750R Only): Specifies the priority of burst mode transfers by the DMAC. When OFF, the priority is as follows: bus privilege released, refresh, DMAC, CPU. When ON, the bus privileges are released and refresh operations are not performed until the end of the DMAC's burst transfer. This bit is initialized at a power-on reset. Bit 16: DMABST 0 1 Description DMAC burst mode transfer priority specification OFF DMAC burst mode transfer priority specification ON (Initial value) Bit 15--High Impedance Control (HIZMEM): Specifies the state of address and other signals (A[25:0], %6, &6Q, RD/:5, &(5$, &(5%) in software standby mode. Bit 15: HIZMEM 0 Description The A[25:0], %6, &6Q, RD/:5, &(5$, and &(5% signals go to highimpedance (High-Z) in standby mode and when the bus is released (Initial value) The A[25:0], %6, &6Q, RD/:5, &(5$, and &(5% signals are driven in standby mode. When the bus is released, they go to high-impedance. 1 Bit 14--High Impedance Control (HIZCNT): Specifies the state of the 5$6 and &$6 signals in software standby mode and when the bus is released. Bit 14: HIZCNT 0 Description The 5$6, 5$65, :(Q/&$6Q/DQMn, 5'/&$66/)5$0(, and 5'5 signals go to high-impedance (High-Z) in standby mode and when the bus is released (Initial value) The 5$6, 5$65, :(Q/&$6Q/DQMn, 5'/&$66/)5$0(, and 5'5 signals are driven in standby mode and when the bus is released 1 Rev. 6.0, 07/02, page 330 of 986 Bits 13 to 11--Area 0 Burst ROM Control (A0BST2-A0BST0): These bits specify whether burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored. Bit 13: A0BST2 0 Bit 12: A0BST1 0 Bit 11: A0BST0 0 1 Description Area 0 is accessed as SRAM interface (Initial value) Area 0 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, 32-, or 64*-bit bus width 1 0 Area 0 is accessed as burst ROM interface (8 consecutive accesses) Can only be used with 8-, 16-, or 32-bit bus width 1 Area 0 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 0 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 1 Note: * Settable only for SH7750R. 0 1 Reserved Reserved Reserved Rev. 6.0, 07/02, page 331 of 986 Bits 10 to 8--Area 5 Burst Enable (A5BST2-A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 5 is an MPX interface area, these bits are ignored. Bit 10: A5BST2 0 Bit 9: A5BST1 0 Bit 8: A5BST0 0 1 Description Area 5 is accessed as SRAM interface (Initial value) Area 5 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, 32-, or 64*-bit bus width 1 0 Area 5 is accessed as burst ROM interface (8 consecutive accesses) Can only be used with 8-, 16-, or 32-bit bus width 1 Area 5 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 5 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 1 0 1 Note: Clear to 0 when PCMCIA interface is set. * Settable only for SH7750R. Reserved Reserved Reserved Rev. 6.0, 07/02, page 332 of 986 Bits 7 to 5--Area 6 Burst Enable (A6BST2-A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 6 is an MPX interface area, these bits are ignored. Bit 7: A6BST2 0 Bit 6: A6BST1 0 Bit 5: A6BST0 0 1 Description Area 6 is accessed as SRAM interface (Initial value) Area 6 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, 32-, or 64*-bit bus width 1 0 Area 6 is accessed as burst ROM interface (8 consecutive accesses) Can only be used with 8-, 16-, or 32-bit bus width 1 Area 6 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 6 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 1 0 1 Note: Clear to 0 when PCMCIA interface is set. * Settable only for SH7750R. Reserved Reserved Reserved Rev. 6.0, 07/02, page 333 of 986 Bits 4 to 2--Area 2 and 3 Memory Type (DRAMTP2-DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface. DRAM and synchronous DRAM can also be connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description 0 0 0 Areas 2 and 3 are SRAM interface or 1 MPX interface* (Initial value) Reserved (Cannot be set) Area 2 is SRAM interface or MPX 1 interface* , area 3 is synchronous DRAM interface Areas 2 and 3 are synchronous DRAM interface Area 2 is SRAM interface or MPX 1 interface* , area 3 is DRAM interface Areas 2 and 3 are DRAM interface* Reserved (Cannot be set) Reserved (Cannot be set) 2 1 1 0 1 1 0 0 1 1 Note: 0 1 *1 Selection of SRAM interface or MPX interface is determined by the setting of the MEMMPX bit *2 When this mode is selected, 16 or 32 bits should be specified as the bus width for areas 2 and 3. In this mode the MD5 pin is designated for output as the 5$65 pin. Bit 0--Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as PCMCIA interface. The setting of these bits has priority over the MEMMPX bit settings. Bit 0: A56PCM 0 1 Description Areas 5 and 6 are accessed as SRAM interface Areas 5 and 6 are accessed as PCMCIA interface* (Initial value) Note: * The MD3 pin is designated for output as the &(5$ pin. The MD4 pin is designated for output as the &(5% pin. Rev. 6.0, 07/02, page 334 of 986 13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used. BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in standby mode. External memory space other than area 0 should not be accessed until register initialization is completed. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 A0SZ1 0/1* R 7 A3SZ1 1 R/W 14 A0SZ0 0/1* R 6 A3SZ0 1 R/W 13 A6SZ1 1 R/W 5 A2SZ1 1 R/W 12 A6SZ0 1 R/W 4 A2SZ0 1 R/W 11 A5SZ1 1 R/W 3 A1SZ1 1 R/W 10 A5SZ0 1 R/W 2 A0SZ0 1 R/W 9 A4SZ1 1 R/W 1 -- 0 -- 8 A4SZ0 1 R/W 0 PORTEN 0 R/W Note: * These bits sample the values of the external pins that specify the area 0 bus size. Bits 15 and 14--Area 0 Bus Width (A0SZ1, A0SZ0): These bits sample the external pins, MD4 and MD3 that specify the bus size in a power-on reset by the 5(6(7 pin. They are read-only bits. Bit 15 A0SZ1 0 Bit 14 A0SZ0 0 1 1 0 1 Description Bus width is 64 bits Bus width is 8 bits Bus width is 16 bits Bus width is 32 bits Rev. 6.0, 07/02, page 335 of 986 Bits 2n + 1, 2n--Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify the bus width of area n (n = 1 to 6). (Bit 0): PORTEN Bit 2n + 1: AnSZ1 0 0 Bit 2n: AnSZ0 0 1 1 0 1 1 0 0 1 1 0 1 Description Bus width is 64 bits Bus width is 8 bits Bus width is 16 bits Bus width is 32 bits (Initial value) Reserved (Setting prohibited) Bus width is 8 bits Bus width is 16 bits Bus width is 32 bits Bit 1--Reserved: This bit is always read as 0, and should only be written with 0. Bit 0--Port Function Enable (PORTEN): Specifies whether pins D51 to D32 are used as a 20bit port. When this function is used, a bus width of 8, 16, or 32 bits should be set for all areas. Bit 0: PORTEN 0 1 Description D51 to D32 are not used as a port D51 to D32 are used as a port (Initial value) Rev. 6.0, 07/02, page 336 of 986 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of either the MPX interface or the SRAM interface and specifies the burst length when the synchronous DRAM interface is used. BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. No external memory space other than area 0 should be accessed before register initialization has been completed. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 MEMMODE 14 A1MPX 0 R/W 6 -- 0 R 13 A4MPX 0 R/W 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 SDBL 0 R/W 0 R/W 7 -- 0 R Bit 15A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by MEMMPX. Bit 15: MEMMODE 0 1 Description MPX or SRAM interface is selected by MEMMPX MPX or SRAM interface is selected by A1MPX and A4MPX (Initial value) Bits 14 and 13MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These bits specify the types of memory connected to areas 1 and 4. These settings are validated by MEMMODE. Bit 14: A1MPX 0 1 Bit 13: A4MPX 0 1 Description SRAM/byte control SRAM interface is selected for area 1 MPX interface is selected for area 1 Description SRAM/byte control SRAM interface is selected for area 4 MPX interface is selected for area 4 (Initial value) (Initial value) Rev. 6.0, 07/02, page 337 of 986 Bits 12 to 1--Reserved: These bits are always read as 0, and should only be written with 0. Bit 0Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is used. The burst-length setting is only valid when the bus width is 32 bits. Bit 0: SDBL 0 1 Description Burst length is 8 Burst length is 4 (Initial value) 13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only) Bus control register 4 (BCR4) is a 32-bit readable/writable register that enables asynchronous input to the pin corresponding to each bit. BCR4 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle earlier than when synchronous input is set (ASYNCn = 0)* (see figure 13.4) The timings shown in this section and section 22, Electrical Characteristics, are all for the case where synchronous input is set (ASYNCn = 0). Note: * With the synchronous input setting, ensure that setup and hold times are observed. T1 CKIO Tw Tw Twe T2 (BCR4.ASYNC0 = 0) (BCR4.ASYNC0 = 1) Figure 13.4 Example of 5'< Sampling Timing at which BCR4 is Set (Two Wait Cycles are Inserted by WCR2) Rev. 6.0, 07/02, page 338 of 986 Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 31 -- 0 R 23 -- 0 R 15 -- 0 R 7 -- 0 R 30 -- 0 R 22 -- 0 R 14 -- 0 R 6 -- 0 R 29 -- 0 R 21 -- 0 R 13 -- 0 R 5 -- 0 R 28 -- 0 R 20 -- 0 R 12 -- 0 R 4 27 -- 0 R 19 -- 0 R 11 -- 0 R 3 26 -- 0 R 18 -- 0 R 10 -- 0 R 2 ASYNC 25 -- 0 R 17 -- 0 R 9 -- 0 R 1 24 -- 0 R 16 -- 0 R 8 -- 0 R 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 31 to 5Reserved: These bits are always read as 0, and should only be written with 0. Bits 4 to 0Asynchronous Input: These bits enable asynchronous input to the corresponding pin. Bits 4 to 0: ASYNCn 0 1 Bit 4 3 2 1 0 Description Input to corresponding pin is synchronous with CKIO Input to corresponding pin can be asynchronous with CKIO Corresponding Pin ,2,649 '5(44 '5(43 %5(4 5'< (Initial value) Rev. 6.0, 07/02, page 339 of 986 13.2.5 Wait Control Register 1 (WCR1) Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go off immediately after the read signal from off-chip goes off. As a result, there is a possibility of a data bus collision when consecutive memory accesses are performed on memory in different areas, or when a memory write is performed immediately after a read. In the SH7750 Series, the number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision. WCR1 is initialized to H'77777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 31 -- 0 R 23 -- 0 R 15 -- 0 R 7 -- 0 R 30 29 28 27 -- 0 R 19 -- 0 R 11 -- 0 R 3 -- 0 R 26 A6IW2 1 R/W 18 A4IW2 1 R/W 10 A2IW2 1 R/W 2 A0IW2 1 R/W 25 A6IW1 1 R/W 17 A4IW1 1 R/W 9 A2IW1 1 R/W 1 A0IW1 1 R/W 24 A6IW0 1 R/W 16 A4IW0 1 R/W 8 A2IW0 1 R/W 0 A0IW0 1 R/W DMAIW2 DMAIW1 DMAIW0 1 R/W 22 A5IW2 1 R/W 14 A3IW2 1 R/W 6 A1IW2 1 R/W 1 R/W 21 A5IW1 1 R/W 13 A3IW1 1 R/W 5 A1IW1 1 R/W 1 R/W 20 A5IW0 1 R/W 12 A3IW0 1 R/W 4 A1IW0 1 R/W Rev. 6.0, 07/02, page 340 of 986 Bits 31, 27, 23, 19, 15, 11, 7, and 3--Reserved: These bits are always read as 0, and should only be written with 0. Bits 30 to 28-- DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2- DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from a DACK device to another space, or from a read access to a write access on the same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual address transfer, inter-area idle cycles are inserted. Bits 4n + 2 to 4n--Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2-AnlW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the same space. DMAIW2/AnIW2 0 DMAIW1/AnIW1 0 DMAIW0/AnIW0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Idle Cycles 0 1 2 3 6 9 12 15 (Initial value) Rev. 6.0, 07/02, page 341 of 986 * Idle Insertion between Accesses Following Cycle Same Area Read Preceding Cycle Read Write DMA read (memory device) DMA write (device memory) D D M M CPU DMA Write CPU DMA M M Different Area Read CPU M M M DMA M M M Write CPU DMA M M M M M M Same Area Different Area MPX MPX Address Address Output Output M (1) *2 -- M (1) M M (1) D 1 D* D D D D -- D (1) "DMA" in the table indicates DMA single-address transfer. DMA dual transfer is in accordance with the CPU. M, D: Idle wait always inserted by WCR1 (M(1): One cycle inserted in MPX access even if WCR1 is cleared to 0) M: Idle cycles according to setting of AnIW2-AnIW0 (area 0 to area 6) D: Idle cycles according to setting of DMAIW2-DMAIW0 Notes: When synchronous DRAM is used in RAS down mode, set bits DMAIW2-DMAIW0 to 000 and bits A3IW2-A3IW0 to 000. *1 Inserted when device is switched *2 On the MPX interface, a WCR1 idle wait may be inserted before an access (either read or write) to the same area after a write access. The specific conditions for idle wait insertion in accesses to the same area are shown below. (a) Synchronous DRAM set to RAS down mode (b) Synchronous DRAM accessed by on-chip DMAC Apart from use under above conditions (a) and (b), an idle wait is also inserted between an MPX interface write access and a following access to the same area. Even under the above conditions, an idle wait may be inserted in a same-area access following an interface write access, depending on the synchronous DRAM pipeline access situation. An idle wait is not inserted when the WCR1 register setting is 0. The setting for the number of idle state cycles inserted after a power-on reset is the default value of 15 (the maximum value), so ensure that the optimum value is set. Rev. 6.0, 07/02, page 342 of 986 13.2.6 Wait Control Register 2 (WCR2) Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of wait states to be inserted for each area. It also specifies the data access pitch when performing burst memory access. This enables low-speed memory to be connected without using external circuitry. WCR2 is initialized to H'FFFEEFFF by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 31 A6W2 1 R/W 23 A5W0 1 R/W 15 A3W2 1 R/W 7 A1W1 1 R/W 30 A6W1 1 R/W 22 A5B2 1 R/W 14 A3W1 1 R/W 6 A1W0 1 R/W 29 A6W0 1 R/W 21 A5B1 1 R/W 13 A3W0 1 R/W 5 A0W2 1 R/W 28 A6B2 1 R/W 20 A5B0 1 R/W 12 -- 0 R 4 A0W1 1 R/W 27 A6B1 1 R/W 19 A4W2 1 R/W 11 A2W2 1 R/W 3 A0W0 1 R/W 26 A6B0 1 R/W 18 A4W1 1 R/W 10 A2W1 1 R/W 2 A0B2 1 R/W 25 A5W2 1 R/W 17 A4W0 1 R/W 9 A2W0 1 R/W 1 A0B1 1 R/W 24 A5W1 1 R/W 16 -- 0 R 8 A1W2 1 R/W 0 A0B0 1 R/W Rev. 6.0, 07/02, page 343 of 986 Bits 31 to 29--Area 6 Wait Control (A6W2--A6W0): These bits specify the number of wait states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle Bit 31: A6W2 0 Bit 30: A6W1 0 Bit 29: A6W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 28 to 26--Area 6 Burst Pitch (A6B2-A6B0): These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer with the burst ROM interface selected. Description Burst Cycle (Excluding First Cycle) Wait States Inserted from Second Data Access Onward 0 1 2 3 4 5 6 7 (Initial value) Bit 28: A6B2 0 Bit 27: A6B1 0 Bit 26: A6B0 0 1 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled 1 0 1 1 0 0 1 1 0 1 Rev. 6.0, 07/02, page 344 of 986 Bits 25 to 23--Area 5 Wait Control (A5W2-A5W0): These bits specify the number of wait states to be inserted for area 5. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle Bit 25: A5W2 0 Bit 24: A5W1 0 Bit 23: A5W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 22 to 20--Area 5 Burst Pitch (A5B2-A5B0): These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer with the burst ROM interface selected. Description Burst Cycle (Excluding First Cycle) Bit 22: A5B2 0 Bit 21: A5B1 0 Bit 20: A5B0 0 1 1 0 1 1 0 0 1 1 0 1 Wait States Inserted from Second Data Access Onward 0 1 2 3 4 5 6 7 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 6.0, 07/02, page 345 of 986 Bits 19 to 17--Area 4 Wait Control (A4W2-A4W0): These bits specify the number of wait states to be inserted for area 4. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description Bit 19: A4W2 0 Bit 18: A4W1 0 Bit 17: A4W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 16 and 12--Reserved: These bits are always read as 0, and should only be written with 0. Bits 15 to 13--Area 3 Wait Control (A3W2-A3W0): These bits specify the number of wait states to be inserted for area 3. External wait input is only enabled when SRAM interface or MPX interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). * When SRAM Interface is Set Description Bit 15: A3W2 0 Bit 14: A3W1 0 Bit 13: A3W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 6.0, 07/02, page 346 of 986 * When DRAM or Synchronous DRAM Interface is Set* 1 Description Bit 15: A3W2 0 Bit 14: A3W1 0 Bit 13: A3W0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: *1 External wait input is always ignored. *2 Inhibited in RAS down mode. DRAM &$6 Assertion Width 1 2 3 4 7 10 13 16 Synchronous DRAM &$6 Latency Cycles Inhibited 1* 2 3 4* 5* 2 2 2 Inhibited Inhibited Bits 11 to 9--Area 2 Wait Control (A2W2-A2W0): These bits specify the number of wait states to be inserted for area 2. External wait input is only enabled when the SRAM interface or MPX interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). * When SRAM Interface is Set Description Bit 11: A2W2 0 Bit 10: A2W1 0 Bit 9: A2W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 6.0, 07/02, page 347 of 986 * When DRAM or Synchronous DRAM Interface is Set* 1 Description Bit 11: A2W2 0 Bit 10: A2W1 0 Bit 9: A2W0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: *1 External wait input is always ignored. *2 RAS down mode is prohibited. DRAM &$6 Assertion Width 1 2 3 4 7 10 13 16 Synchronous DRAM &$6 Latency Cycles Inhibited 1* 2 3 4* 5* 2 2 2 Inhibited Inhibited Bits 8 to 6--Area 1 Wait Control (A1W2-A1W0): These bits specify the number of wait states to be inserted for area 1. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description Bit 8: A1W2 0 Bit 7: A1W1 0 Bit 6: A1W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 6.0, 07/02, page 348 of 986 Bits 5 to 3--Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle Bit 5: A0W2 0 Bit 4: A0W1 0 Bit 3: A0W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 2 to 0--Area 0 Burst Pitch (A0B2-A0B0): These bits specify the number of wait states to be inserted afterwards the second data access in a burst transfer with the burst ROM interface selected. Description Burst Cycle (Excluding First Cycle) Bit 2: A0B2 0 Bit 1: A0B1 0 Bit 0: A0B0 0 1 1 0 1 1 0 0 1 1 0 1 Wait States Inserted from Second Data Access Onward 0 1 2 3 4 5 6 7 (Initial value) 5'< Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 6.0, 07/02, page 349 of 986 Table 13.6 MPX Interface is Selected (Areas 0 to 6) Description Inserted Wait States 1st Data AnW2 0 AnW1 0 AnW0 0 1 1 0 1 1 0 0 1 1 (n = 6 to 0) 0 1 2 3 2 3 1 Read 1 Write 0 1 2 3 0 1 2 3 1 2nd Data Onward 0 5'< Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 6.0, 07/02, page 350 of 986 13.2.7 Wait Control Register 3 (WCR3) Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area. This enables low-speed memory to be connected without using external circuitry. WCR3 is initialized to H'07777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: 31 -- 0 R 23 -- 0 R 15 -- 0 R 7 30 -- 0 R 22 A5S0 1 R/W 14 A3S0 1 R/W 6 A1S0 1 R/W 29 -- 0 R 21 A5H1 1 R/W 13 A3H1 1 R/W 5 A1H1 1 R/W 28 -- 0 R 20 A5H0 1 R/W 12 A3H0 1 R/W 4 A0H0 1 R/W 27 -- 0 R 19 A4RDH* 0 R/W* 11 -- 0 R 3 -- 0 R 26 A6S0 1 R/W 18 A4S0 1 R/W 10 A2S0 1 R/W 2 A0S0 1 R/W 25 A6H1 1 R/W 17 A4H1 1 R/W 9 A2H1 1 R/W 1 A0H1 1 R/W 24 A6H0 1 R/W 16 A4H0 1 R/W 8 A2H0 1 R/W 0 A0H0 1 R/W Bit name: A1RDH* Initial value: R/W: Note: * SH7750R only 0 R/W* Bits 31 to 27, 23, 19*, 15, 11, 7*, and 3--Reserved: These bits are always read as 0, and should only be written with 0. Note: * SH7750R only Rev. 6.0, 07/02, page 351 of 986 Bit 4n + 2--Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface. Bit 4n + 2: AnS0 0 1 Waits Inserted in Setup 0 1 (Initial value) (n = 6 to 0) Bits 4n + 1 and 4n--Area n (6 to 0) Data Hold Time (AnH1, AnH0): When writing, these bits specify the number of cycles to be inserted in the hold time from negation of the write strobe. When reading, they specify the number of cycles to be inserted in the hold time from the data sampling timing. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface. Bit 4n + 1: AnH1 0 Bit 4n: AnH0 0 1 1 0 1 Waits Inserted in Hold 0 1 2 3 (Initial value) (n = 6 to 0) Bits 4n+3Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in the SH7750R): When reading, these bits specify the timing for the negation of read strobe. These bits should be cleared to 0 when a byte control SRAM setting is made. Bit 4n + 3: AnRDH 0 1 Read-Strobe Negate Timing Negation occurs after insertion of the number of hold wait cycles specified by the AnH setting (Initial value) Negation occurs based on the read strobe data sampling timing (n = 4 or 1) 13.2.8 Memory Control Register (MCR) The memory control register (MCR) is a 32-bit readable/writable register that specifies 5$6 and &$6 timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected without using external circuitry. MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bits RASD, MRSET, TRC2-0, TPC2-0, RCD1-0, TRWL2-0, TRAS2-0, BE, SZ1-0, AMXEXT, AMX2-0, and EDOMODE are written in the initialization following a powerRev. 6.0, 07/02, page 352 of 986 on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the same values should be written to the other bits so that they remain unchanged. When using DRAM or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is completed. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 31 RASD 0 R/W 23 TCAS 0 R/W 15 TRWL2 0 R/W 7 SZ0 0 R/W 30 MRSET 0 R/W 22 -- 0 R 14 TRWL1 0 R/W 6 29 TRC2 0 R/W 21 TPC2 0 R/W 13 TRWL0 0 R/W 5 28 TRC1 0 R/W 20 TPC1 0 R/W 12 TRAS2 0 R/W 4 AMX1 0 R/W 27 TRC0 0 R/W 19 TPC0 0 R/W 11 TRAS1 0 R/W 3 AMX0 0 R/W 26 -- 0 R 18 -- 0 R 10 TRAS0 0 R/W 2 RFSH 0 R/W 25 -- 0 R 17 RCD1 0 R/W 9 BE 0 R/W 1 RMODE 0 R/W 24 -- 0 R 16 RCD0 0 R/W 8 SZ1 0 R/W 0 EDO MODE 0 R/W AMXEXT AMX2 0 R/W 0 R/W Bit 31--RAS Down (RASD): Sets RAS down mode. When DRAM/RAS down mode is used, set BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both designated as synchronous DRAM interface. Bit 31: RASD 0 1 Description Normal mode RAS down mode (Initial value) Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2-DMAIW0 to 000 and bits A3IW2-A3IW0 to 000. Rev. 6.0, 07/02, page 353 of 986 Bit 30--Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface. Bit 30: MRSET 0 1 Description All-bank precharge Mode register setting (Initial value) Bits 29 to 27--RAS Precharge Time at End of Refresh (TRC2-TRC0) (Synchronous DRAM: auto- and self-refresh both enabled; DRAM: auto- and self-refresh both enabled) RAS Precharge Interval Immediately after Refresh 0 3 6 9 12 15 18 21 (Initial value) Bit 29: TRC2 0 Bit 28: TRC1 0 Bit 27: TRC0 0 1 1 0 1 1 0 0 1 1 0 1 Bits 26 to 24, 22, and 18--Reserved: These bits are always read as 0, and should only be written with 0. Bit 23--CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set. Bit 23: TCAS 0 1 CAS Negation Period 1 2 (Initial value) Rev. 6.0, 07/02, page 354 of 986 Bits 21 to 19--RAS Precharge Period (TPC2-TPC0): When the DRAM interface is set, these bits specify the minimum number of cycles until 5$6 is asserted again after being negated. When the synchronous DRAM interface is set, these bits specify the minimum number of cycles until the next bank active command is output after precharging. RAS Precharge Interval Bit 21: TPC2 0 Bit 20: TPC1 0 Bit 19: TPC0 0 1 1 0 1 1 0 0 1 1 Note: * Inhibited in RAS down mode. 0 1 DRAM 0 1 2 3 4 5 6 7 Synchronous DRAM 1* (Initial value) 2 3 4* 5* 6* 7* 8* Bits 17 and 16--RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits set the 5$6-&$6 assertion delay time. When the synchronous DRAM interface is set, these bits set the bank active-read/write command delay time. Description Bit 17: RCD1 0 Bit 16: RCD0 0 1 1 0 1 Note: * Inhibited in RAS down mode. DRAM 2 cycles 3 cycles 4 cycles 5 cycles Synchronous DRAM Reserved (Setting prohibited) 2 cycles 3 cycles 4 cycles* Bits 15 to 13--Write Precharge Delay (TRWL2-TRWL0): These bits set the synchronous DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next bank active command is issued after a write cycle. After a write cycle, the next active command is not issued for a period of TPC + TRWL. In RAS down mode, they specify the time until the next precharge command is issued. After a write cycle, the next precharge command is not issued for a period of TRWL. This setting is valid only when synchronous DRAM interface is set. For the setting values and delay time when no command is issued, refer to section 22.3.3, Bus Timing. Rev. 6.0, 07/02, page 355 of 986 Bit 15: TRWL2 0 Bit 14: TRWL1 0 Bit 13: TRWL0 0 1 Write Precharge ACT Delay Time 1 (Initial value) 2 3* 4* 5* Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) 1 0 1 1 0 0 1 1 Note: * Inhibited in RAS down mode. 0 1 Bits 12 to 10--CAS-Before-RAS Refresh 5$6 Assertion Period (TRAS2-TRAS0): When the DRAM interface is set, these bits set the 5$6 assertion period in CAS-before-RAS refreshing. When the synchronous DRAM interface is set, the bank active command is not issued for a period of TRC* + TRAS after an auto-refresh command is issued. Note: * Bits 29 to 27: RAS precharge interval at end of refresh. Command Interval after Synchronous DRAM Refresh 4 + TRC* (Initial value) 5 + TRC 6 + TRC 7 + TRC 8 + TRC 9 + TRC 10 + TRC 11 + TRC Bit 12: TRAS2 0 Bit 11: TRAS1 0 Bit 10: TRAS0 0 1 5$6/DRAM 5$6 Assertion Period 2 3 4 5 6 7 8 9 1 0 1 1 0 0 1 1 0 1 Note: * Bits 29 to 27: RAS precharge interval at end of refresh. Bit 9--Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In synchronous DRAM access, burst access is always performed regardless of the specification of this bit. The DRAM transfer mode depends on EDOMODE. Rev. 6.0, 07/02, page 356 of 986 BE 0 EDOMODE 0 1 8/16/32/64-Bit Transfer Single Setting prohibited Single/fast page* EDO 32-Byte Transfer Single Setting prohibited Fast page EDO 1 0 1 Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus. Bits 8 and 7--Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM. This setting has priority over the BCR2 register setting. Description Bit 8: SZ1 0 Bit 7: SZ0 0 1 1 0 1 DRAM 64 bits Reserved (Setting prohibited) 16 bits 32 bits SDRAM 64 bits Reserved (Setting prohibited) Reserved (Setting prohibited) 32 bits Bits 6 to 3--Address Multiplexing (AMXEXT, AMX2-AMX0): These bits specify address multiplexing for DRAM and synchronous DRAM. The address shift value is different for the DRAM interface and the synchronous DRAM interface. * For DRAM Interface: Bit 6: AMXEXT 0* Bit 5: AMX2 0 Bit 4: AMX1 0 Bit 3: AMX0 0 1 1 0 1 1 0 0 1 1 0 1 Description DRAM 8-bit column address product (Initial value) 9-bit column address product 10-bit column address product 11-bit column address product 12-bit column address product Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Note: * When the DRAM interface is used, clear the AMXEXT bit to 0. Rev. 6.0, 07/02, page 357 of 986 * For Synchronous DRAM Interface: AMX 0 AMXEXT 0 1 1 0 1 2 3 4 5 6 -- -- -- -- 0 1 0 1 7 Notes: *1 *2 *3 *4 -- SZ 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 64 32 32 64 32 Example of Synchronous DRAM (16M: 512k x 16 bits x 2) x 4 (16M: 512k x 16 bits x 2) x 2 (16M: 512k x 16 bits x 2) x 4 (16M: 512k x 16 bits x 2) x 2 (16M: 1M x 8 bits x 2) x 8 (16M: 1M x 8 bits x 2) x 4 (16M: 1M x 8 bits x 2) x 8 (16M: 1M x 8 bits x 2) x 4 (64M: 1M x 16 bits x 4) x 4 (64M: 1M x 16 bits x 4) x 2 (64M: 2M x 8 bits x 4) x 8 (64M: 2M x 8 bits x 4) x 4 (64M: 512k x 32 bits x 4) x 2 (64M: 512k x 32 bits x 4) x 1 (64M: 1M x 32 bits x 2) x 2 (64M: 1M x 32 bits x 2) x 1 (128M: 4M x 8 bits x 4) x 8* (128M: 4M x 8 bits x 4) x 4* 2 2 4 BANK* 1 a[22]* 1 a[21]* 1 a[21]* 1 a[20]* 1 a[23]* 1 a[22]* 1 a[22]* 1 a[21]* a[24:23]* a[23:22]* a[24:23]* 1 1 1 1 1 1 a[25:24]* a[23:22]* 1 a[23]* 1 a[22]* a[22:21]* a[26:25]* a[26:25]* a[25:24]* 3 1 1 1 1 (256M: 4M x 16 bits x 4) x 4* 3 (256M: 4M x 16 bits x 4) x 2* (16M: 256k x 32 bits x 2) x 2 (16M: 256k x 32 bits x 2) x 1 a[25:24]* 1 a[21]* 1 a[20]* a[*]: Not an address pin but an external address Can only be set in the SH7750R. Can only be set in the SH7750S/SH7750R (Setting prohibited in the SH7750). For details on address multiplexing, refer to appendix F, Synchronous DRAM Address Multiplexing Tables. Bit 2--Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh request cycle generation timer can be used as an interval timer. Bit 2: RFSH 0 1 Description Refreshing is not performed Refreshing is performed (Initial value) Rev. 6.0, 07/02, page 358 of 986 Bit 1--Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CASbefore-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous DRAM, after waiting for the end of any currently executing external bus cycle. All refresh requests for memory in the self-refresh state are ignored. Bit 1: RMODE 0 1 Description CAS-before-RAS refreshing is performed (when RFSH = 1) Self-refreshing is performed (when RFSH = 1) (Initial value) Bit 0--EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of memory other than DRAM. Set this bit to 1 only when DRAM is used. 13.2.9 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the 2( and :( signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6. The 2( and :( signal assertion width is set by the wait control bits in the WCR2 register. For details of access to PCMCIA, see section 13.3.7, PCMCIA Interface. PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 15 14 13 12 11 10 9 8 Bit name: A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 Bit name: A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 6.0, 07/02, page 359 of 986 Bits 15 and 14--PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0. Bit 15: A5PCW1 0 Bit 14: A5PCW0 0 1 1 0 1 Waits Inserted 0 (Initial value) 15 30 50 Bits 13 and 12--PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Bit 13: A6PCW1 0 Bit 12: A6PCW0 0 1 1 0 1 Waits Inserted 0 (Initial value) 15 30 50 Bits 11 to 9--Address-2( :( Assertion Delay (A5TED2-A5TED0): These bits set the delay 2(/:( 2( time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0. Bit 11: A5TED2 0 Bit 10: A5TED1 0 Bit 9: A5TED0 0 1 1 0 1 1 0 0 1 1 0 1 Waits Inserted 0 (Initial value) 1 2 3 6 9 12 15 Rev. 6.0, 07/02, page 360 of 986 Bits 8 to 6--Address-2( :( Assertion Delay (A6TED2-A6TED0): These bits set the delay 2(/:( 2( time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Bit 8: A6TED2 0 Bit 7: A6TED1 0 Bit 6: A6TED0 0 1 1 0 1 1 0 0 1 1 0 1 Waits Inserted 0 (Initial value) 1 2 3 6 9 12 15 Bits 5 to 3--2( :( Negation-Address Delay (A5TEH2-A5TEH0): These bits set the address 2(/:( 2( hold delay time from 2(/:( negation in a write on the connected PCMCIA interface or in an I/O card read. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0. Bit 5: A5TEH2 0 Bit 4: A5TEH1 0 Bit 3: A5TEH0 0 1 1 0 1 1 0 0 1 1 0 1 Waits Inserted 0 (Initial value) 1 2 3 6 9 12 15 Bits 2 to 0--2( :( Negation-Address Delay (A6TEH2-A6TEH0): These bits set the address 2(/:( 2( hold delay time from 2(/:( negation in a write on the connected PCMCIA interface or in an I/O card read. In the case of a memory card read, the address hold delay time from the data sampling timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Rev. 6.0, 07/02, page 361 of 986 Bit 2: A6TEH2 0 Bit 1: A6TEH1 0 Bit 0: A6TEH0 0 1 Waits Inserted 0 (Initial value) 1 2 3 6 9 12 15 1 0 1 1 0 0 1 1 0 1 13.2.10 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3 synchronous DRAM. Settings for the SDMR register must be made before accessing synchronous DRAM. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: -- W -- W -- W -- W -- W -- W -- W -- W -- W 7 -- W 6 -- W 5 -- W 4 -- W 3 -- W 2 -- W 1 -- W 0 15 14 13 12 11 10 9 8 Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register, if the value to be set is "X" and the SDMR register address is "Y", value "X" is written to the synchronous DRAM mode register by performing a write to address X + Y. When the synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to A2 of the SH7750 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7750 Series, the value actually written to the synchronous DRAM is the value of "X" shifted 2 bits to the right. Rev. 6.0, 07/02, page 362 of 986 For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address H'FF900000 (address "Y") + H'08C0 (value "X") (= H'FF9008C0). As a result, H'0230 is written to the SDMR register. The range of value "X" is H'0000 to H'0FFC. Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address H'FF940000 (address "Y") + H'08C0 (value "X") (= H'FF9408C0). As a result, H'0230 is written to the SDMR register. The range of value "X" is H'0000 to H'0FFC. The lower 16 bits of the address are set in the synchronous DRAM mode register. When the bus width is 32 bits, the burst length is 4* and 8. When the bus width is 64 bits, the burst length is fixed at 4. When a setting is made in SDMR, byte-size writes are performed at the following addresses. Bus Width 32 Burst Length 4* CAS Latency 1 2 3 32 8 1 2 3 64 4 1 2 3 Area 2 H'FF900048 H'FF900088 H'FF9000C8 H'FF90004C H'FF90008C H'FF9000CC H'FF900090 H'FF900110 H'FF900190 Area 3 H'FF940048 H'FF940088 H'FF9400C8 H'FF94004C H'FF94008C H'FF9400CC H'FF940090 H'FF940110 H'FF940190 For a 32-bit bus: 17 Address 0 16 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 3 2 1 0 LMO LMO LMO WT BL2 BL1 BL0 DE2 DE1 DE0 10 bits set in case of 32-bit bus width For a 64-bit bus: 17 Address 0 16 0 15 0 14 0 13 0 12 0 11 0 10 0 9 8 7 6 5 4 3 2 1 0 LMO LMO LMO WT BL2 BL1 BL0 DE2 DE1 DE0 10 bits set in case of 64-bit bus width Rev. 6.0, 07/02, page 363 of 986 LMODE: RAS-CAS latency BL: Burst length WT: Wrap type (0: Sequential) BL 000: Reserved 001: Reserved 010: 4 011: 8 100: Reserved 101: Reserved 110: Reserved 111: Reserved LMODE 000: Reserved 001: 1 010: 2 011: 3 100: Reserved 101: Reserved 110: Reserved 111: Reserved Note: * SH7750R only. 13.2.11 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that specifies the refresh cycle and whether interrupts are to be generated. RTCSR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 -- 7 CMF 0 R/W 14 -- 0 -- 6 CMIE 0 R/W 13 -- 0 -- 5 CKS2 0 R/W 12 -- 0 -- 4 CKS1 0 R/W 11 -- 0 -- 3 CKS0 0 R/W 10 -- 0 -- 2 OVF 0 R/W 9 -- 0 -- 1 OVIE 0 R/W 8 -- 0 -- 0 LMTS 0 R/W Bits 15 to 8--Reserved: These bits are always read as 0. For the write values, see section 13.2.15, Notes on Accessing Refresh Control Registers. Rev. 6.0, 07/02, page 364 of 986 Bit 7--Compare-Match Flag (CMF): Status flag that indicates a match between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR) values. Bit 7: CMF 0 Description RTCNT and RTCOR values do not match [Clearing condition] When 0 is written to CMF 1 RTCNT and RTCOR values match [Setting condition] When RTCNT = RTCOR* Note: * If 1 is written, the original value is retained. (Initial value) Bit 6--Compare-Match Interrupt Enable (CMIE): Controls generation or suppression of an interrupt request when the CMF flag is set to 1 in RTCSR. Do not set this bit to 1 when CASbefore-RAS refreshing or auto-refreshing is used. Bit 6: CMIE 0 1 Description Interrupt requests initiated by CMF are disabled Interrupt requests initiated by CMF are enabled (Initial value) Bits 5 to 3--Clock Select Bits (CKS2-CKS0): These bits select the input clock for RTCNT. The base clock is the external bus clock (CKIO). The RTCNT count clock is obtained by scaling CKIO by the specified factor. Bit 5: CKS2 0 Bit 4: CKS1 0 Bit 3: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Clock input disabled Bus clock (CKIO)/4 CKIO/16 CKIO/64 CKIO/256 CKIO/1024 CKIO/2048 CKIO/4096 (Initial value) Rev. 6.0, 07/02, page 365 of 986 Bit 2--Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified by the LMTS bit in RTCSR. Bit 2: OVF 0 Description RFCR has not overflowed the count limit indicated by LMTS [Clearing condition] When 0 is written to OVF 1 RFCR has overflowed the count limit indicated by LMTS [Setting condition] When RFCR overflows the count limit set by LMTS* Note: * If 1 is written, the original value is retained. (Initial value) Bit 1--Refresh Count Overflow Interrupt Enable (OVIE): Controls generation or suppression of an interrupt request when the OVF flag is set to 1 in RTCSR. Bit 1: OVIE 0 1 Description Interrupt requests initiated by OVF are disabled Interrupt requests initiated by OVF are enabled (Initial value) Bit 0--Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value exceeds the value specified by LMTS, the OVF flag is set. Bit 0: LMTS 0 1 Description Count limit is 1024 Count limit is 512 (Initial value) Rev. 6.0, 07/02, page 366 of 986 13.2.12 Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by the input clock (selected by bits CKS2-CKS0 in the RTCSR register). When the RTCNT counter value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the RTCNT counter is cleared. RTCNT is initialized to H'0000 by a power-on reset, but continues to count when a manual reset is performed. In standby mode, RTCNT is not initialized, and retains its contents. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 -- 0 -- 7 14 -- 0 -- 6 13 -- 0 -- 5 12 -- 0 -- 4 11 -- 0 -- 3 10 -- 0 -- 2 9 -- 0 -- 1 8 -- 0 -- 0 Rev. 6.0, 07/02, page 367 of 986 13.2.13 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are constantly compared, and when they match the CMF bit is set in the RTCSR register and the RTCNT counter is cleared to 0. If the refresh bit (RFSH) has been set to 1 in the memory control register (MCR) and CAS-before-RAS has been selected as the refresh mode, a memory refresh cycle is generated when the CMF bit is set. RTCOR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 -- 0 -- 7 14 -- 0 -- 6 13 -- 0 -- 5 12 -- 0 -- 4 11 -- 0 -- 3 10 -- 0 -- 2 9 -- 0 -- 1 8 -- 0 -- 0 Rev. 6.0, 07/02, page 368 of 986 13.2.14 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of refreshes by being incremented each time the RTCOR register and RTCNT counter values match. If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR register, the OVF flag is set in the RTCSR register and the RFCR register is cleared. RFCR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 -- 0 -- 7 14 -- 0 -- 6 13 -- 0 -- 5 12 -- 0 -- 4 11 -- 0 -- 3 10 -- 0 -- 2 0 R/W 1 0 R/W 0 9 8 13.2.15 Notes on Accessing Refresh Control Registers When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The following procedures should be used for read/write operations. Writing to RTCSR, RTCNT, RTCOR, and RFCR: A word transfer instruction must always be used when writing to RTCSR, RTCNT, RTCOR, or RFCR. A write cannot be performed with a byte transfer instruction. When writing to RTCSR, RTCNT, or RTCOR, set B'10100101 in the upper byte and the write data in the lower byte, as shown in figure 13.5. When writing to RFCR, set B'101001 in the 6 bits starting from the MSB in the upper byte, and the write data in the remaining bits. Rev. 6.0, 07/02, page 369 of 986 RTCSR, RTCNT, RTCOR 15 1 14 0 13 1 12 0 11 0 10 1 9 0 8 1 7 6 5 4 3 2 1 0 Write data 15 RFCR 1 14 0 13 1 12 0 11 0 10 1 9 8 7 6 5 4 3 2 1 0 Write data Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0. 13.3 13.3.1 Operation Endian/Access Size and Data Alignment The SH7750 Series supports both big-endian mode, in which the most significant byte (MSByte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (LSByte) is at the 0 address end. The mode is set by means of the MD5 external pin in a power-on reset by the 5(6(7 pin, big-endian mode being set if the MD5 pin is low, and littleendian mode if it is high. A data bus width of 8, 16, 32, or 64 bits can be selected for normal memory, 16, 32, or 64 bits for DRAM, 32 or 64 bits for synchronous DRAM, and 8 or 16 bits for the PCMCIA interface. Data alignment is carried out according to the data bus width and endian mode of each device. If the data bus width is smaller than the access size, a number of bus cycles will be generated automatically until the access size is reached. In this case, address incrementing is performed automatically according to the bus width as access is performed. For example, if longword access is performed in an 8-bit bus width area using the SRAM interface, four accesses are executed, with the address automatically incremented by 1 each time. In 32-byte transfer, a total of 32 bytes of data are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on 32-byte boundary data using wraparound. Bus release or refresh operations are not performed between these transfers. Data alignment and data length conversion between the different interfaces is performed automatically. Quadword access is used only in transfer by the DMAC. The relationship between the endian mode, device data length, and access unit, is shown in tables 13.7 to 13.14. Rev. 6.0, 07/02, page 370 of 986 Data Configuration MSB Byte Data 7 to 0 LSB MSB Word Data 15 to 8 Data 7 to 0 LSB MSB Longword Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 LSB MSB Quadword Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Data 31 to 24 Data 23 to 16 Data 15 to 8 LSB Data 7 to 0 Rev. 6.0, 07/02, page 371 of 986 Table 13.7 (1) Operation 64-Bit External Device/Big-Endian Access and Data Alignment Data Bus D55-48 -- Data 7-0 -- -- -- -- -- -- Data 7-0 -- -- -- Data 23-16 -- Data 55-48 D47-40 -- -- Data 7-0 -- -- -- -- -- -- Data 15-8 -- -- Data 15-8 -- Data 47-40 D39-32 -- -- -- Data 7-0 -- -- -- -- -- Data 7-0 -- -- Data 7-0 -- Data 39-32 D31-24 -- -- -- -- Data 7-0 -- -- -- -- -- Data 15-8 -- -- Data 31-24 Data 31-24 D23-16 -- -- -- -- -- Data 7-0 -- -- -- -- Data 7-0 -- -- Data 23-16 Data 23-16 D15-8 -- -- -- -- -- -- Data 7-0 -- -- -- -- Data 15-8 -- Data 15-8 Data 15-8 D7-0 -- -- -- -- -- -- -- Data 7-0 -- -- -- Data 7-0 -- Data 7-0 Data 7-0 Access Size Address No. D63-56 Byte 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 Word 8n 8n+2 8n+4 8n+6 Longword 8n 8n+4 Quadword 8n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data 7-0 -- -- -- -- -- -- -- Data 15-8 -- -- -- Data 31-24 -- Data 63-56 Rev. 6.0, 07/02, page 372 of 986 Table 13.7 (2) Operation 64-Bit External Device/Big-Endian Access and Data Alignment Strobe Signals :(9, :(9 &$69, &$69 DQM6 :(8, :(8 &$68, &$68 DQM5 :(7, :(7 &$67, &$67 DQM4 :(6, :(6 &$66, &$66 DQM3 :(5, :(5 &$65, &$65 DQM2 :(4, :(4 &$64, &$64 DQM1 :(3, :(3 &$63, &$63 DQM0 :(:, :(: Access &$6:, &$6: Size Address No. DQM7 Byte 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 Word 8n 8n+2 8n+4 8n+6 Longword Quadword 8n 8n+4 8n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Rev. 6.0, 07/02, page 373 of 986 Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus :(6, :(6 &$66, &$66 DQM3 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Strobe Signals :(5, :(5 &$65, &$65 DQM2 :(4, :(4 &$64, &$64 DQM1 :(3, :(3 &$63, &$63 DQM0 Access Size Address No. D31-D24 D23-D16 D15-D8 D7-D0 Byte 4n 4n+1 4n+2 4n+3 Word 4n 4n+2 Longword Quadword 4n 8n 8n+4 1 1 1 1 1 1 1 1 2 Data 7-0 -- -- -- Data 15-8 -- Data 31-24 Data 63-56 Data 31-24 -- Data 7-0 -- -- Data 7-0 -- Data 23-16 Data 55-48 Data 23-16 -- -- Data 7-0 -- -- Data 15-8 Data 15-8 Data 47-40 Data 15-8 -- -- -- Data 7-0 -- Data 7-0 Data 7-0 Data 39-32 Data 7-0 Rev. 6.0, 07/02, page 374 of 986 Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus :(6, :(6 &$66, &$66 DQM3 Strobe Signals :(5, :(5 &$65, &$65 DQM2 :(4, :(4 &$64, &$64 DQM1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted :(3, :(3 &$63, &$63 DQM0 Access Size Address No. D31-D24 D23-D16 D15-D8 D7-D0 Byte 2n 2n+1 Word Longword 2n 4n 4n+2 Quadword 8n 8n+2 8n+4 8n+6 1 1 1 1 2 1 2 3 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 -- Data 15-8 Data 31-24 Data 15-8 Data 63-56 Data 47-40 Data 31-24 Data 15-8 -- Data 7-0 Data 7-0 Data 23-16 Data 7-0 Data 55-48 Data 39-32 Data 23-16 Data 7-0 Rev. 6.0, 07/02, page 375 of 986 Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus :(6, :(6 &$66, &$66 DQM3 Strobe Signals :(5, :(5 &$65, &$65 DQM2 :(4, :(4 &$64, &$64 DQM1 :(3, :(3 &$63, &$63 DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Access Size Address No. D31-D24 D23-D16 D15-D8 D7-D0 Byte Word n 2n 2n+1 Longword 4n 4n+1 4n+2 4n+3 Quadword 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 1 1 2 1 2 3 4 1 2 3 4 5 6 7 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 Data 15-8 Data 7-0 Data 31-24 Data 23-16 Data 15-8 Data 7-0 Data 63-56 Data 55-48 Data 47-40 Data 39-32 Data 31-24 Data 23-16 Data 15-8 Data 7-0 Rev. 6.0, 07/02, page 376 of 986 Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Access Size Address No. D63-56 Byte 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 Word 8n 8n+2 8n+4 8n+6 Longword 8n 8n+4 Quadword 8n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- Data 7-0 -- -- -- Data 15-8 -- Data 31-24 Data 63-56 D55-48 -- -- -- -- -- -- Data 7-0 -- -- -- -- Data 7-0 -- Data 23-16 Data 55-48 Data 15-8 -- -- Data 15-8 Data 47-40 Data 7-0 -- -- Data 7-0 Data 39-32 D47-40 -- -- -- -- -- Data 7-0 -- -- -- Data Bus D39-32 -- -- -- -- Data 7-0 -- -- -- -- D31-24 -- -- -- Data 7-0 -- -- -- -- -- Data 15-8 -- -- Data 31-24 -- Data 31-24 D23-16 -- -- Data 7-0 -- -- -- -- -- -- Data 7-0 -- -- Data 23-16 -- Data 23-16 D15-8 -- Data 7-0 -- -- -- -- -- -- Data 15-8 -- -- -- Data 15-8 -- Data 15-8 D7-0 Data 7-0 -- -- -- -- -- -- -- Data 7-0 -- -- -- Data 7-0 -- Data 7-0 Rev. 6.0, 07/02, page 377 of 986 Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment Operation :(:, :(: Access &$6:, &$6: Size Address No. DQM7 Byte 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 Word 8n 8n+2 8n+4 8n+6 Longword Quadword 8n 8n+4 8n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted :(9, :(9 &$69, &$69 DQM6 :(8, :(8 &$68, &$68 DQM5 Strobe Signals :(7, :(7 &$67, &$67 DQM4 :(6, :(6 &$66, &$66 DQM3 :(5, :(5 &$65, &$65 DQM2 :(4, :(4 &$64, &$64 DQM1 :(3, :(3 &$63, &$63 DQM0 Asserted Rev. 6.0, 07/02, page 378 of 986 Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment Operation Access Size Address No. Byte 4n 4n+1 4n+2 4n+3 Word 4n 4n+2 Longword Quadword 4n 8n 8n+4 1 1 1 1 1 1 1 1 2 -- -- Data 7-0 -- Data 15-8 Data 31-24 Data 31-24 Data 63-56 Data Bus :(6, :(6 &$66, &$66 DQM3 Strobe Signals :(5, :(5 &$65, &$65 DQM2 :(4, :(4 &$64, &$64 DQM1 :(3, :(3 &$63, &$63 DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted D31-D24 D23-D16 -- -- Data 7-0 -- -- Data 7-0 Data 23-16 Data 23-16 Data 55-48 D15-D8 -- Data 7-0 -- -- Data 15-8 -- Data 15-8 Data 15-8 Data 47-40 D7-D0 Data 7-0 -- -- -- Data 7-0 -- Data 7-0 Data 7-0 Data 39-32 Rev. 6.0, 07/02, page 379 of 986 Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus :(6, :(6 &$66, &$66 DQM3 Strobe Signals :(5, :(5 &$65, &$65 DQM2 :(4, :(4 &$64, &$64 DQM1 :(3, :(3 &$63, &$63 DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Access Size Address No. D31-D24 D23-D16 D15-D8 D7-D0 Byte 2n 2n+1 Word Longword 2n 4n 4n+2 Quadword 8n 8n+2 8n+4 8n+6 1 1 1 1 2 1 2 3 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 Data 15-8 Data 15-8 Data 31-24 Data 15-8 Data 31-24 Data 47-40 Data 63-56 Data 7-0 -- Data 7-0 Data 7-0 Data 23-16 Data 7-0 Data 23-16 Data 39-32 Data 55-48 Rev. 6.0, 07/02, page 380 of 986 Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus :(6, :(6 &$66, &$66 DQM3 Strobe Signals :(5, :(5 &$65, &$65 DQM2 :(4, :(4 &$64, &$64 DQM1 :(3, :(3 &$63, &$63 DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Access Size Address No. D31-D24 D23-D16 D15-D8 D7-D0 Byte Word n 2n 2n+1 Longword 4n 4n+1 4n+2 4n+3 Quadword 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 1 1 2 1 2 3 4 1 2 3 4 5 6 7 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 Data 7-0 Data 15-8 Data 7-0 Data 15-8 Data 23-16 Data 31-24 Data 7-0 Data 15-8 Data 23-16 Data 31-24 Data 39-32 Data 47-40 Data 55-48 Data 63-56 Rev. 6.0, 07/02, page 381 of 986 13.3.2 Areas Area 0: For area 0, external address bits A28 to A26 are 000. SRAM, MPX, and burst ROM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins MD4 and MD3. For details, see Memory Bus Width in section 13.1.5. When area 0 is accessed, the &63 signal is asserted. In addition, the 5' signal, which can be used as 2(, and write control signals :(3 to :(:, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A0W2 to A0W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (5'<). When the burst ROM interface is used, the number of burst cycle transfer states is selected in the range 2 to 9 according to the number of waits. The read/write strobe signal address and the &6 setup/hold time can be set, respectively, to 0 or 1 and to 0 to 3 cycles using the A0S0, A0H1, and A0H0 bits in the WCR3 register. Area 1: For area 1, external address bits A28 to A26 are 001. SRAM, MPX and byte control SRAM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A1SZ1 and A1SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus width of 16, 32, or 64 bits. When area 1 is accessed, the &64 signal is asserted. In addition, the 5' signal, which can be used as 2(, and write control signals :(3 to :(:, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A1W2 to A1W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (5'<). The read/write strobe signal address and &6 setup and hold times can be set within a range of 0-1 and 0-3 cycles, respectively, by means of bit A1S0 and bits A1H1 and A1H0 in the WCR3 register. Rev. 6.0, 07/02, page 382 of 986 Area 2: For area 2, external address bits A28 to A26 are 010. SRAM, MPX, DRAM, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When synchronous DRAM interface is set, select 32 or 64 bits with the SZ bits in the MCR register. When DRAM is connected to area 2, select a bus width of 16 or 32 bits with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5. When area 2 is accessed, the &65 signal is asserted. When SRAM interface is set, the 5' signal, which can be used as 2(, and write control signals :(3 to :(:, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A2W2 to A2W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (5'<). The read/write strobe signal address and &6 setup and hold times can be set within a range of 0-1 and 0-3 cycles, respectively, by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3 register. When synchronous DRAM interface is set, the 5$6 and &$6 signals, RD/:5 signal, and byte control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. 5$6, &$6, and data timing control, and address multiplexing control, can be set using the MCR register. When DRAM is connected, the 5$65 signal, &$67 to &$6: signals, and RD/:5 signal are asserted, and address multiplexing is performed. 5$65, &$6, and data timing control, and address multiplexing control, can be set using the MCR register. Area 3: For area 3, external address bits A28 to A26 are 011. SRAM, MPX, DRAM, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A3SZ1 and A3SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A3SZ1 and A3SZ0 in the BCR2 register. When DRAM interface is set, 16, 32, or 64 bits can be selected with the SZ bits in the MCR register. When synchronous DRAM interface is set, select 32 or 64 bits with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5. When area 3 is accessed, the &66 signal is asserted. Rev. 6.0, 07/02, page 383 of 986 When SRAM interface is set, the 5' signal, which can be used as 2(, and write control signals :(3 to :(:, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (5'<). The read/write strobe signal address and &6 setup and hold times can be set within a range of 0-1 and 0-3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3 register. When synchronous DRAM interface is set, the 5$6 and &$6 signals, RD/:5 signal, and byte control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. When DRAM interface is set, the 5$6 signal, &$63 to &$6: signals, and RD/:5 signal are asserted, and address multiplexing is performed. 5$6, &$6, and data timing control, and address multiplexing control, can be set using the MCR register. Area 4: For area 4, external address bits A28 to A26 are 100. SRAM, MPX, and byte control SRAM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A4SZ1 and A4SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus width of 16, 32, or 64 bits. For details, see Memory Bus Width in section 13.1.5. When area 4 is accessed, the &67 signal is asserted, and the 5' signal, which can be used as 2(, and write control signals :(3 to :(:, are also asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A4W2 to A4W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (5'<). The read/write strobe signal address and &6 setup and hold times can be set within a range of 0-1 and 0-3 cycles, respectively, by means of bit A4S0 and bits A4H1 and A4H0 in the WCR3 register. Rev. 6.0, 07/02, page 384 of 986 Area 5: For area 5, external address bits A28 to A26 are 101. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A5SZ1 and A5SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can be selected with bits A5SZ1 and A5SZ0 in BCR2. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. When a PCMCIA interface is set, either 8 or 16 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. For details, see Memory Bus Width in section 13.1.5. When area 5 set is accessed with SRAM interface set, the &68 signal is asserted. In addition, the 5' signal, which can be used as 2(, and write control signals :(3 to :(:, are asserted. When a PCMCIA interface is connected, the &(4$ and &(5$ signals, the 5' signal, which can be used as 2(, and the :(4, :(5, :(6, and :(: signals, which can be used as :(, ,&,25', ,&,2:5, and 5(*, respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (5'<). When the burst function is used, the number of burst cycle transfer states is determined in the range 2 to 9 according to the number of waits. The read/write strobe signal address and &6 setup and hold times can be set within a range of 0-1 and 0-3 cycles, respectively, by means of bit A5S0 and bits A5H1 and A5H0 in the WCR3 register. When a PCMCIA interface is used, the address/&(4$/&(5$ setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in PCR is added to the number of waits set in WCR2. Rev. 6.0, 07/02, page 385 of 986 Area 6: For area 6, external address bits A28 to A26 are 110. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A6SZ1 and A6SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can be selected with bits A6SZ1 and A6SZ0 in BCR2. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A6SZ1 and A6SZ0 in BCR2. When a PCMCIA interface is set, either 8 or 16 bits should be selected with bits A6SZ1 and A6SZ0 in BCR2. For details, see Memory Bus Width in section 13.1.5. When area 6 is accessed with SRAM interface set, the &69 signal is asserted. In addition, the 5' signal, which can be used as 2(, and write control signals :(3 to :(:, are asserted. When a PCMCIA interface is set, the &(4% and &(5% signals, the 5' signal, which can be used as 2(, and the :(4, :(5, :(6, and :(: signals, which can be used as :(, ,&,25', ,&,2:5, and 5(*, respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A6W2 to A6W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (5'<). When the burst function is used, the number of burst cycle transfer states is determined in the range 2 to 9 according to the number of waits. The read/write strobe signal address and &6 setup and hold times can be set within a range of 0-1 and 0-3 cycles, respectively, by means of bit A6S0 and bits A6H1 and A6H0 in the WCR3 register. When a PCMCIA interface is used, the address/&(4%/&(5% setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in PCR is added to the number of waits set in WCR2. Rev. 6.0, 07/02, page 386 of 986 13.3.3 SRAM Interface Basic Timing: The SRAM interface of the SH7750 Series uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The %6 signal is asserted for one cycle to indicate the start of a bus cycle. The &6Q signal is asserted on the T1 rising edge, and negated on the next T2 clock rising edge. Therefore, there is no negation period in case of access at minimum pitch. There is no access size specification when reading. The correct access address is output to the address pins (A[25:0]), but since there is no access size specification, 32 bits are always read in the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only the :( signal for the byte to be written is asserted. For details, see section 13.3.1, Endian/Access Size and Data Alignment. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wrap around mode on the data at the 32-byte boundary. The bus is not released during this transfer. Rev. 6.0, 07/02, page 387 of 986 T1 CKIO A25-A0 T2 RD/ D63-D0 (read) D63-D0 (write) DACKn (SA: IO memory) DACKn (SA: IO memory) DACKn (DA) SA: Single address DMA DA: Dual address DMA Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.6 Basic Timing of SRAM Interface Rev. 6.0, 07/02, page 388 of 986 Figures 13.7, 13.8, 13.9, and 13.10 show examples of connection to 64-, 32-, 16-, and 8-bit data width SRAM. 128k x 8-bit SRAM A16-A0 SH7750 Series A19-A3 D63-D56 I/O7-I/O0 A16-A0 D55-D48 I/O7-I/O0 A16-A0 D47-D40 I/O7-I/O0 A16-A0 D39-D32 I/O7-I/O0 A16-A0 D31-D24 I/O7-I/O0 A16-A0 D23-D16 I/O7-I/O0 A16-A0 D15-D8 I/O7-I/O0 A16-A0 D7-D0 I/O7-I/O0 Figure 13.7 Example of 64-Bit Data Width SRAM Connection Rev. 6.0, 07/02, page 389 of 986 SH7750 Series **** 128k x 8-bit SRAM **** **** **** **** **** **** **** **** **** **** A18 A2 D31 **** A16 A0 I/O7 **** **** D24 D23 **** **** I/O0 D16 **** A16 **** **** D15 D8 A0 I/O7 **** **** **** D7 D0 I/O0 A16 **** A0 I/O7 I/O0 **** A16 **** A0 I/O7 **** I/O0 Figure 13.8 Example of 32-Bit Data Width SRAM Connection Rev. 6.0, 07/02, page 390 of 986 SH7750 Series A17 **** **** **** 128k x 8-bit SRAM A16 A0 **** A1 D15 **** I/O7 **** D8 D7 **** I/O0 D0 **** **** A16 A0 **** I/O7 **** I/O0 Figure 13.9 Example of 16-Bit Data Width SRAM Connection Rev. 6.0, 07/02, page 391 of 986 **** **** SH7750 Series A16 **** **** **** 128k x 8-bit SRAM A16 A0 **** A0 D7 **** **** I/O7 **** D0 I/O0 Figure 13.10 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 13.2.6, Wait Control Register 2 (WCR2). The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait timing shown in figure 13.11. Rev. 6.0, 07/02, page 392 of 986 **** T1 CKIO A25-A0 Tw T2 RD/ D63-D0 (read) D63-D0 (write) DACKn (SA: IO memory) DACKn (SA: IO memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) Rev. 6.0, 07/02, page 393 of 986 When software wait insertion is specified by WCR2, the external wait input 5'< signal is also sampled. 5'< signal sampling is shown in figure 13.12. A single-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the 5'< signal has no effect if asserted in the T1 cycle or the first Tw cycle. The 5'< signal is sampled on the rising edge of the clock. T1 CKIO Tw Twe T2 A25-A0 RD/ (read) D63-D0 (read) (write) D63-D0 (write) DACKn (SA: IO memory) DACKn (SA: IO memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by 5'< Signal) Rev. 6.0, 07/02, page 394 of 986 Read-Strobe Negate Timing (Setting Only Possible in the SH7750R): When the SRAM interface is used, timing for the negation of the strobe during read operations can be specified by the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this setting, see the description of the WCR3 register. When a byte control SRAM setting is made, AnRDH should be cleared to 0. TS1 T1 Tw Tw Tw Tw T2 TH1 TH2 CKIO A25A0 CSn RD/WR * D63D0 BS TS1: Setup wait WCR3.AnS (0 to 1) Tw: Access wait WCR2.AnW (0 to 15) TH1, TH2: Hold wait WCR3.AnH (0 to 3) Note: * When AnRDH is set to 1 Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) 13.3.4 DRAM Interface Direct Connection of DRAM: When the memory type bits (DRAMTP2-0) in BCR1 are set to 100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The DRAM interface function can then be used to connect DRAM to the SH7750. 16, 32, or 64 bits can be selected as the interface data width for area 3 when bits DRAMTP2-0 are set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits DRAMTP2-0 are set to 101. 2-CAS 16-bit DRAMs can be connected, since &$6 is used to control byte access. Rev. 6.0, 07/02, page 395 of 986 Signals used for connection when DRAM is connected to area 3 are 5$6, &$63 to &$6:, and RD/:5. &$65 to &$6: are not used when the data width is 16 bits. When DRAM is connected to areas 2 and 3, the signals for area 2 DRAM connection are 5$65, &$67 to &$6:, and RD/:5, and those for area 3 DRAM connection are 5$6, &$63 to &$66, and RD/:5. In addition to normal read and write access modes, fast page mode is supported for burst access. For DRAM connected to areas 2 and 3, EDO mode, which enables the DRAM access time to be increased, is supported. 1M x 16-bit DRAM A9-A0 SH7750 Series A12-A3 RD/ D63-D48 I/O15-I/O0 A9-A0 D47-D32 I/O15-I/O0 A9-A0 D31-D16 I/O15-I/O0 A9-A0 D15-D0 I/O15-I/O0 Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3) Rev. 6.0, 07/02, page 396 of 986 SH7750 Series A10 **** **** **** 256k x 16-bit DRAM A8 A0 **** A2 RD/ D31 **** **** **** I/O15 I/O0 **** D16 D15 **** D0 **** **** A8 A0 **** I/O15 **** I/O0 Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3) Rev. 6.0, 07/02, page 397 of 986 **** SH7750 Series A9 **** **** **** 256k x 16-bit DRAM A8 A0 Area 3 **** A1 RD/ D15 **** **** **** I/O15 I/O0 **** D0 A8 **** A0 Area 2 **** **** I/O15 I/O0 Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) Rev. 6.0, 07/02, page 398 of 986 **** Address Multiplexing: When area 2 or area 3 is designated as DRAM space, address multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to the SH7750 Series without using an external address multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting bits AMXEXT and AMX2-0 in MCR for area 2 or 3 DRAM. The relationship between the AMXEXT and AMX2-0 bits and address multiplexing is shown in table 13.15. The address output pins subject to address multiplexing are A17 to A1. The address signals output by pins A25 to A18 are undefined. Table 13.15 Relationship between AMXEXT and AMX2-0 Bits and Address Multiplexing Setting AMXEXT 0 AMX2 0 AMX1 0 AMX0 0 Number of Column Address Bits Output Timing 8 bits Column address Row address 1 9 bits Column address Row address 1 0 10 bits Column address Row address 1 11 bits Column address Row address 1 0 0 12 bits Column address Row address Other settings Reserved -- External Address Pins A1-A13 A1-A13 A9-A21 A1-A13 A10-A22 A1-A13 A11-A23 A1-A13 A12-A24 A1-A13 A13-A25 -- A14 A14 A22 A14 A23 A14 A24 A14 A25 A14 A14 -- A15 A15 A23 A15 A24 A15 A25 A15 A15 A15 A15 -- A16 A16 A24 A16 A25 A16 A16 A16 A16 A16 A16 -- A17 A17 A25 A17 A17 A17 A17 A17 A17 A17 A17 -- Rev. 6.0, 07/02, page 399 of 986 Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.17. Tpc is the precharge cycle, Tr the 5$6 assert cycle, Tc1 the &$6 assert cycle, and Tc2 the read data latch cycle. Tr1 CKIO A25-A0 Row Column Tr2 Tc1 Tc2 Tpc RD/ D63-D0 (read) D63-D0 (write) DACKn (SA: IO memory) DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.17 Basic DRAM Access Timing Rev. 6.0, 07/02, page 400 of 986 Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 13.18. Additional Tpc cycles (cycles used to secure the 5$6 precharge time) can be inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from 5$6 assertion to &$6 assertion can be set to between 2 and 5 by inserting Trw cycles by means of the RCD bit in MCR. Also, the number of cycles from &$6 assertion to the end of the access can be varied between 1 and 16 according to the setting of A2W2 to A2W0 or A3W2 to A3W0 in WCR2. Tr1 Tr2 Trw Tc1 Tcw Tc2 Tpc Tpc CKIO A25-A0 Row Column RD/ D63-D0 (read) D63-D0 (write) DACKn (SA: IO memory) DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.18 DRAM Wait State Timing Rev. 6.0, 07/02, page 401 of 986 Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row. This mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access. Normal access or burst access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The timing for burst access using fast page mode is shown in figure 13.19. If the access size exceeds the set bus width, burst access is performed. In a 32-byte burst transfer (cache fill), the first access comprises a longword that includes the data requiring access. The remaining accesses are performed on 32-byte boundary data that includes the relevant data. In burst transfer (cache write-back), wraparound writing is performed for 32-byte data. Tr1 CKIO A25-A0 r c1 c2 c3 c4 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tpc RD/ D63-D0 (read) D63-D0 (write) d1 d1 d2 d2 d3 d3 d4 d4 DACKn (SA: IO memory) DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19 DRAM Burst Access Timing Rev. 6.0, 07/02, page 402 of 986 EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only while the &$6 signal is asserted in a data read cycle, an EDO (extended data out) mode is also provided in which, once the &$6 signal is asserted while the 5$6 signal is asserted, even if the &$6 signal is negated, data is output to the data bus until the &$6 signal is next asserted. In the SH7750, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst access using fast page mode, or EDO mode normal access/burst access, to be selected for DRAM. When EDO mode is set, BE must be set to 1 in MCR. EDO mode normal access is shown in figure 13.20, and burst access in figure 13.21. CAS Negation Period: The CAS negation period can be set to 1 or 2 by means of the TCAS bit in the MCR register. Tr1 CKIO Tr2 Tc1 Tc2 Tce Tpc A25-A0 Row Column RD/ D63-D0 (read) DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) Rev. 6.0, 07/02, page 403 of 986 Tr1 CKIO A25-A0 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce Tpc r c1 c2 c3 c4 RD/ D63-D0 (read) d1 d2 d3 d4 DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.21 Burst Access Timing in DRAM EDO Mode RAS Down Mode: The SH7750 Series has an address comparator for detecting row address matches in burst mode. By using this address comparator, and also setting RAS down mode specification bit RASD to 1, it is possible to select RAS down mode, in which 5$6 remains asserted after the end of an access. When RAS down mode is used, if the refresh cycle is longer than the maximum DRAM 5$6 assert time, the refresh cycle must be decreased to or below the maximum value of tRAS. RAS down mode can only be used when DRAM is connected in area 3. In RAS down mode, in the event of an access to an address with a different row address, an access to a different area, a refresh request, or a bus request, 5$6 is negated and the necessary operation is performed. When DRAM access is resumed after this, since this is the start of RAS down mode, the operation starts with row address output. Timing charts are shown in figures 13.22 (1), (2), (3), and (4). Rev. 6.0, 07/02, page 404 of 986 Tpc CKIO A25-A0 Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 r c1 c2 c3 c4 RD/ D63-D0 (read) D63-D0 (write) d1 d1 d2 d3 d4 d2 d3 d4 DACKn (SA: IO memory) DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0) Rev. 6.0, 07/02, page 405 of 986 Tnop CKIO Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 A25-A0 c0 c1 c2 c3 RD/ End of RAS down mode D63-D0 (read) d0 d1 d2 d3 D63-D0 (write) d0 d1 d2 d3 DACKn (SA: IO memory) DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) Rev. 6.0, 07/02, page 406 of 986 Tpc CKIO A25-A0 Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce r c1 c2 c3 c4 RD/ D63-D0 (read) d1 d2 d3 d4 DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0) Rev. 6.0, 07/02, page 407 of 986 Tc1 CKIO A25-A0 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce c1 c2 c3 c4 RD/ End of RAS down mode D63-D0 (read) d1 d2 d3 d4 DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) Rev. 6.0, 07/02, page 408 of 986 Refresh Timing: The bus state controller includes a function for controlling DRAM refreshing. Distributed refreshing using a CAS-before-RAS cycle can be performed for DRAM by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Self-refresh mode is also supported. * CAS-before-RAS Refresh When CAS-before-RAS refresh cycles are executed, refreshing is performed at intervals determined by the input clock selected by bits CKS2-CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2-CKS0 in RTCOR should be set so as to satisfy the specification for the DRAM refresh interval. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2-CKS0 setting. When the clock is selected by CKS2-CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and the %$&. pin goes high. If the SH7750 Series' external bus can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 13.23 shows the operation of CAS-before-RAS refreshing. RTCNT cleared to 0 when RTCNT = RTCOR RTCNT value RTCOR-1 H'00000000 RTCSR.CKS2-0 Refresh request External bus = 000 000 Time Refresh request cleared by start of refresh cycle CAS-before-RAS refresh cycle Figure 13.23 CAS-Before-RAS Refresh Operation Figure 13.24 shows the timing of the CAS-before-RAS refresh cycle. The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2-TRAS0 in MCR. The specification of the RAS precharge time in the refresh cycle is determined by the setting of bits TRC2-TRC0 in MCR. Rev. 6.0, 07/02, page 409 of 986 TRr1 CKIO A25-A0 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc RD/ D63-D0 Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) * Self-Refresh The self-refreshing supported by the SH7750 Series is shown in figure 13.25. After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge time immediately after the end of the self-refreshing can be set by bits TRC2-TRC0 in MCR. DRAMs include low-power products (L versions) with a long refresh cycle time (for example, the HM51W4160AL L version has a refresh cycle of 1024 cycles/128 ms compared with 1024 cycles/16 ms for the normal version). With these DRAMs, however, the same refresh cycle as for the normal version is requested only in the case of refreshing immediately following selfrefreshing. To ensure efficient DRAM refreshing, therefore, processing is needed to generate an overflow interrupt and restore the refresh cycle to the proper value, after the necessary CAS-before-RAS refreshing has been performed following self-refreshing of an L-version DRAM, using the OVF, OVIE, and LMTS bits in RTCSR and the refresh controller's refresh count register (RFCR). The necessary procedure is as follows. Rev. 6.0, 07/02, page 410 of 986 1. Normally, set the refresh counter count cycle to the optimum value for the L version (e.g. 1024 cycles/128 ms). 2. When a transition is made to self-refreshing: a. Provide an interrupt handler to restore the refresh counter count value to the optimum value for the L version (e.g. 1024 cycles/128 ms) when a refresh counter overflow interrupt is generated. b. Re-set the refresh counter count cycle to the requested short cycle (e.g. 1024 cycles/16 ms), set refresh controller overflow interruption, and clear the refresh controller's refresh count register (RFCR) to 0. c. Set self-refresh mode. By using this procedure, the refreshing immediately following a self-refresh will be performed in a short cycle, and when adequate refreshing ends, an interrupt is generated and the setting can be restored to the original refresh cycle. CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset. When the bus has been released in response to a bus arbitration request, or when a transition is made to standby mode, signals generally become high-impedance, but whether the 5$6 and &$6 signals become high-impedance or continue to be output can be controlled by the HIZCNT bit in BCR1. This enables the DRAM to be kept in the self-refreshing state. As the DRAM &$6 signal is multiplexed with :(Q for normal memory (SRAM, etc.), access to memory that uses the :(Q signals must be disabled during self-refreshing. * Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the %$&. pin is negated (driven high). Therefore, normal refreshing can be performed by having the %$&. pin monitored by a bus Rev. 6.0, 07/02, page 411 of 986 master other than the SH7750 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7750 Series. TRr1 CKIO A25-A0 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc RD/ D63-D0 Figure 13.25 DRAM Self-Refresh Cycle Timing Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 s or 200 s) during which no access can be performed be provided, followed by at least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus state controller does not perform any special operations for a power-on reset, the necessary poweron sequence must be carried out by the initialization program executed after a power-on reset. Rev. 6.0, 07/02, page 412 of 986 13.3.5 Synchronous DRAM Interface Connection of Synchronous DRAM: Since synchronous DRAM can be selected by the &6 signal, it can be connected to physical space areas 2 and 3 using 5$6 and other control signals in common. If the memory type bits (DRAMTP2-0) in BCR1 are set to 010, area 2 is normal memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are both synchronous DRAM space. With the SH7750 Series, burst read/burst write mode is supported as the synchronous DRAM operating mode. The data bus width is 32 or 64 bits, and the SZ size bits in MCR must be set to 00 or 11. The burst enable bit (BE) in MCR is ignored, a 32-byte burst transfer is performed in a cache fill/copy-back cycle, and in a write-through area write or a non-cacheable area read/write, 32-byte data is read even in a single read in order to access synchronous DRAM with a burst read/write access. 32-byte data transfer is also performed in a single write, but DQMn is not asserted when unnecessary data is transferred. For details on the burst length, see section 13.2.10, Synchronous DRAM Module Register (SDMR), and Power-On Sequence in section 13.3.5, Synchronous DRAM Interface. For changing the burst length (a function only available in the SH7750R) for a 32-bit bus, see Notes on Changing the Burst Length (SH7750R Only) in section 13.3.5, Synchronous DRAM Interface. The control signals for connection of synchronous DRAM are 5$6, &$6, RD/:5, &65 or &66, DQM0 to DQM7, and CKE. All the signals other than &65 and &66 are common to all areas, and signals other than CKE are valid and latched only when &65 or &66 is asserted. Synchronous DRAM can therefore be connected in parallel to a number of areas. CKE is negated (driven low) when the frequency is changed, when the clock is unstable after the clock supply is stopped and restarted, or when self-refreshing is performed, and is always asserted (high) at other times. Commands for synchronous DRAM are specified by 5$6, &$6, RD/:5, and specific address signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register setting (MRS). Byte specification is performed by DQM0 to DQM7. A read/write is performed for the byte for which the corresponding DQM signal is low. When the bus width is 64 bits, in big-endian mode DQM7 specifies an access to address 8n, and DQM0 specifies an access to address 8n + 7. In little-endian mode, DQM7 specifies an access to address 8n + 7, and DQM0 specifies an access to address 8n. Figures 13.26 and 13.27 show examples of the connection of 16M x 16-bit synchronous DRAMs. Rev. 6.0, 07/02, page 413 of 986 SH7750 Series A12-A3 CKIO CKE 512k x 16-bit x 2-bank synchronous DRAM A9-A0 CLK CKE RD/ D63-D48 DQM7 DQM6 I/O15-I/O0 DQMU DQML A9-A0 CLK CKE D47-D32 DQM5 DQM4 I/O15-I/O0 DQMU DQML A9-A0 CLK CKE D31-D16 DQM3 DQM2 I/O15-I/O0 DQMU DQML A9-A0 CLK CKE D15-D0 DQM1 DQM0 I/O15-I/O0 DQMU DQML Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) Rev. 6.0, 07/02, page 414 of 986 SH7750 Series A11-A2 CKIO CKE 512k x 16-bit x 2-bank synchronous DRAM A9-A0 CLK CKE RD/ D31-D16 DQM3 DQM2 I/O15-I/O0 DQMU DQML A9-A0 CLK CKE D15-D0 DQM1 DQM0 I/O15-I/O0 DQMU DQML Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2- AMX0 in MCR. Table 13.16 shows the relationship between the address multiplex specification bits and the bits output at the address pins. See Appendix F, Synchronous DRAM Address Multiplexing Tables. Address pin output at A25-A18, A1, and A0 are undefined. When A0, the LSB of the synchronous DRAM address, is connected to the SH7750 Series, with a 32-bit bus width it makes a longword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A2 of the SH7750, then connect pin A1 to pin A3. With a 64-bit bus width, the LSB makes a quadword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A3 of the SH7750, then connect pin A1 to pin A4. Rev. 6.0, 07/02, page 415 of 986 Table 13.16 Example of Correspondence between SH7750 Series and Synchronous DRAM Address Pins (64-Bit Bus Width, AMX2-AMX0 = 011, AMXEXT = 0) SH7750 Series Address Pin RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 -- -- -- CAS Cycle A22 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Not used Not used Not used Synchronous DRAM Address Pin Function BANK select bank address Address precharge setting Burst Read: The timing chart for a burst read is shown in figure 13.28. In the following example it is assumed that four 512k x 16-bit x 2-bank synchronous DRAMs are connected, and a 64-bit data width is used. The burst length is 4. Following the Tr cycle in which ACTV command output is performed, a READA command is issued in the Tc1 cycle, and the read data is accepted on the rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle. In the SH7750 Series, the number of Tpc cycles is determined by the specification of bits TPC2- TPC0 in MCR, and commands are not issued for synchronous DRAM during this interval. The example in figure 13.28 shows the basic cycle. To connect slower synchronous DRAM, the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV command output cycle, Tr, to the READA command output cycle, Tc1, can be specified by bits RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READA command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles independently for areas 2 and 3 by means of bits A2W2-A2W0 and A3W2-A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Rev. 6.0, 07/02, page 416 of 986 Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Bank Row Precharge-sel Row H/L Address Row c0 RD/ DQMn D63-D0 (read) d0 d1 d2 d3 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.28 Basic Timing for Synchronous DRAM Burst Read In a synchronous DRAM cycle, the %6 signal is asserted for one cycle at the start of the data transfer cycle corresponding to the READ or READA command. The order of access is as follows: in a fill operation in the event of a cache miss, 64-bit boundary data including the missed data is read first, then 16-byte boundary data including the missed data is read in wraparound mode. The remaining 16 bytes of the 32-byte boundary data are read by the READA command issued next. Rev. 6.0, 07/02, page 417 of 986 Single Read: With the SH7750 Series, as synchronous DRAM is set to burst read/burst write mode, read data output continues after the required data has been read. To prevent data collisions, after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and the SH7750 Series waits for the end of the synchronous DRAM operation. The %6 signal is asserted only in Td1. When the data width is 64 bits, there are 4 burst transfers in a read. In cache-through and other DMA read cycles, of cycles Td1 to Td4, %6 is asserted and data latched only in the Td1 cycle. Since such empty cycles increase the memory access time, and tend to reduce program execution speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM specified as the source. Tr CKIO Bank Row Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc Tpc Tpc Precharge-sel Row H/L c1 Address Row RD/ DQMn D63-D0 (read) c1 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.29 Basic Timing for Synchronous DRAM Single Read Rev. 6.0, 07/02, page 418 of 986 Burst Write: The timing chart for a burst write is shown in figure 13.30. In the SH7750 Series, a burst write occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst write operation, the WRITA command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output. In the write cycle, the write data is output at the same time as the write command. In the case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for synchronous DRAM is postponed during this interval. The number of Trwl cycles can be specified by bits TRWL2-TRWL0 in MCR. 32-byte boundary data is written in wraparound mode. DACK is asserted two cycles before the data write cycle. Tr CKIO Bank Precharge-sel Address Row Row Row H/L c1 Trw Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Tpc RD/ DQMn D63-D0 (read) c1 c2 c3 c4 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.30 Basic Timing for Synchronous DRAM Burst Write Rev. 6.0, 07/02, page 419 of 986 Single Write: The basic timing chart for write access is shown in figure 13.31. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command. In the case of a write with auto-precharge, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for synchronous DRAM until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for synchronous DRAM is postponed during this interval. The number of Trwl cycles can be specified by bits TRWL2-TRWL0 in MCR. DACK is asserted two cycles before the data write cycle. As the SH7750 Series supports burst read/burst write operations for synchronous DRAM, there are empty cycles in a single write operation. Rev. 6.0, 07/02, page 420 of 986 Tr CKIO Bank Precharge-sel Address Trw Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Tpc Row Row Row H/L c1 RD/ DQMn D63-D0 (read) c1 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.31 Basic Timing for Synchronous DRAM Single Write Rev. 6.0, 07/02, page 421 of 986 RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command, in the same way as in the DRAM RAS down state. As synchronous DRAM is internally divided into two or four banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl + Tpc cycles after issuance of the WRIT command. When RAS down mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tpc cycles for each write. The number of cycles between issuance of the precharge command and the row address strobe command is determined by bits TPC2- TPC0 in MCR. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. In this way, it is possible to observe the restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. A burst read cycle without auto-precharge is shown in figure 13.32, a burst read cycle for the same row address in figure 13.33, and a burst read cycle for different row addresses in figure 13.34. Similarly, a burst write cycle without auto-precharge is shown in figure 13.35, a burst write cycle for the same row address in figure 13.36, and a burst write cycle for different row addresses in figure 13.37. When synchronous DRAM is read, there is a 2-cycle latency for the DMQn signal that performs the byte specification. As a result, when the READ command is issued in figure 13.32, if the Tc cycle is executed immediately, the DMQn signal specification for Td1 cycle data output cannot be carried out. Therefore, the CAS latency should not be set to 1. When RAS down mode is set, if only accesses to the respective banks in area 3 are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 13.32 or 13.35, followed by repetition of the cycle in figure 13.33 or 13.36. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 13.34 or 13.37 is executed instead of Rev. 6.0, 07/02, page 422 of 986 that in figure 13.33 or 13.36. In RAS down mode, too, a PALL command is issued before a refresh cycle or before bus release due to bus arbitration. Tr CKIO Bank Precharge-sel Address Row Row Row H/L c1 Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 RD/ DQMn D63-D0 (read) c1 c2 c3 c4 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.32 Burst Read Timing Rev. 6.0, 07/02, page 423 of 986 Tc1 CKIO Bank Precharge-sel Address Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 H/L c1 RD/ DQMn D63-D0 (read) c1 c2 c3 c4 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.33 Burst Read Timing (RAS Down, Same Row Address) Rev. 6.0, 07/02, page 424 of 986 Tpr CKIO Bank Tpc Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Row Precharge-sel Row H/L Address Row c1 RD/ DQMn D63-D0 (read) c1 c2 c3 c4 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses) Rev. 6.0, 07/02, page 425 of 986 Tr CKIO Bank Precharge-sel Address Trw Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Row Row Row H/L c1 RD/ DQMn D63-D0 (read) c1 c2 c3 c4 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.35 Burst Write Timing Rev. 6.0, 07/02, page 426 of 986 Tncp CKIO Bank Precharge-sel Address Tnop Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Row H/L c1 RD/ DQMn D63-D0 (read) c1 c2 c3 c4 CKE Single-address DMA DACKn (SA: IO memory) Normal write Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line. DACKn shows an example where DMAC, CHCRn, and AL (acknowledge level) are 0. Figure 13.36 Burst Write Timing (Same Row Address) Rev. 6.0, 07/02, page 427 of 986 Tpr CKIO Bank Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Trw1 Row Precharge-sel Row Row H/L Address c1 RD/ DQMn D63-D0 (read) c1 c2 c3 c4 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.37 Burst Write Timing (Different Row Addresses) Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally divided into two or four banks, after a READ or WRIT command is issued for one bank it is possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch cycle, or during the data write cycle, and so shorten the access cycle. When a read access is followed by another read access to the same row address, after a READ command has been issued, another READ command is issued before the end of the data latch cycle, so that there is read data on the data bus continuously. When an access is made to another Rev. 6.0, 07/02, page 428 of 986 row address and the bank is different, the PRE command or ACTV command can be issued during the CAS latency cycle or data latch cycle. If there are consecutive access requests for different row addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACT command, depending on the bank and row address, but since the write data is output at the same time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that one or two empty cycles occur automatically on the data bus. Similarly, with a read access following a write access, or a write access following a write access, the PRE, ACTV, READ, or WRIT command is issued during the data write cycle for the preceding access; however, in the case of different row addresses in the same bank, a PRE command cannot be issued, and so in this case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits in MCR, after the end of the last data write cycle. Figure 13.38 shows a burst read cycle for a different bank and row address following a preceding burst read cycle. Pipelined access is enabled only for consecutive access to area 3, and will be discontinued in the event of an access to another area. Pipelined access is also discontinued in the event of a refresh cycle, or bus release due to bus arbitration. The cases in which pipelined access is available are shown in table 13.17. In this table, "DMAC dual" indicates transfer in DMAC dual address mode, and "DMAC single", transfer in DMAC single address mode. Rev. 6.0, 07/02, page 429 of 986 Tc1_A CKIO Bank Precharge-sel Address H/L c_A Tc1_B H/L c_B RD/ DQMn D63-D0 (read) a1 a2 a3 a4 b1 b2 CKE Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Rev. 6.0, 07/02, page 430 of 986 Table 13.17 Cycles for which Pipeline Access is Possible Succeeding Access CPU Preceding Access CPU Read Write DMAC dual Read Write DMAC single Read Write Read X X X O O O Write X X X O O O DMAC Dual Read O O X O X O Write X X X X X X DMAC Single Read O O X O O O Write O O X O O O O: Pipeline access possible X: Pipeline access not possible Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. * Auto-Refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2- CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2-CKS0 in RTCOR should be set so as to satisfy the refresh interval specification for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2-CKS0 setting last of all. When the clock is selected by CKS2-CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 13.40 shows the auto-refresh cycle timing. First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by bits TRAS2-TRAS0 in MCR plus the number of cycles specified by bits TRC2-TRC0 in MCR. The TRAS2- TRAS0 and TRC2-TRC0 bits must be set so as to satisfy the synchronous DRAM refresh cycle time specification (active/active command delay time). Auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. When both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is performed subsequent to area 3. Rev. 6.0, 07/02, page 431 of 986 RTCNT value RTCOR-1 RTCNT cleared to 0 when RTCNT = RTCOR H'00000000 RTCSR.CKS2-0 Refresh request External bus = 000 000 Time Refresh request cleared by start of refresh cycle Auto-refresh cycle Figure 13.39 Auto-Refresh Operation TRr1 CKIO TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc RD/ DQMn D63-D0 CKE Figure 13.40 Synchronous DRAM Auto-Refresh Timing Rev. 6.0, 07/02, page 432 of 986 * Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by bits TRC2-TRC0 in MCR. Self-refresh timing is shown in figure 13.41. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the SH7750 Series' standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In the case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset. Rev. 6.0, 07/02, page 433 of 986 TRs1 CKIO TRs2 TRs3 TRs4 TRs5 Trc Trc Trc RD/ DQMn D63-D0 CKE Figure 13.41 Synchronous DRAM Self-Refresh Timing * Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the %$&. pin is negated (driven high). Therefore, normal refreshing can be performed by having the %$&. pin monitored by a bus master other than the SH7750 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7750 Series. Rev. 6.0, 07/02, page 434 of 986 Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the 5$6, &$6, and RD/:5 signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'FF900000 + X for area 2 synchronous DRAM, and to address H'FF940000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/write, CAS latency 1 to 3, wrap type = sequential, and burst length 4* or 8, supported by the SH7750, arbitrary data is written by byte-size access to the following addresses. Bus Width 32 Burst Length 4* CAS Latency 1 2 3 32 8 1 2 3 64 4 1 2 3 Note: * SH7750R only. Area 2 H'FF900048 H'FF900088 H'FF9000C8 H'FF90004C H'FF90008C H'FF9000CC H'FF900090 H'FF900110 H'FF900190 Area 3 H'FF940048 H'FF940088 H'FF9400C8 H'FF94004C H'FF94008C H'FF9400CC H'FF940090 H'FF940110 H'FF940190 The value set in MCR.MRSET is used to select whether a precharge all banks command or a mode register setting command is issued. The timing for the precharge all banks command is shown in figure 13.42 (1), and the timing for the mode register setting command in figure 13.42 (2). Before mode register, a 200 s idle time (depending on the memory manufacturer) must be guaranteed after the power required for the synchronous DRAM is turned on. If the reset signal pulse width is greater than this idle time, there is no problem in making the precharge all banks setting immediately. First, a precharge all banks (PALL) command is issued in the TRp1 cycle by performing a write to address H'FF900000 + X or H'FF940000 + X while MCR.MRSET = 0. Next, the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. This is achieved automatically while various kinds of initialization are being performed after autorefresh setting, but a way of carrying this out more dependably is to change the RTCOR register value to set a short refresh request generation interval just while these dummy cycles are being executed. With simple read or write access, the address counter in the synchronous DRAM used for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. After Rev. 6.0, 07/02, page 435 of 986 auto-refreshing has been executed at least the prescribed number of times, a mode register setting command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to address H'FF900000 + X or H'FF940000 + X. Synchronous DRAM mode register setting should be executed once only after power-on (reset) and before synchronous DRAM access, and no subsequent changes should be made. TRp1 CKIO TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 Bank Precharge-sel Address RD/ D31-D0 CKE (High) Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) Rev. 6.0, 07/02, page 436 of 986 TRp1 CKIO TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 Bank Precharge-sel Address RD/ D31-D0 CKE (High) Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) Rev. 6.0, 07/02, page 437 of 986 Notes on Changing the Burst Length (SH7750R Only): In the SH7750R, when synchronous DRAM is connected with a 32-bit memory bus, the burst length can be selected as either 4 or 8 by the setting of the SDBL bit of the BCR3 register. For more details, see the description of the BCR3 register. * Burst Read Figure 13.43 is the timing chart of a burst-read operation with a burst length of 4. Following the Tr cycle, during which an ACTV command is output, a READ command is issued during cycle Tc1, and a READA command is issued four cycles later. During the Td1 to Td8 cycles, read data are accepted on the rising edges of the external command clock (CKIO). Tpc is the cycle used to wait for the auto-precharging, which is triggered by the READA command, to be completed in the synchronous DRAM. During this cycle, a new command for accessing the same bank cannot be issued. In this LSI, the number of Tpc cycles is determined by the setting of the TPC2 to TPC0 bits of MCR, and no command that operates on the synchronous DRAM may be issued during these cycles. Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Tpc Bank Row Precharge-sel Row H/L H/L Address Row c1 c5 RD/ DQMn D31-D0 (read) c1 c2 c3 c4 c5 c6 c7 c8 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4) Rev. 6.0, 07/02, page 438 of 986 In a synchronous DRAM cycle, the %6 signal is asserted for one cycle at the beginning of each data transfer cycle that is in response to a READ or READA command. Data are accessed in the following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that include the missing data are first read by the initial READ command; after that, the data between 16-bit boundaries data that include the missing data are read in a wraparound way. The subsequently issued READA command reads the 16 bytes of data, which is the remainder of the data between 32-byte boundaries, from the start of the 16-byte boundary. * Burst Write Figure 13.44 is the timing chart for a burst-write operation with a burst length of 4. In this LSI, a burst write takes place when a 32-byte data transfer has occurred. In a burst-write operation, subsequent to the Tr cycle, in which ACTV command output takes place, a WRIT command is issued during the Tc1 cycle, and a WRITA command is issued four cycles later. During the write cycle, write data is output together with the write command. With a write command that includes an auto precharge, the precharge is performed on the relevant bank of the synchronous DRAM on completion of the write command so no new command that accesses the same bank can be issued until precharging is completed. For this reason, Trwl cycles, which are a period of waiting for precharging to start after the write command, are added. This is additional to the precharge-waiting cycle used in read access. These cycles delay the issuing of new commands to the synchronous DRAM. The setting of the TRWL2 to TRWL0 bits of MCR selects the number of Trwl cycles. The data between 16-byte boundaries is first accessed, and the data between 32-byte boundaries are then written in a wraparound way. DACK is asserted for two cycles before the data-write cycle. Rev. 6.0, 07/02, page 439 of 986 Tr CKIO Bank Precharge-sel Address Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 Tpc Row Row Row H/L c1 H/L c5 RD/ DQMn D31-D0 (read) c1 c2 c3 c4 c5 c6 c7 c8 CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM Connecting a 128-Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R Only): It is possible to connect 128-Mbit or 256-Mbit synchronous DRAMs with 64-bit bus width to the SH7750R. RAS down mode is also available using a 128 Mbytes of external memory space in area 2 or 3. Either eight 128-Mbit (4 M x 8 bit x 4 bank) DRAMs or four 256-Mbit (4 M x 8 bit x 4 bank) DRAMs can be connected. Figure 13.45 shows an example in which four 256-Mbit DRAMs are connected. Notes on Usage: * BCR1.DRAMTP2-DRAMTP0 = 011: Sets areas 2 and 3 as synchronous-DRAM-interface spaces. * MCR.SZ = 00: Sets the bus width of the synchronous DRAM to 64 bits. * MCR.AMX = 6: Selects the 128-Mbit or 256-Mbit address-multiplex setting for the synchronous DRAM. * In the auto-refresh operation, the REF command is issued twice in response to a single refresh request. Set RTCOR and bits CKS2-CKS0 so as to satisfy the refresh-interval rating of the synchronous DRAM which you are using. * When setting the mode register of the synchronous DRAM, set the address for area 2 first. Rev. 6.0, 07/02, page 440 of 986 * Control signals required in this connection are 5$6, &$6, RD/:5, &66, DQM0-DQM7, and CKE. &65 is not used. * Do not use partial-sharing mode. If you use this, correct operation is not guaranteed. SH7750R CKIO CKE CS3 RAS CASS RD/WR A17 A16 A15-A3 D63-D48 DQM7 DQM6 D47-D32 DQM5 DQM4 D31-D16 DQM3 DQM2 D15-D0 DQM1 DQM0 CLK CKE CS RAS CAS WE BANK1 BANK0 A12-A0 I/O15-I/O0 DQMU DQML CLK CKE CS RAS CAS WE BANK1 BANK0 A12-A0 I/O15-I/O0 DQMU DQML CLK CKE CS RAS CAS WE BANK1 BANK0 A12-A0 I/O15-I/O0 DQMU DQML CLK CKE CS RAS CAS WE BANK1 BANK0 A12-A0 I/O15-I/O0 DQMU DQML Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width (256 Mbits) 13.3.6 Burst ROM Interface Setting bits A0BST2-A0BST0, A5BST2-A5BST0, and A6BST2-A6BST0 in BCR1 to a nonzero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The timing for burst access to burst ROM is shown in figure 13.46. Two wait cycles are set. Basically, access is performed in the same way as for SRAM interface, but when the first cycle ends, only the address is changed before the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses can be set as 4, 8, 16, or 32 with bits A0BST2-A0BST0, A5BST2-A5BST0, or A6BST2- A6BST0. When 16-bit ROM is connected, 4, 8, or 16 can be set in the same way. When 32-bit ROM is connected, 4 or 8 can be set. 5'< pin sampling is always performed when one or more wait states are set. The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait specification is 0. The timing in this case is shown in figure 13.47. A write operation for the burst ROM interface is performed as if the SRAM interface is selected. Rev. 6.0, 07/02, page 441 of 986 In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. The bus is not released during this period. Figure 13.48 shows the timing when a burst ROM setting is made, and setup/hold is specified in WCR3. T1 CKIO A25-A5 TB2 TB1 TB2 TB1 TB2 TB1 T2 A4-A0 RD/ D63-D0 (read) DACKn (SA: IO memory) Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed. 2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.46 Burst ROM Basic Access Timing Rev. 6.0, 07/02, page 442 of 986 T1 CKIO A25-A5 Tw Tw TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2 A4-A0 RD/ D63-D0 (read) DACKn (SA: IO memory) Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed. 2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.47 Burst ROM Wait Access Timing Rev. 6.0, 07/02, page 443 of 986 TS1 CKIO A25-A5 A4-A0 T1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 T2 TH1 RD/ D63-D0 (read) DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.48 Burst ROM Wait Access Timing 13.3.7 PCMCIA Interface In the SH7750 Series, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA specification version 4.2 (PCMCIA2.1). Figure 13.49 shows an example of PCMCIA card connection to the SH7750 Series. To enable active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between the SH7750 Series' bus interface and the PCMCIA cards. As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications, the SH7750 Series supports only a little-endian mode PCMCIA interface. In the SH7750, the PCMCIA interface area can only be accessed when the MMU is used. The PCMCIA interface memory space can be set in page units and there is a choice of 8-bit common memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O space, 16-bit I/O space, or dynamic bus sizing, according to the accessed SA2 to SA0 bits. The setting for wait cycles during a bus access can also be made in MMU page units. When the TC bit to be accessed is cleared to 0, bits A5W2 to A5W0 in wait control register 2 (WCR2), and bits A5PCW1 and A5PCW0, A5TED2 to A5TED0, and A5TEH2 to A5TEH0 in the PCMCIA Rev. 6.0, 07/02, page 444 of 986 control register (PCR), are selected. When the TC bit to be accessed is set to 1, bits A6W2 to A6W0 in wait control register 2 (WCR2), and bits A6PCW1 and A6PCW0, A6TED2 to A6TED0, and A6TEH2 to A6TEH0 in the PCMCIA control register (PCR), are selected. For the method of setting bits SA2 to SA0 and bit TC for the page to be accessed, see section 3, Memory Management Unit (MMU). In the SH7750S and SH7750R, the PCMCIA interface can be accessed even when the MMU is not used. When the MMU is off (MMUCR.AT=0), access is always performed by means of bits SA2 to SA0 and bit TC in the page table entry assistance register (PTEA). When the MMU is on (MMUCR.AT=1), the situation is the same as for the SH7750. In the SH7750 Series, access to a PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. SA2 0 SA1 0 SA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Reserved (Setting prohibited) Dynamic I/O bus sizing 8-bit I/O space 16-bit I/O space 8-bit common memory 16-bit common memory 8-bit attribute memory 16-bit attribute memory AnPCW1-AnPCW0 specify the number of wait states to be inserted in a low-speed bus cycle; a value of 0, 15, 30, or 50 can be set, and this value is added to the number of wait states for insertion specified by WCR2. AnTED2-AnTED0 can be set to a value from 0 to 15, enabling the address, &6, &(5$, &(5%, and 5(* setup times with respect to the 5' and :(4 signals to be secured. AnTEH2-AnTEH0 can also be set to a value from 0 to 15, enabling the address, &6, &(5$, &(5%, and 5(* write data hold times with respect to the 5' and :(4 signals to be secured. Wait cycles between cycles are set with bits A5IW2-A5IW0 and A6IW2-A6IW0 in wait control register 1 (WCR1). The inter-cycle write cycles selected depend only on the area accessed (area 5 or 6): when area 5 is accessed, bits A5IW2-A5IW0 are selected, and when area 6 is accessed, bits A6IW2-A6IW0 are selected. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. The bus is not released during this period. Rev. 6.0, 07/02, page 445 of 986 Table 13.18 Relationship between Address and CE when Using PCMCIA Interface Bus Width (Bits) 8 Read/ Write Read Access Size Odd/ 1 (Bits)* Even 8 Even Odd 16 Even Even Odd Write 8 Even Odd 16 Even Even Odd 16 Read 8 Even Odd 16 Even Odd Write 8 Even Odd 16 Even Odd IOIS16 Access CE2 Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care -- -- First 1 1 1 CE1 0 0 0 0 -- 0 0 0 0 -- 0 1 0 -- 0 1 0 -- A0 0 1 0 1 -- 0 1 0 1 -- 0 1 0 -- 0 1 0 -- D15-D8 Invalid Invalid Invalid Invalid -- Invalid Invalid Invalid Invalid -- Invalid Read data D7-D0 Read data Read data Lower read data Upper read data -- Write data Write data Lower write data Upper write data -- Read data Invalid Second 1 -- -- -- First -- 1 1 1 Second 1 -- -- -- -- -- -- -- -- -- -- 1 0 0 -- 1 0 0 -- Upper read data Lower read data -- Invalid Write data -- Write data Invalid Upper write data Lower write data -- -- Rev. 6.0, 07/02, page 446 of 986 Table 13.18 Relationship between Address and CE when Using PCMCIA Interface (cont) Bus Width (Bits) Read/ Write Access Size Odd/ 1 (Bits)* Even 8 Even Odd 16 Even Odd Write 8 Even Odd 16 Even Odd Read 8 Even Odd Odd 16 Even Even Odd Write 8 Even Odd Odd 16 Even Even Odd IOIS16 Access CE2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- First 1 0 0 -- 1 0 0 -- 1 0 CE1 0 1 0 -- 0 1 0 -- 0 1 0 0 0 -- 0 1 0 0 0 -- A0 0 1 0 -- 0 1 0 -- 0 1 1 0 1 -- 0 1 1 0 1 -- D15-D8 Invalid Read data D7-D0 Read data Invalid Dynamic Read bus 2 sizing* Upper read data Lower read data -- Invalid Write data -- Write data Invalid Upper write data Lower write data -- Invalid Ignored Invalid Invalid Invalid -- Invalid Invalid Invalid -- Read data Invalid Read data Lower read data Upper read data -- Write data Write data Write data Second 1 First 0 Second 1 -- -- First -- 1 0 Second 1 First 0 Upper write data Lower write data Invalid -- Upper write data -- Second 1 -- -- Notes: *1 In 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address incrementing performed automatically according to the bus width, until the transfer data size is reached. *2 PCMCIA I/O card interface only Rev. 6.0, 07/02, page 447 of 986 A25-A0 D15-D0 RD/ /( /( ) ) DIR D15-D8 D7-D0 A25-A0 D15-D0 PC card (memory I/O) DIR SH7750 Series / ( ( ) ) ( Card detection circuit Output Port D7-D0 ) CD1, CD2 A25-A0 D15-D0 DIR D15-D8 PC card (memory I/O) DIR / Card detection circuit CD1, CD2 Figure 13.49 Example of PCMCIA Interface Rev. 6.0, 07/02, page 448 of 986 Memory Card Interface Basic Timing: Figure 13.50 shows the basic timing for the PCMCIA IC memory card interface, and figure 13.51 shows the PCMCIA memory card interface wait timing. Tpcm1 Tpcm2 CKIO A25-A0 RD/ (read) D15-D0 (read) (write) D15-D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.50 Basic Timing for PCMCIA Memory Card Interface Rev. 6.0, 07/02, page 449 of 986 Tpcm0 CKIO Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w A25-A0 RD/ * (read) D15-D0 (read) (write) D15-D0 (write) DACKn (DA) Notes: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. * SH7750S, SH7750R only Figure 13.51 Wait Timing for PCMCIA Memory Card Interface Rev. 6.0, 07/02, page 450 of 986 Common memory (64 MB) Access by CS5 wait controller Virtual address space Physical I/O addresses 1 kB page IO 1 IO 1 IO 2 Virtual address space Common memory 1 Card 1 on CS5 Common memory 2 Attribute memory I/O space 1 I/O space 2 Access by CS6 wait controller Attribute memory (64 MB) . . . IO 2 1 kB page Different virtual pages mapped to the same physical page Example of I/O spaces with different cycle times (less than 1 kB) I/O space (64 MB) Card 2 on CS6 . . . The page size can be 1 kB, 4 kB, 64 kB, or 1 MB. Example of PCMCIA interface mapping Figure 13.52 PCMCIA Space Allocation I/O Card Interface Timing: Figures 13.53 and 13.54 show the timing for the PCMCIA I/O card interface. When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic sizing of the I/O bus width is possible using the ,2,649 pin. When a 16-bit bus width is set, if the ,2,649 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits. Dynamic bus sizing is also performed in the case of byte-size access to address 2n + 1. Figure 13.55 shows the basic timing for dynamic bus sizing. Rev. 6.0, 07/02, page 451 of 986 Tpci1 Tpci2 CKIO A25-A0 RD/ (read) D15-D0 (read) (write) D15-D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.53 Basic Timing for PCMCIA I/O Card Interface Rev. 6.0, 07/02, page 452 of 986 Tpci0 CKIO Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w A25-A0 RD/ (read) D15-D0 (read) (write) D15-D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.54 Wait Timing for PCMCIA I/O Card Interface Rev. 6.0, 07/02, page 453 of 986 Tpci0 CKIO Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w A25-A1 A0 ( ) RD/ ( (read) ) D15-D0 (read) ( (write) ) D15-D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.55 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev. 6.0, 07/02, page 454 of 986 13.3.8 MPX Interface If the MD6 pin is set to 0 in a power-on reset by the 5(6(7 pin, the MPX interface for normal memory is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in BCR1 and the MEMMODE, A4MPX, and AIMPX bits in BCR3. The MPX interface offers a multiplexed address/data type bus protocol, and permits easy connection to an external memory controller chip that uses a single 32-bit multiplexed address/data bus. A bus cycle consists of an address phase and a data phase. In the address phase, the address information is output to D25-D0, and the access size to D63-D61 and D31-D29*. The %6 signal which indicates the address phase is asserted for one cycle. The &6Q signal is asserted at the rise of Tm1, and negated after the last data transfer in the data phase. Therefore, a negate period does not exist for access with the minimum pitch. The )5$0( signal is asserted at the rise of Tm1, and negated when the cycle of the last data transfer starts in the data phase. Therefore, in an external device supporting the MPX interface, the address information and access size output in the address phase must be saved in the external device memory, and data corresponding to the data phase must be input or output. For details of access sizes and data alignment, see section 13.3.1, Endian/Access Size and Data Alignment. The address pins output at A25-A0 are undefined. 32-byte transfer performed consecutively for a total of 32 bytes according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. When the access size is larger than the data bus width, as in this case, burst access is generated, with the address output once, followed by multiple data cycles. The bus is not released during this period. Note: * SH7750R only. D63 0 D62 0 D61 0 1 1 0 1 1 X: Don't care X X Access Size Byte Word Longword Quadword 32-byte burst Rev. 6.0, 07/02, page 455 of 986 SH7750 Series CKIO MPX device CLK RD/ D63-D0 I/O63-I/O0 Figure 13.56 Example of 64-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 or 64 bits should be specified in BCR2. For wait control, waits specified by WCR2 and wait insertion by means of the 5'< pin can be used. In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to 0. Rev. 6.0, 07/02, page 456 of 986 Tm1 CKIO Tmd1w Tmd1 / D63-D0 A D0 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.57 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits) Rev. 6.0, 07/02, page 457 of 986 Tm1 CKIO Tmd1w Tmd1w Tmd1 / D63-D0 A D0 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.58 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) Rev. 6.0, 07/02, page 458 of 986 Tm1 CKIO Tmd1 / D63-D0 A D0 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.59 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits) Rev. 6.0, 07/02, page 459 of 986 Tm1 CKIO Tmd1w Tmd1w Tmd1 / D63-D0 A D0 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.60 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) Rev. 6.0, 07/02, page 460 of 986 Tm1 CKIO / D63-D0 A Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 D0 D1 D2 D3 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.61 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 461 of 986 Tm1 CKIO / D63-D0 A Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 D0 D1 D2 D3 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.62 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 462 of 986 Tm1 CKIO / D63-D0 A Tmd1 Tmd2 Tmd3 Tmd4 D0 D1 D2 D3 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.63 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 463 of 986 Tm1 CKIO / D63-D0 A Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 D0 D1 D2 D3 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.64 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 464 of 986 Tm1 CKIO Tmd1w Tmd1 Tmd2 / D31-D0 A D0 D1 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.65 MPX Interface Timing 1 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 6.0, 07/02, page 465 of 986 Tm1 CKIO Tmd1w Tmd1w Tmd1 Tmd2 / D31-D0 A D0 D1 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.66 MPX Interface Timing 2 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 6.0, 07/02, page 466 of 986 Tm1 CKIO Tmd1 Tmd2 / D31-D0 A D0 D1 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.67 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 6.0, 07/02, page 467 of 986 Tm1 CKIO Tmd1w Tmd1w Tmd1 Tmd2 / D31-D0 A D0 D1 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.68 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 6.0, 07/02, page 468 of 986 Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 CKIO / A D0 D1 D2 D3 D4 D5 D6 D7 D31-D0 RD/ DACKn (DA) Figure 13.69 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 469 of 986 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd8w Tmd8 D6 D7 D31-D0 CKIO Figure 13.70 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 470 of 986 DACKn (DA) RD/ Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd7 Tmd3 Tmd2w Tmd2 Tmd1w Tmd1 Tm1 / A D0 D1 D2 Tmd8 Tmd7 D6 D7 Figure 13.71 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 471 of 986 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd6 Tmd5 Tmd4 Tmd3 Tmd2 Tmd1 Tm1 D31-D0 A D0 D1 D2 D3 D4 D5 DACKn (DA) CKIO / RD/ Tmd8 Tmd8w D6 D7 Figure 13.72 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 472 of 986 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd7 Tmd2 Tmd3 Tmd1 Tmd2w Tmd1w Tm1 D31-D0 A D0 D1 D2 DACKn (DA) CKIO RD/ / 13.3.9 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte select strobe (:(Q) in both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has an upper byte select strobe and lower byte select strobe function such as UB and LB. Areas 1 and 4 can be designated as byte control SRAM interface. However, when these areas are set to MPX mode, MPX mode has priority. The byte control SRAM interface write timing is the same as for the normal SRAM interface. In read operations, the :(Q pin timing is different. In a read access, only the :( signal for the byte being read is asserted. Assertion is synchronized with the fall of the CKIO clock, as for the :( signal, while negation is synchronized with the rise of the CKIO clock, using the same timing as the 5' signal. In 32-byte transfer such as a cache fill or copy-back, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. The bus is not released during this period. Figure 13.73 shows an example of byte control SRAM connection to the SH7750, and figures 13.74 to 13.76 show examples of byte control SRAM read cycle. Rev. 6.0, 07/02, page 473 of 986 SH7750 Series A18-A3 RD/ D63-D48 64k x 16-bit SRAM A15-A0 I/O15-I/O0 A15-A0 D47-D32 I/O15-I/O0 A15-A0 D31-D16 I/O15-I/O0 A15-A0 D15-D0 I/O15-I/O0 Figure 13.73 Example of 64-Bit Data Width Byte Control SRAM Rev. 6.0, 07/02, page 474 of 986 T1 CKIO T2 A25-A0 RD/ D63-D0 (read) DACKn (SA: IO memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.74 Byte Control SRAM Basic Read Cycle (No Wait) Rev. 6.0, 07/02, page 475 of 986 T1 CKIO Tw T2 A25-A0 RD/ D63-D0 (read) DACKn (SA: IO memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.75 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev. 6.0, 07/02, page 476 of 986 T1 CKIO Tw Twe T2 A25-A0 RD/ D63-D0 (read) DACKn (SA: IO memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev. 6.0, 07/02, page 477 of 986 13.3.10 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and so resulting in lower reliability or incorrect operation. To avoid this problem, a data collision prevention feature has been provided. This memorizes the preceding access area and the kind of read/write, and if there is a possibility of a bus collision when the next access is started, inserts a wait cycle before the access cycle to prevent a data collision. Wait cycle insertion consists of inserting idle cycles between access cycles, as shown in section 13.2.5, Wait Control Register (WCR1). When the SH7750 Series performs consecutive write cycles, the data transfer direction is fixed (from the SH7750 Series to other memory) and there is no problem. With read accesses to the same area, also, in principle data is output from the same data buffer, and wait cycle insertion is not performed. If there is originally space between accesses, according to the setting of bits AnIW2-AnIW0 (n = 0 to 6) in WCR1, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. When bus arbitration is performed, the bus is released after waits are inserted between cycles. In single address mode DMA transfer, when data transfer is performed from an I/O device to memory the data on the bus is determined by the speed of the I/O device. With a low-speed I/O device, an inter-cycle idle wait equivalent to the output buffer turn-off time must be inserted. Even with high-speed memory, when DMA transfer is considered, it may be necessary to insert an intercycle wait to adjust to the speed of a low-speed device, preventing the memory from being used at full speed. Bits DMAIW2-DMAIW0 in wait control register 1 (WCR1) allow an inter-cycle wait setting to be made when transferring data from an I/O device to memory using single address mode DMA transfer. From 0 to 15 waits can be inserted. The number of waits specified by DMAIW2- DMAIW0 are inserted in single address DMA transfers to all areas. In dual address mode DMA transfer, the normal inter-cycle wait specified by AnIW2-AnIW0 (n = 0 to 6) is inserted. Rev. 6.0, 07/02, page 478 of 986 T1 T2 Twait T1 T2 Twait T1 T2 A25-A0 RD/ D31-D0 Area m space read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 13.77 Waits between Access Cycles Rev. 6.0, 07/02, page 479 of 986 13.3.11 Bus Arbitration The SH7750 Series is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode. In master mode the bus is held on a constant basis, and is released to another device in response to a bus request. In slave mode the bus is not held on a constant basis; a bus request is issued each time an external bus cycle occurs, and the bus is released again at the end of the access. In partialsharing master mode, only area 2 is shared with external devices; slave mode is in effect for area 2, while for other spaces, bus arbitration is not performed and the bus is held constantly. The area in the master mode chip to which area 2 in the partial-sharing master mode chip is allocated is determined by an external circuit. Master mode and slave mode can be specified by the external mode pins. Partial-sharing master mode is entered from master mode by means of a software setting. See Appendix C, Mode Pin Settings, for the external mode pin settings. In master mode and slave mode, the bus goes to the high-impedance state when not being held. In partial-sharing master mode, the bus is constantly driven, and therefore an external buffer is necessary for connection to the master bus. In master mode, it is possible to connect an external device that issues bus requests instead of a slave mode chip. In the following description, an external device that issues bus requests is also referred to as a slave. The SH7750 Series has two internal bus masters: the CPU and the DMAC. When synchronous DRAM or DRAM is connected and refresh control is performed, refresh requests constitute a third bus master. In addition to these are bus requests from external devices in master mode. If requests occur simultaneously, priority is given, in high-to-low order, to a bus request from an external device, a refresh request, the DMAC, and the CPU. To prevent incorrect operation of connected devices when the bus is transferred between master and slave, all bus control signals are negated before the bus is released. When mastership of the bus is received, also, bus control signals begin driving the bus from the negated state. Since signals are driven to the same value by the master and slave exchanging the bus, output buffer collisions can be avoided. Bus transfer is executed between bus cycles. When the bus release request signal (%5(4) is asserted, the SH7750 Series releases the bus as soon as the currently executing bus cycle ends, and outputs the bus use permission signal (%$&.). However, bus release is not performed during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is not performed between read and write cycles during execution of a TAS instruction, or between read and write cycles when DMAC dual address transfer is executed. When %5(4 is Rev. 6.0, 07/02, page 480 of 986 negated, %$&. is negated and use of the bus is resumed. See Appendix E, Pin Functions, for the pin states when the bus is released. When a refresh request is generated, the SH7750 Series performs a refresh operation as soon as the currently executing bus cycle ends. However, refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. Refresh operations are also deferred in the bus-released state. If the synchronous DRAM interface is set to the RAS down mode the PALL command is issued before a refresh cycle occurs or before the bus is released by bus arbitration. As the CPU in the SH7750 Series is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside the SH7750 Series. When writing from the CPU, an external write cycle is generated when write-through has been set for the cache in the SH7750 Series, or when an access is made to a cache-off area. There is consequently a delay until the bus is returned. When the SH7750 Series wants to take back the bus in response to an internal memory refresh request, it negates %$&.. On receiving the %$&. negation, the device that asserted the external bus release request negates %5(4 to release the bus. The bus is thereby returned to the SH7750 Series, which then carries out the necessary processing. Rev. 6.0, 07/02, page 481 of 986 CKIO Asserted for at least 2 cycles Negated within 2 cycles A25-A0 HiZ HiZ RD/ HiZ HiZ HiZ D63-D0 (write) HiZ HiZ HiZ Master mode device access Must be asserted for at least 2 cycles Must be negated within 2 cycles / / HiZ HiZ RD/ HiZ HiZ HiZ D63-D0 (write) HiZ HiZ Slave mode device access HiZ HiZ HiZ HiZ HiZ HiZ HiZ A25-A0 Master access Slave access Master access Figure 13.78 Arbitration Sequence Rev. 6.0, 07/02, page 482 of 986 13.3.12 Master Mode The master mode processor holds the bus itself unless it receives a bus request. On receiving an assertion (low level) of the bus request signal (%5(4) from off-chip, the master mode processor releases the bus and asserts (drives low) the bus use permission signal (%$&.) as soon as the currently executing bus cycle ends. If a bus release request due to a refresh request has not been issued, on receiving the %5(4 negation (high level) indicating that the slave has released the bus, the processor negates (drives high) the %$&. signal and resumes use of the bus. If a bus request is issued due to a memory refresh request in the bus-released state, the processor negates the bus use permission signal (%$&.), and on receiving the %5(4 negation indicating that the slave has released the bus, resumes use of the bus. When the bus is released, all bus interface related output signals and input/output signals go to the high-impedance state, except for the synchronous DRAM interface CKE signal and bus arbitration %$&. signal, and DACK0 and DACK1 which control DMA transfers. With DRAM, the bus is released after precharging is completed. With synchronous DRAM, also, a precharge command is issued for the active bank and the bus is released after precharging is completed. The actual bus release sequence is as follows. First, the bus use permission signal is asserted in synchronization with the rising edge of the clock. The address bus and data bus go to the high-impedance state in synchronization with the next rising edge of the clock after this %$&. assertion. At the same time, the bus control signals (%6, &6Q, 5$64, 5$65, :(Q, 5', RD/:5, 5'5, RD/:55, &(5$, and &(5%) go to the highimpedance state. These bus control signals are negated no later than one cycle before going to high-impedance. Bus request signal sampling is performed on the rising edge of the clock. The sequence for re-acquiring the bus from the slave is as follows. As soon as %5(4 negation is detected on the rising edge of the clock, %$&. is negated and bus control signal driving is started. Driving of the address bus and data bus starts at the next rising edge of an in-phase clock. The bus control signals are asserted and the bus cycle is actually started, at the earliest, at the clock rising edge at which the address and data signals are driven. In order to reacquire the bus and start execution of a refresh operation or bus access, the %5(4 signal must be negated for at least two cycles. If a refresh request is generated when %$&. has been asserted and the bus has been released, the %$&. signal is negated even while the %5(4 signal is asserted to request the slave to relinquish the bus. When the SH7750 Series is used in master mode, consecutive bus accesses may be attempted to reduce the overhead due to arbitration in the case of a slave designed independently Rev. 6.0, 07/02, page 483 of 986 by the user. When connecting a slave for which the total duration of consecutive accesses exceeds the refresh cycle, the design should provide for the bus to be released as soon as possible after negation of the %$&. signal is detected. 13.3.13 Slave Mode In slave mode, the bus is normally in the released state, and an external device cannot be accessed unless the bus is acquired through execution of the bus arbitration sequence. In a reset, also, the bus-released state is established and the bus arbitration sequence is started from the reset vector fetch. To acquire the bus, the slave device asserts (drives low) the %65(4 signal in synchronization with the rising edge of the clock. The bus use permission %6$&. signal is sampled for assertion (low level) in synchronization with the rising edge of the clock. When %6$&. assertion is detected, the bus control signals and address bus are immediately driven at the negated level. The bus cycle is started at the next rising edge of the clock. The last signal negated at the end of the access cycle is synchronized with the rising edge of the clock. When the bus cycle ends, the %65(4 signal is negated and the release of the bus is reported to the master. On the next rising edge of the clock, the control signals are set to high-impedance. In order for the slave mode processor to begin access, the %6$&. signal must be asserted for at least two cycles. For a slave access cycle in DRAM or synchronous DRAM, the bus is released on completion of precharging, as in the case of the master. Refresh control is left to the master mode device, and any refresh control settings made in slave mode are ignored. Do not use DRAM/synchronous DRAM RAS down mode in slave mode. Synchronous DRAM mode register settings should be made by the master mode device. Do not use the DMAC's DDT mode in slave mode. Rev. 6.0, 07/02, page 484 of 986 13.3.14 Partial-Sharing Master Mode In partial-sharing master mode, area 2 only is shared with other devices, and other areas can be accessed at all times. Partial-sharing master mode can be set by setting master mode with the external mode pins, and setting the PSHR bit to 1 in BCR1 in the initialization procedure in a power-on reset. In a manual reset the bus state controller setting register values are retained, and so need not be set again. Partial-sharing master mode is designed for use in conjunction with a master mode chip. The partial-sharing master can access a device on the master side via area 2, but the master cannot access a device on the partial-sharing master side. An address and control signal buffer and a data buffer must be located between the partial-sharing master and the master, and controlled by a buffer control circuit. The partial-sharing master mode processor uses the following procedure to access area 2. It asserts the %65(4 signal on the rising edge of the clock, and issues a bus request to the master. It samples %6$&. on each rising edge of the clock, and on receiving %6$&. assertion, starts the access cycle on the next rising edge of the clock. At the end of the access, it negates %65(4 on the rising edge of the clock. Buffer control in an access to an area 2 device by the partial-sharing master is carried out by referencing the &65 signal or %65(4 and %6$&. signals on the partialsharing master side. Permission to use the bus is reported by the %6$&. line connected to the partial-sharing master, but the master may also negate the %6$&. signal even while the bus is being used, if it needs the bus urgently in order to service a refresh, for example. Consequently, the partial-sharing master has to monitor the %65(4 signal to see whether it can continue to use the bus after detecting %6$&. assertion. In the case of the address buffer, after the address buffer is turned on when %6$&. assertion is detected, the buffer is kept on until %65(4 is negated, at which point it is turned off. If the turning-off of the buffer used is late, resulting in a collision with the start of an access cycle on the master side, the %65(4 signal output from the partial-sharing master must be routed through a delay circuit as part of the buffer control circuit, and input to the master %5(4 signal. In order for a partial-sharing master mode processor to begin area 2 access, the %6$&. signal must be asserted for at least two cycles. When the bus is released after area 2 has been accessed in partial-sharing master mode, if area 2 is synchronous DRAM, there is a wait of the period required for auto-precharge before bus release is performed. In partial-sharing master mode, refreshing is not performed for area 2 (refresh requests are ignored). Do not use DRAM/synchronous DRAM RAS down mode in partial-sharing master mode. Rev. 6.0, 07/02, page 485 of 986 Area 2 synchronous DRAM mode register settings should be made by the master mode device. Set partial-sharing master mode (by setting the PSHR bit to 1 in BCR1) after completion of the area 3 synchronous DRAM mode register settings. In partial-sharing master mode, DMA transfer should not be performed on area 2, and the DMAC's DDT mode should not be used. 13.3.15 Cooperation between Master and Slave To enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. Before DRAM or synchronous DRAM is used, initialization operations must be carried out. Responsibility must also be assigned when a standby operation is performed to implement the power-down state. The design of the SH7750 Series provides for all control, including initialization, refreshing, and standby control, to be carried out by the master mode device. In a dual-processor configuration using direct master/slave connection, all processing except direct access to memory is handled by the master. In a combination of master mode and partial-sharing master mode, the partial-sharing master mode processor performs initialization, refreshing, and standby control for the areas connected to it, with the exception of area 2, while the master performs initialization of the memory connected to it. If the SH7750 Series is specified as the master in a power-on reset, it will not accept bus requests from the slave until the %5(4 enable bit (BCR1.BREQEN) is set to 1. To ensure that the slave processor does not access memory requiring initialization before use, such as DRAM and synchronous DRAM, until initialization is completed, write 1 to the %5(4 enable bit after initialization ends. Before setting self-refresh mode in standby mode, etc., write 0 to the %5(4 enable bit to invalidate the %5(4 signal from the slave. Write 1 to the %5(4 enable bit only after the master has performed the necessary processing (refresh settings, etc.) for exiting self-refresh mode. Rev. 6.0, 07/02, page 486 of 986 13.3.16 Notes on Usage Refresh: Auto refresh operations stop when a transition is made to standby mode, hardware standby mode or deep-sleep mode. If the memory system requires refresh operations, set the memory in the self-refresh state prior to making the transition to standby mode, hardware standby mode or deep-sleep mode. Bus Arbitration: On transition to standby mode or deep-sleep mode, the processor in master mode does not release bus privileges. In systems performing bus arbitration, make the transition to standby mode or deep-sleep mode only after setting the bus privilege release enable bit (BCR1.BREQEN) to 0 for the processor in master mode. If the bus privilege release enable bit remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or deep-sleep mode. Synchronous DRAM Mode Register Setting (SH7750, SH7750S Only): The following conditions must be satisfied when setting the synchronous DRAM mode register. * The DMAC must not be activated until synchronous DRAM mode register setting is 1 completed.* * Register setting for the on-chip peripheral modules* must not be performed until synchronous 3 DRAM mode register setting is completed.* 2 Notes: *1 If a conflict occurs between synchronous DRAM mode register setting and memory access using the DMAC, neither operation can be guaranteed. *2 This applies to the following on-chip peripheral modules: CPG, RTC, INTC, TMU, SCI, SCIF, and H-UDI. *3 If synchronous DRAM mode register setting is performed immediately following write 2 access to the on-chip peripheral modules* , the values written to the on-chip peripheral modules cannot be guaranteed. Rev. 6.0, 07/02, page 487 of 986 Rev. 6.0, 07/02, page 488 of 986 Section 14 Direct Memory Access Controller (DMAC) 14.1 Overview The SH7750 and SH7750S include an on-chip four-channel direct memory access controller (DMAC). The SH7750R includes an on-chip eight-channel DMAC. The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (TMU, SCI, SCIF), external memories, memory-mapped external devices, and on-chip peripheral modules (except the DMAC, BSC, and UBC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of the chip. When using the SH7750R, see the following sections: Section 14.6, Configuration of DMAC (SH7750R); Section 14.7, Register Descriptions (SH7750R); Section 14.8, Operation (SH7750R). 14.1.1 Features The DMAC has the following features. * Four channels (SH7750/SH7750S), eight channels (SH7750R) * Physical address space * Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length * Maximum of 16 M (16,777,216) transfers * Choice of single or dual address mode Single address mode: Either the transfer source or the transfer destination (external device) is accessed by a DACK signal while the other is accessed by address. One data transfer is completed in one bus cycle. Dual address mode: Both the transfer source and transfer destination are accessed by address. Values set in DMAC internal registers indicate the accessed address for both the transfer source and the transfer destination. Two bus cycles are required for one data transfer. * Choice of bus mode: Cycle steal mode or burst mode * Two types of DMAC channel priority ranking: Fixed priority mode: Channel priorities are permanently fixed. Round robin mode: Sets the lowest priority for the channel for which an execution request was last accepted. * An interrupt request can be sent to the CPU on completion of the specified number of transfers. Rev. 6.0, 07/02, page 489 of 986 * Transfer requests: The following three DMAC transfer activation requests are supported. External request (1) Normal DMA mode From two '5(4 pins. Either low level detection or falling edge detection can be specified. External requests can be accepted on channels 0 and 1 only. (2) On-demand data transfer mode (DDT mode) In this mode of the SH7750 and SH7750S, interfacing between an external device and the DMAC is performed using the '%5(4, %$9/, 75, 7'$&., ID [1:0], and D [63:0] pins. External requests can be accepted on all four channels. In the SH7750R, the '%5(4, %$9/, 75, 7'$&., ID [2:0], and D [63:0] pins are used as the interface between an external device and the DMAC. External requests can be accepted on any of the eight channels. For channel 0, data transfer can be carried out with the transfer mode, number of transfers, transfer address (single only), etc., specified by the external device. Although channel 0 has no request queue, there are four request queues for each of the other channels: i.e., channels 1 to 3 in the SH7750 or SH7750S, and channels 1 to 7 in the SH7750R. In the SH7750R, request queues can be cleared on a channel-by-channel basis in DDT mode in either of the following two ways. * Clearing a request queue by DTR format The request queues of the relevant channel are cleared when it receives DTR.SZ = 110, DTR.ID = 00, DTR.MD = 11, and DTR.COUNT [7:4]* = [1-8]. Using software to clear the request queue The request queues of the relevant channel are cleared by writing a 1 to the CHCRn.QCL bit (request-queue clear bit) of each channel. * Note: * DTR.COUNT [7:4] (DTR [55:52]): Sets the port as not used. Requests from on-chip peripheral modules Transfer requests from the SCI, SCIF, and TMU. These can be accepted on all channels. Auto-request The transfer request is generated automatically within the DMAC. * Channel functions: Transfer modes that can be set are different for each channel. Normal DMA mode * * * * * * Channel 0: Single or dual address mode. External requests are accepted. Channel 1: Single or dual address mode. External requests are accepted. Channel 2: Dual address mode only. Channel 3: Dual address mode only. Channel 4 (SH7750R only): Dual address mode only. Channel 5 (SH7750R only): Dual address mode only. Rev. 6.0, 07/02, page 490 of 986 * * Channel 6 (SH7750R only): Dual address mode only. Channel 7 (SH7750R only): Dual address mode only. DDT mode channel function * Channel 0: Single address mode. External requests are accepted Dual address mode (SH7750S, SH7750R) * * * * * * * Channel 1: Single or dual address mode. External requests are accepted. Channel 2: Single or dual address mode. External requests are accepted. Channel 3: Single or dual address mode. External requests are accepted. Channel 4 (SH7750R only): Single or dual address mode. External requests are accepted. Channel 5 (SH7750R only): Single or dual address mode. External requests are accepted. Channel 6 (SH7750R only): Single or dual address mode. External requests are accepted. Channel 7 (SH7750R only): Single or dual address mode. External requests are accepted. Rev. 6.0, 07/02, page 491 of 986 14.1.2 Block Diagram (SH7750, SH7750S) Figure 14.1 shows a block diagram of the DMAC. DMAC module Count control Register control SARn DARn DMATCRn CHCRn DMAOR Request priority control Peripheral bus Internal bus On-chip peripheral module Activation control TMU SCI, SCIF DACK0, DACK1 DRAK0, DRAK1 Bus interface External address/on-chip peripheral module address 4 Request SAR0, DAR0, DMATCR0, CHCR0 only DDT module DTR command buffer , D[63:0] ID[1:0] External bus 32B data buffer Bus state controller CH0 CH1 CH2 CH3 DBREQ DDTMODE BAVL DDTD id[1:0] tdack Request controller 48 bits DMAC operation register DMAC source address register DARn: DMAC destination address register DMATCRn: DMAC transfer count register CHCRn: DMAC channel control register (n: 0 to 3) DMAOR: SARn: Figure 14.1 Block Diagram of DMAC Rev. 6.0, 07/02, page 492 of 986 14.1.3 Pin Configuration (SH7750, SH7750S) Tables 14.1 and 14.2 show the DMAC pins. Table 14.1 DMAC Pins Channel 0 Pin Name DMA transfer request '5(4 acceptance confirmation Abbreviation '5(43 DRAK0 I/O Input Output Function DMA transfer request input from external device to channel 0 Acceptance of request for DMA transfer from channel 0 to external device Notification to external device of start of execution DMA transfer end notification 1 DMA transfer request '5(4 acceptance confirmation DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device DMA transfer request input from external device to channel 1 Acceptance of request for DMA transfer from channel 1 to external device Notification to external device of start of execution DMA transfer end notification DACK1 Output Strobe output to external device of DMA transfer request from channel 1 to external device '5(44 DRAK1 Input Output Rev. 6.0, 07/02, page 493 of 986 Table 14.2 DMAC Pins in DDT Mode Pin Name Data bus request Data bus available Abbreviation '%5(4 ('5(43) %$9/ (DRAK0) 75 ('5(44) I/O Input Output Function Data bus release request from external device for DTR format input Data bus release notification Data bus can be used 2 cycles after %$9/ is asserted Input If asserted 2 cycles after %$9/ assertion, DTR format is sent Only 75 asserted: DMA request '%5(4 and 75 asserted simultaneously: Direct request to channel 2 DMAC strobe Channel number notification 7'$&. (DACK0) ID [1:0] (DRAK1, DACK1) Output Output Reply strobe signal for external device from DMAC Notification of channel number to external device at same time as 7'$&. output (ID [1] = DRAK1, ID [0] = DACK1) Transfer request signal 14.1.4 Register Configuration (SH7750, SH7750S) Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers are allocated to each channel, and an additional control register is shared by all four channels. Table 14.3 DMAC Registers Channel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 Abbreviation SAR0 DAR0 Read/ Write R/W* R/W* 2 Area 7 Initial Value P4 Address Address Undefined Undefined Undefined Access Size H'FFA00000 H'1FA00000 32 H'FFA00004 H'1FA00004 32 H'FFA00008 H'1FA00008 32 2 DMATCR0 R/W* CHCR0 2 12 R/W* * H'00000000 H'FFA0000C H'1FA0000C 32 Rev. 6.0, 07/02, page 494 of 986 Table 14.3 DMAC Registers (cont) Channel Name 1 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 Com- DMA operation mon register Abbreviation SAR1 DAR1 Read/ Write R/W R/W Area 7 Initial Value P4 Address Address Undefined Undefined Undefined 1 Access Size H'FFA00010 H'1FA00010 32 H'FFA00014 H'1FA00014 32 H'FFA00018 H'1FA00018 32 DMATCR1 R/W CHCR1 SAR2 DAR2 R/W* R/W R/W H'00000000 H'FFA0001C H'1FA0001C 32 Undefined Undefined Undefined H'FFA00020 H'1FA00020 32 H'FFA00024 H'1FA00024 32 H'FFA00028 H'1FA00028 32 DMATCR2 R/W CHCR2 SAR3 DAR3 R/W* R/W R/W 1 H'00000000 H'FFA0002C H'1FA0002C 32 Undefined Undefined Undefined H'FFA00030 H'1FA00030 32 H'FFA00034 H'1FA00034 32 H'FFA00038 H'1FA00038 32 DMATCR3 R/W CHCR3 DMAOR R/W* R/W* 1 H'00000000 H'FFA0003C H'1FA0003C 32 H'00000000 H'FFA00040 H'1FA00040 32 1 Notes: Longword access should be used for all control registers. If a different access width is used, reads will return all 0s and writes will not be possible. *1 Bit 1 of CHCR0-CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after being read as 1, to clear the flags. *2 In the SH7750, writes from the CPU are masked in DDT mode, while writes from external I/O devices using the DTR format are possible. In the SH7750S, writes from the CPU and writes from external I/O devices using the DTR format are possible In DDT mode. Rev. 6.0, 07/02, page 495 of 986 14.2 14.2.1 Register Descriptions (SH7750, SH7750S) DMA Source Address Registers 0-3 (SAR0-SAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: -- R/W 23 -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 0 ********************************************* Initial value: R/W: -- R/W ********************************************* ********************************************* -- R/W DMA source address registers 0-3 (SAR0-SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. These registers have a counter feedback function, and during a DMA transfer they indicate the next source address. In single address mode, the SAR value is ignored when an external device with DACK has been specified as the transfer source. Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will be detected and the DMAC will halt. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode and deep sleep mode. When transfer is performed from memory to an external device with DACK in DDT mode, DTR format [31:0] is set in SAR0 [31:0]. For details, see Data Transfer Request Format in section 14.5.2. In the SH7750, writes from the CPU are masked in DDT mode, while writes from external I/O devices using the DTR format are possible. In the SH7750S, writes from the CPU and writes from external I/O devices using the DTR format are possible In DDT mode. Rev. 6.0, 07/02, page 496 of 986 14.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: -- R/W 23 -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 0 ********************************************* Initial value: R/W: -- R/W ********************************************* ********************************************* -- R/W DMA destination address registers 0-3 (DAR0-DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers have a counter feedback function, and during a DMA transfer they indicate the next destination address. In single address mode, the DAR value is ignored when a device with DACK has been specified as the transfer destination. Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will be detected and the DMAC will halt. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode and deep sleep mode. When transfer is performed from an external device with DACK to memory in DDT mode, DTR format [31:0] is set in DAR0 [31:0]. For details, see Data Transfer Request Format in section 14.5.2. Notes: 1. When a 16-bit, 32-bit, 64-bit, or 32-byte boundary address is specified, take care with the setting of bit 0, bits 1-0, bits 2-0, or bits 4-0, respectively. If an address specification that ignores boundary considerations is made, the DMAC will detect an address error and halt operation on all channels (DMAOR: address error flag AE = 1). The DMAC will also detect an address error and halt if an area 7 address is specified in a data transfer employing the external bus, or if the address of a nonexistent on-chip peripheral module is specified. 2. External addresses are 29-bit. As SAR[31:29] and DAR[31:29] are not used in DMA transfers, settings of SAR[31:29] = 000 and DAR[31:29] = 000 are recommended. Rev. 6.0, 07/02, page 497 of 986 14.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3) Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: 0 R 23 0 R 22 0 R 21 0 R 20 0 R 19 0 R 18 0 R 17 0 R 16 Initial value: R/W: Bit: -- R/W 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 Initial value: R/W: Bit: -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W DMA transfer count registers 0-3 (DMATCR0-DMATCR3) are 32-bit readable/writable registers that specify the transfer count for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 (16M) transfers. During DMAC operation, the remaining number of transfers is shown. Bits 31-24 of these registers are reserved; they are always read as 0, and should only be written with 0. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode and deep sleep mode. In DDT mode, settings to DMATCR0[7:0] may be made from DTR format [55:48] as well. For details, see Data Transfer Request Format in section 14.5.2. Rev. 6.0, 07/02, page 498 of 986 14.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) Bit: 31 SSA2 Initial value: R/W: Bit: 0 R/W 23 -- Initial value: R/W: Bit: 0 R 15 DM1 Initial value: R/W: Bit: 0 R/W 7 TM Initial value: R/W: 0 R/W 30 SSA1 0 R/W 22 -- 0 R 14 DM0 0 R/W 6 TS2 0 R/W 29 SSA0 0 R/W 21 -- 0 R 13 SM1 0 R/W 5 TS1 0 R/W 28 STC 0 R/W 20 -- 0 R 12 SM0 0 R/W 4 TS0 0 R/W 27 DSA2 0 R/W 19 DS 0 R/W 11 RS3 0 R/W 3 -- 0 R 26 DSA1 0 R/W 18 RL 0 (R/W) 10 RS2 0 R/W 2 IE 0 R/W 25 DSA0 0 R/W 17 AM 0 R/W 9 RS1 0 R/W 1 TE 0 R/(W) 24 DTC 0 R/W 16 AL 0 (R/W) 8 RS0 0 R/W 0 DE 0 R/W Note: The TE bit can only be written with 0 after being read as 1, to clear the flag. The RL, AM, AL, and DS bits may be absent, depending on the channel. DMA channel control registers 0-3 (CHCR0-CHCR3) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. Bits 31-28 and 27-24 indicate the source address and destination address, respectively; these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA interface space. In other cases, these bits should be cleared to 0. For details of the PCMCIA interface, see section 13.3.7, PCMCIA Interface, in section 13, Bus State Controller (BSC). In DDT mode, CHCR0 is set according to the DTR format. (The following settings are fixed: CHCR0 [31:24] = 0, [18:16] = 0, [15:14] = 01, [13:12] = 01, [2] = 0, [1] = 0, [0] = 1) Bits 18 and 16 are not present in CHCR2 and CHCR3. In CHCR2 and CHCR3, these bits cannot be modified (a write value of 0 should always be used) and are always read as 0. These registers are initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Rev. 6.0, 07/02, page 499 of 986 Bits 31 to 29--Source Address Space Attribute Specification (SSA2-SSA0): These bits specify the space attribute for access to a PCMCIA interface area. Bit 31: SSA2 0 Bit 30: SSA1 0 Bit 29: SSA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Reserved in PCMCIA access Dynamic bus sizing I/O space 8-bit I/O space 16-bit I/O space 8-bit common memory space 16-bit common memory space 8-bit attribute memory space 16-bit attribute memory space (Initial value) Bit 28--Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait cycle control for access to a PCMCIA interface area. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. Bit 28: STC 0 Description C5 space wait cycle selection (Initial value) Settings of bits A5W2-A5W0 in wait control register 2 (WCR2), and bits A5PCW1-A5PCW0, A5TED2-A5TED0, and A5TEH2-A5TEH0 in the PCMCIA control register (PCR), are selected 1 C6 space wait cycle selection Settings of bits A6W2-A6W0 in wait control register 2 (WCR2), and bits A6PCW1-A6PCW0, A6TED2-A6TED0, and A6TEH2-A6TEH0 in the PCMCIA control register (PCR), are selected Note: For details, see section 13.3.7, PCMCIA Interface. Rev. 6.0, 07/02, page 500 of 986 Bits 27 to 25--Destination Address Space Attribute Specification (DSA2-DSA0): These bits specify the space attribute for access to a PCMCIA interface area. Bit 27: DSA2 0 Bit 26: DSA1 0 Bit 25: DSA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Reserved in PCMCIA access Dynamic bus sizing I/O space 8-bit I/O space 16-bit I/O space 8-bit common memory space 16-bit common memory space 8-bit attribute memory space 16-bit attribute memory space (Initial value) Bit 24--Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait cycle control for access to a PCMCIA interface area. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. Bit 24: DTC 0 Description C5 space wait cycle selection (Initial value) Settings of bits A5W2-A5W0 in wait control register 2 (WCR2), and bits A5PCW1-A5PCW0, A5TED2-A5TED0, and A5TEH2-A5TEH0 in the PCMCIA control register (PCR), are selected 1 C6 space wait cycle selection Settings of bits A6W2-A6W0 in wait control register 2 (WCR2), and bits A6PCW1-A6PCW0, A6TED2-A6TED0, and A6TEH2-A6TEH0 in the PCMCIA control register (PCR), are selected Note: For details, see section 13.3.7, PCMCIA Interface. Bits 23 to 20--Reserved: These bits are always read as 0, and should only be written with 0. Rev. 6.0, 07/02, page 501 of 986 Bit 19--'5(4 Select (DS): Specifies either low level detection or falling edge detection as the '5(4 sampling method for the '5(4 pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0-CHCR3. Bit 19: DS 0 1 Description Low level detection Falling edge detection (Initial value) Note: Level detection burst mode when TM = 1 and DS = 0 Edge detection burst mode when TM = 1 and DS = 1 Bit 18--Request Check Level (RL): Selects whether the DRAK signal (that notifies an external device of the acceptance of '5(4) is an active-high or active-low output. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is invalid. Bit 18: RL 0 1 Description DRAK is an active-high output DRAK is an active-low output (Initial value) Bit 17--Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is valid for CHCR1 to CHCR3 in the SH7750. In the SH7750S, this bit is valid for CHCR0 to CHCR3. (DDT mode: 7'$&.) Bit 17: AM 0 1 Description DACK is output in read cycle DACK is output in write cycle (Initial value) Rev. 6.0, 07/02, page 502 of 986 Bit 16--Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is invalid. Bit 16: AL 0 1 Description Active-high output Active-low output (Initial value) Bits 15 and 14--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. For channel 0, in DDT mode these bits are set to DM1 = 0 and DM0 = 1 with the DTR format. Bit 15: DM1 0 Bit 14: DM0 0 1 Description Destination address fixed (Initial value) Destination address incremented (+1 in 8-bit transfer, +2 in 16bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32byte burst transfer) Destination address decremented (-1 in 8-bit transfer, -2 in 16bit transfer, -4 in 32-bit transfer, -8 in 64-bit transfer, -32 in 32byte burst transfer) Setting prohibited 1 0 1 Bits 13 and 12--Source Address Mode 1 and 0 (SM1, SM0): These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. For channel 0, in DDT mode these bits are set to DM1 = 0 and DM0 = 1 with the DTR format. Bit 13: SM1 0 Bit 12: SM0 0 1 Description Source address fixed (Initial value) Source address incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32byte burst transfer) Source address decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer, -8 in 64-bit transfer, -32 in 32byte burst transfer) Setting prohibited 1 0 1 Rev. 6.0, 07/02, page 503 of 986 Bits 11 to 8--Resource Select 3 to 0 (RS3-RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: RS3 RS2 RS1 0 0 0 Bit 8: RS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description 14 External request, dual address mode* * (external address space external address space) (Initial value) Setting prohibited External request, single address mode 134 External address space external device* * * External request, single address mode 134 External device external address space* * * Auto-request (external address space external address 2 space)* Auto-request (external address space on-chip peripheral 2 module)* Auto-request (on-chip peripheral module external address 2 space)* Setting prohibited SCI transmit-data-empty interrupt transfer request 2 (external address space SCTDR1)* SCI receive-data-full interrupt transfer request 2 (SCRDR1 external address space)* SCIF transmit-data-empty interrupt transfer request 2 (external address space SCFTDR2)* SCIF receive-data-full interrupt transfer request 2 (SCFRDR2 external address space)* TMU channel 2 (input capture interrupt, external address space 2 external address space)* TMU channel 2 (input capture interrupt, external address space 2 on-chip peripheral module)* TMU channel 2 (input capture interrupt, on-chip peripheral 2 module external address space)* Setting prohibited Notes: *1 External request specifications are valid only for channels 0 and 1. Requests are not accepted for channels 2 and 3 in normal DMA mode. *2 Dual address mode *3 In DDT mode, selection is possible with the DTR format [60] (R/W bit) and [57-56] (MD1, MD0 bits) specification for channel 0 only. *4 In DDT mode: [SH7750] An external request specification should be set for channels 1 to 3. For channel 0, only single address mode can be set with the DTR format. [SH7750S] An external request specification can be set for channels 0 to 3. Rev. 6.0, 07/02, page 504 of 986 Bit 7--Transmit Mode (TM): Specifies the bus mode for transfer. Bit 7: TM 0 1 Description Cycle steal mode Burst mode (Initial value) Bits 6 to 4--Transmit Size 2 to 0 (TS2-TS0): These bits specify the transfer data size. For external memory access, the setting of these bits serves as the access size in section 14.3, Operation. For register access, the setting of these bits is the size in which the register is accessed. Bit 6: TS2 0 Bit 5: TS1 0 Bit 4: TS0 0 1 1 0 1 1 0 0 Description Quadword size (64-bit) specification(Initial value) Byte size (8-bit) specification Word size (16-bit) specification Longword size (32-bit) specification 32-byte block transfer specification Bit 3--Reserved: This bit is always read as 0, and should only be written with 0. Bit 2--Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated after the number of data transfers specified in DMATCR (when TE = 1). Bit 2: IE 0 1 Description Interrupt request not generated after number of transfers specified in DMATCR (Initial value) Interrupt request generated after number of transfers specified in DMATCR Rev. 6.0, 07/02, page 505 of 986 Bit 1--Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1, the transfer enabled state is not entered even if the DE bit is set to 1. Bit 1: TE 0 Description Number of transfers specified in DMATCR not completed [Clearing conditions] * * 1 When 0 is written to TE after reading TE = 1 In a power-on or manual reset, and in standby mode (Initial value) Number of transfers specified in DMATCR completed Bit 0--DMAC Enable (DE): Enables operation of the corresponding channel. Bit 0: DE 0 1 Description Operation of corresponding channel is disabled Operation of corresponding channel is enabled (Initial value) When auto-request is specified (with RS3-RS0), transfer is begun when this bit is set to 1. In the case of an external request or on-chip peripheral module request, transfer is begun when a transfer request is issued after this bit is set to 1. Transfer can be suspended midway by clearing this bit to 0. Even if the DE bit has been set, transfer is not enabled when TE is 1, when DME in DMAOR is 0, or when the NMIF or AE bit in DMAOR is 1. For channel 0, in DDT mode this bit is set to 1 when a DTR format is received. DE remains set to 1 even if TE is set to 1. When the mode is switched from DDT mode to normal DMA mode (DDT bit = 0 in DMAOR), the DE bit must be cleared to 0. Rev. 6.0, 07/02, page 506 of 986 14.2.5 DMA Operation Register (DMAOR) Bit: 31 -- Initial value: R/W: Bit: 0 R 23 -- Initial value: R/W: Bit: 0 R 15 DDT Initial value: R/W: Bit: 0 R/W 7 -- Initial value: R/W: 0 R 30 -- 0 R 22 -- 0 R 14 -- 0 R 6 -- 0 R 29 -- 0 R 21 -- 0 R 13 -- 0 R 5 -- 0 R 28 -- 0 R 20 -- 0 R 12 -- 0 R 4 COD 0 R/(W) 27 -- 0 R 19 -- 0 R 11 -- 0 R 3 -- 0 R 26 -- 0 R 18 -- 0 R 10 -- 0 R 2 AE 0 R/(W) 25 -- 0 R 17 -- 0 R 9 PR1 0 R/W 1 NMIF 0 R/(W) 24 -- 0 R 16 -- 0 R 8 PR0 0 R/W 0 DME 0 R/W Note: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags. The COD bit can be written to in the SH7750S only. DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode. DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 16--Reserved: These bits are always read as 0, and should only be written with 0. Bit 15--On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. Bit 15: DDT 0 1 Description Normal DMA mode On-demand data transfer mode (Initial value) Note: %$9/ (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1, the %$9/ pin function is enabled and this pin becomes an active-low output. Rev. 6.0, 07/02, page 507 of 986 Bits 14 to 10--Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8--Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. Bit 9: PR1 0 Bit 8: PR0 0 1 1 0 1 Description CH0 > CH1 > CH2 > CH3 CH0 > CH2 > CH3 > CH1 CH2 > CH0 > CH1 > CH3 Round robin mode (Initial value) Bits 7 to 5--Reserved: These bits are always read as 0, and should only be written with 0. Bit 4 (SH7750S)--Check Overrun for '5(4 (COD): When this bit is set to 1, cancellation of an accepted '5(4 acceptance flag is enabled. When cancellation of an accepted '5(4 acceptance flag is enabled by setting COD to 1, clear CHCRn.DS to 0 and then negate '5(4 (to the high level). For details, see External Request Mode in section 14.3.2. Bit 4: COD 0 1 Description '5(4 acceptance flag cancellation disabled '5(4 acceptance flag cancellation enabled (Initial value) Note: When external request mode is used in the SH7750S, recommend setting COD to 1 permanently. Bit 4 (SH7750)--Reserved: These bits are always read as 0, and should only be written with 0. Bit 3--Reserved: This bit is always read as 0, and should only be written with 0. Bit 2--Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE 0 Description No address error, DMA transfer enabled [Clearing condition] When 0 is written to AE after reading AE = 1 1 Address error, DMA transfer disabled [Setting condition] When an address error is caused by the DMAC (Initial value) Rev. 6.0, 07/02, page 508 of 986 Bit 1--NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1. Bit 1: NMIF 0 Description No NMI input, DMA transfer enabled [Clearing condition] When 0 is written to NMIF after reading NMIF = 1 1 NMI input, DMA transfer disabled [Setting condition] When an NMI interrupt is generated (Initial value) Bit 0--DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. Bit 0: DME 0 1 Description Operation disabled on all channels Operation enabled on all channels (Initial value) Rev. 6.0, 07/02, page 509 of 986 14.3 Operation When a DMA transfer request is issued, the DMAC starts the transfer according to the predetermined channel priority order. It ends the transfer when the transfer end conditions are satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. There are two modes for DMA transfer: single address mode and dual address mode. Either burst mode or cycle steal mode can be selected as the bus mode. 14.3.1 DMA Transfer Procedure After the desired transfer conditions have been set in the DMA source address register (SAR), DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA channel control register (CHCR), and DMA operation register (DMAOR), the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one transfer unit of data (determined by the setting of TS2-TS0). In auto-request mode, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value is decremented by 1 for each transfer. The actual transfer flow depends on the address mode and bus mode. 3. When the specified number of transfers have been completed (when the DMATCR value reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DMTE interrupt request is sent to the CPU. 4. If a DMAC address error or NMI interrupt occurs, the transfer is suspended. Transfer is also suspended when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In the event of an address error, a DMAE interrupt request is forcibly sent to the CPU. Figure 14.2 shows a flowchart of this procedure. Note: If transfer request is issued while transfer is disabled, the transfer enable wait state (transfer suspended state) is entered. Transfer is started when subsequently enabled (by setting DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) Rev. 6.0, 07/02, page 510 of 986 Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1? Yes Illegal address check (reflected in AE bit) No *4 NMIF, AE, TE = 0? Yes Transfer request issued? *1 Yes Transfer (1 transfer unit) DMATCR - 1 DMATCR Update SAR, DAR No *2 No *3 Bus mode, transfer request mode, detection method DMATCR = 0? Yes No NMIF or AE = 1 or DE = 0 or DME = 0? Yes Transfer suspended No DMTE interrupt request (when IE = 1) NMIF or AE = 1 or DE = 0 or DME = 0? Yes End of transfer No Normal end Notes: *1 In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE and DME bits are set to 1. *2 level detection (external request) in burst mode, or cycle steal mode. *3 edge detection (external request) in burst mode, or auto-request mode in burst mode. *4 An illegal address is detected by comparing bits TS2-TS0 in CHCRn with SARn and DARn. Figure 14.2 DMAC Transfer Flowchart Rev. 6.0, 07/02, page 511 of 986 14.3.2 DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The transfer request mode is selected by means of bits RS3-RS0 in DMA channel control registers 0-3 (CHCR0-CHCR3). Auto Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bit in CHCR0-CHCR3 and the DME bit in the DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bit in CHCR0-CHCR3 and the NMIF and AE bits in DMAOR are all 0). External Request Mode: In this mode a transfer is performed in response to a transfer request signal ('5(4) from an external device. One of the modes shown in table 14.4 should be chosen according to the application system. If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when '5(4 is input. The DS bit in CHCR0/CHCR1 is used to select either falling edge detection or low level detection for the '5(4 signal (level detection when DS = 0, edge detection when DS = 1). The source of the transfer request does not have to be the data transfer source or destination. '5(4 is accepted after a power-on reset if TE = 0, NMIF = 0, and AE = 0, but transfer is not executed if DMA transfer is not enabled (DE = 0 or DME = 0). In this case, DMA transfer is started when enabled (by setting DE = 1 and DME = 1). Rev. 6.0, 07/02, page 512 of 986 Table 14.4 Selecting External Request Mode with RS Bits RS3 0 RS2 0 RS1 0 RS0 0 Address Mode Dual address mode Transfer Source External memory or memory-mapped external device, or external device with DACK External memory or memory-mapped external device External device with DACK Transfer Destination External memory or memory-mapped external device, or external device with DACK External device with DACK External memory or memory-mapped external device 1 0 Single address mode Single address mode 1 * External Request Acceptance Conditions 1. When at least one of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF, DMAOR.AE, and CHCR.TE are all 0, if an external request ('5(4: edge-detected) is input it will be held inside the DMAC until DMA transfer is either executed or canceled. Since DMA transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not initiated. DMA transfer is started after it is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0, CHCR.TE = 0). 2. When DMA transfer is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0, CHCR.TE = 0), if an external request ('5(4) is input, DMA transfer is started. 3. An external request ('5(4) will be ignored if input when CHCR.TE = 1, DMAOR.NMIF = 1, or DMAOR.AE = 1, or during a power-on reset or manual reset, in deep sleep mode or standby mode, or while the DMAC is in the module standby state. 4. A previously input external request will be canceled by the occurrence of an NMI interrupt (DMAOR.NMIF = 1) or address error (DMAOR.AE = 1), or by a power-on reset or manual reset. In the SH7750S, it is possible to cancel a previously input external request ('5(4). With DMAOR.COD set to 1, clear CHCRn.DS to 0 and then drive the '5(4 pin high. On the SH7750R, it is possible to cancel an external request that has been accepted by external request ('5(4) edge detection by first negating '5(4 and then clearing CHCR.DS from 1 to 0. Afterwards CHCR.DS should be reset to 1 and '5(4 asserted. (The SH7750R has no DMAOR.COD bit, but it is possible to cancel an external request that has been accepted by external request ('5(4) edge detection, as is the case when the DMAOR.COD bit of the SH7750S is set to 1.) * Usage Notes An external request ('5(4) is detected by a low level or falling edge. Ensure that the external request ('5(4) signal is held high when there is no DMA transfer request from an external device after a power-on reset or manual reset. Rev. 6.0, 07/02, page 513 of 986 When DMA transfer is restarted, check whether a DMA transfer request is being held. On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit (TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input. The source of the transfer request does not have to be the data transfer source or destination. However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full interrupt), the transfer source must be the SCI/SCIF's receive data register (SCRDR1/SCFRDR2). When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty interrupt), the transfer destination must be the SCI/SCIF's transmit data register (SCTDR1/SCFTDR2). Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits DMAC Transfer DMAC Transfer RS3 RS2 RS1 RS0 Request Source Request Signal 1 0 0 0 SCI transmitter SCTDR1 (SCI transmit-dataempty transfer request) SCRDR1 (SCI receive-data-full transfer request) SCFTDR2 (SCIF transmit-dataempty transfer request) SCFRDR2 (SCIF receive-data-full transfer request) Input capture occurrence Input capture occurrence Input capture occurrence Transfer Source External* Transfer Destination Bus Mode SCTDR1 Cycle steal mode 1 SCI receiver SCRDR1 External* Cycle steal mode Cycle steal mode 1 0 SCIF transmitter External* SCFTDR2 1 SCIF receiver SCFRDR2 External* Cycle steal mode Burst/cycle steal mode Burst/cycle steal mode Burst/cycle steal mode 1 0 0 1 TMU channel 2 TMU channel 2 TMU channel 2 External* External* External* On-chip peripheral 1 TMU: SCI: SCIF: Notes: 0 On-chip External* peripheral Timer unit Serial communication interface Serial communication interface with FIFO 1. SCI/SCIF burst transfer setting is prohibited. Rev. 6.0, 07/02, page 514 of 986 2. If input capture interrupt acceptance is set for multiple channels and DE = 1 for each channel, processing will be executed on the highest-priority channel in response to a single input capture interrupt. 3. A DMA transfer request by means of an input capture interrupt can be canceled by setting TCR2.ICPE1 = 0 and ICPE0 = 0 in the TMU. * External memory or memory-mapped external device To output a transfer request from an on-chip peripheral module, set the DMA transfer request enable bit for that module and output a transfer request signal. For details, see sections 12, Timer Unit (TMU), 15, Serial Communication Interface (SCI), and 16, Serial Communication Interface with FIFO (SCIF). When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs every transfer in cycle steal mode, and in the last transfer in burst mode. 14.3.3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority system, either in a fixed mode or round robin mode. The mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In this mode, the relative channel priorities remain fixed. The following priority orders are available in fixed mode: * CH0 > CH1 > CH2 > CH3 * CH0 > CH2 > CH3 > CH1 * CH2 > CH0 > CH1 > CH3 The priority order is selected with bits PR1 and PR0 in DMAOR. Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word, longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest priority level. This is illustrated in figure 14.3. The order of priority in round robin mode immediately after a reset is CH0 > CH1 > CH2 > CH3. Note: In round robin mode, if no transfer request is accepted for any channel during DMA transfer, the priority order becomes CH0 > CH1 > CH2 > CH3. Rev. 6.0, 07/02, page 515 of 986 Transfer on channel 0 Initial priority order CH0 > CH1 > CH2 > CH3 Channel 0 is given the lowest priority. Priority order after transfer CH1 > CH2 > CH3 > CH0 Transfer on channel 1 Initial priority order CH0 > CH1 > CH2 > CH3 When channel 1 is given the lowest priority, the priority of channel 0, which was higher than channel 1, is also shifted simultaneously. Priority order after transfer CH2 > CH3 > CH0 > CH1 Transfer on channel 2 Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer CH3 > CH0 > CH1 > CH2 Priority after transfer due to issuance of a transfer request for channel 1 only. Transfer on channel 3 Initial priority order When channel 2 is given the lowest priority, the priorities of channels 0 and 1, which were higher than channel 2, are also shifted simultaneously. If there is a transfer request for channel 1 only immediately afterward, channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down. CH2 > CH3 > CH0 > CH1 CH0 > CH1 > CH2 > CH3 No change in priority order Priority order after transfer CH0 > CH1 > CH2 > CH3 Figure 14.3 Round Robin Mode Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The operation of the DMAC in this case is as follows. Rev. 6.0, 07/02, page 516 of 986 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby). 4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is started (channel 3 is on transfer standby). 6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level. 7. The channel 3 transfer is started. 8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority. Transfer request 1. Issued for channels 0 and 3 3. Issued for channel 1 Channel waiting DMAC operation Channel priority order 0>1>2>3 3 2. Start of channel 0 transfer Change of priority order 1, 3 4. End of channel 0 transfer 1>2>3>0 5. Start of channel 1 transfer 3 6. End of channel 1 transfer Change of priority order 2>3>0>1 7. Start of channel 3 transfer None Change of priority order 8. End of channel 3 transfer 0>1>2>3 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode Rev. 6.0, 07/02, page 517 of 986 14.3.4 Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output. The actual transfer operation timing depends on the bus mode, which can be either burst mode or cycle steal mode. Table 14.6 Supported DMA Transfers Transfer Destination Transfer Source External device with DACK External memory Memory-mapped external device On-chip peripheral module External Device with DACK Not available Single address mode Single address mode Not available External Memory Single address mode Dual address mode Dual address mode Dual address mode Memory-Mapped External Device Single address mode On-Chip Peripheral Module Not available Dual address mode Dual address mode Dual address mode Dual address mode Dual address mode Not available Rev. 6.0, 07/02, page 518 of 986 Address Modes Single Address Mode: In single address mode, both the transfer source and the transfer destination are external; one is accessed by the DACK signal and the other by an address. In this mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the external device strobe signal (DACK) to either the transfer source or transfer destination external device to access it, while outputting an address to the other side of the transfer. Figure 14.5 shows an example of a transfer between external memory and an external device with DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle. External address bus SH7750 Series DMAC External memory External data bus External device with DACK DACK : Data flow Figure 14.5 Data Flow in Single Address Mode Two types of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. Only the external request signal ('5(4) is used in both these cases. Figure 14.6 shows the DMA transfer timing for single address mode. The access timing depends on the type of external memory. For details, see the descriptions of the memory interfaces in section 13, Bus State Controller (BSC). Rev. 6.0, 07/02, page 519 of 986 CKIO A28-A0 CSn D63-D0 DACK WE Data output from external device with DACK DACK signal to external device with DACK signal to external memory space Address output to external memory space (a) From external device with DACK to external memory space CKIO A28-A0 CSn D63-D0 RD DACK Data output from external memory space signal to external memory space DACK signal to external device with DACK (b) From external memory space to external device with DACK Address output to external memory space Figure 14.6 DMA Transfer Timing in Single Address Mode Dual Address Mode: Dual address mode is used to access both the transfer source and the transfer destination by address. The transfer source and destination can be accessed by either onchip peripheral module or external address. Even if the operand cache is used in RAM mode, the RAM cannot be set as the transfer source or transfer destination. In dual address mode, data corresponding to the size specified by CHCRn.TS is read from the transfer source in the data read cycle, and, in the data write cycle, it is transferred in two bus cycles in order to write in the transfer destination the data corresponding to the size specified by Rev. 6.0, 07/02, page 520 of 986 CHCRn.TS. In this process, the transfer data is temporarily stored in the data buffer in the bus state controller (BSC). In a transfer between external memories such as that shown in figure 14.7, data is read from external memory into the BSC's data buffer in the read cycle, then written to the other external memory in the write cycle. Figure 14.8 shows the timing for this operation. The DACK output timing is the same as that of &6Q in a read or write cycle specified by the CHCRn.AM bit. SAR Memory Address bus DMAC DAR Data bus Transfer source module Transfer destination module BSC Data buffer Taking the SAR value as the address, data is read from the transfer source module and stored temporarily in the data buffer in the bus state controller (BSC). 1st bus cycle SAR Memory Address bus DMAC DAR Data bus Transfer source module Transfer destination module BSC Data buffer Taking the DAR value as the address, the data stored in the BSC's data buffer is written to the transfer destination module. 2nd bus cycle Figure 14.7 Operation in Dual Address Mode Rev. 6.0, 07/02, page 521 of 986 CKIO A26-A0 Transfer source address Transfer destination address D63-D0 DACK Data read cycle (1st cycle) Data write cycle (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0- CHCR3. Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus to the CPU at the end of each transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is issued, the DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer. At the end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end condition is satisfied. Cycle steal mode can be used with all categories of transfer request source, transfer source, and transfer destination. Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer conditions in this example are dual address mode and '5(4 level detection. Rev. 6.0, 07/02, page 522 of 986 Bus returned to CPU Bus cycle CPU CPU CPU DMAC Read DMAC Write CPU DMAC Read DMAC Write CPU CPU Figure 14.9 Example of DMA Transfer in Cycle Steal Mode Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data continuously until the transfer end condition is satisfied. With '5(4 low level detection in external request mode, however, when '5(4 is driven high the bus passes to another bus master after the end of the DMAC transfer request that has already been accepted, even if the transfer end condition has not been satisfied. Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in this example are single address mode and '5(4 level detection (CHCRn.DS = 0, CHCRn.TM = 1). Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 14.10 Example of DMA Transfer in Burst Mode Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode setting can also be made. Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the bus mode. Rev. 6.0, 07/02, page 523 of 986 Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Address Mode Single Type of Transfer External device with DACK and external memory External device with DACK and memory-mapped external device Dual External memory and external memory External memory and memory-mapped external device Request Mode External External Bus Mode B/C B/C Transfer Size Usable (Bits) Channels 8/16/32/64/32B 0, 1 (2, 3)* 8/16/32/64/32B 0, 1 (2, 3)* 6 6 Internal* 7 External* Internal* 7 External* 1 1 B/C B/C 56 8/16/32/64/32B 0, 1, 2, 3* * 56 8/16/32/64/32B 0, 1, 2, 3* * 1 Memory-mapped external Internal* 7 device and memory-mapped External* external device B/C 56 8/16/32/64/32B 0, 1, 2, 3* * External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module 32B: B: C: External: Internal: Internal* Internal* 2 3 B/C* 8/16/32/64* 8/16/32/64* 4 56 0, 1, 2, 3* * 2 3 B/C* 4 56 0, 1, 2, 3* * 32-byte burst transfer Burst Cycle steal External request Auto-request or on-chip peripheral module request Notes: *1 External request, auto-request, or on-chip peripheral module request (TMU input capture interrupt request) possible. In the case of an on-chip peripheral module request, it is not possible to specify external memory data transfer with the SCI (SCIF) as the transfer request source. *2 External request, auto-request, or on-chip peripheral module request possible. If the transfer request source is the SCI (SCIF), either the transfer source must be SCRDR1 (SCFRDR2) or the transfer destination must be SCTDR1 (SCFTDR2). *3 When the transfer request source is the SCI (SCIF), only cycle steal mode can be used. *4 Access size permitted for the on-chip peripheral module register that is the transfer source or transfer destination. *5 When the transfer request is an external request, only channels 0 and 1 can be used. *6 In DDT mode, transfer requests can be accepted for all channels from external devices capable of DTR format output. *7 See tables 14.8 and 14.9 for the transfer sources and transfer destinations in DMA transfer by means of an external request. Rev. 6.0, 07/02, page 524 of 986 (a) Normal DMA Mode Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by the SH7750 Series in normal DMA mode. Table 14.8 External Request Transfer Sources and Destinations in Normal Mode Transfer Direction (Settable Memory Interface) Transfer Source 1 2 3 4 5 6 7 8 Synchronous DRAM External device with DACK SRAM-type, DRAM External device with DACK Synchronous DRAM SRAM-type, MPX, PCMCIA SRAM-type, DRAM, PCMCIA, MPX SRAM-type, MPX, PCMCIA * * Transfer Destination External device with DACK Synchronous DRAM External device with DACK SRAM-type, DRAM SRAM-type, MPX, PCMCIA Synchronous DRAM SRAM-type, MPX, PCMCIA SRAM-type, DRAM, PCMCIA, MPX * * Usable Address DMAC Mode Channels Single Single Single Single Dual Dual Dual Dual 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 *: DACK output setting in dual address mode transfer "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting. Notes: 1. Memory interfaces on which transfer is possible in single address mode are SRAM, byte control SRAM, burst ROM, DRAM, and synchronous DRAM. 2. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. (b) DDT Mode Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by the SH7750 Series in DDT mode. Rev. 6.0, 07/02, page 525 of 986 Table 14.9 External Request Transfer Sources and Destinations in DDT Mode Transfer Direction (Settable Memory Interface) Transfer Source 1 2 3 4 5 6 Synchronous DRAM* Synchronous DRAM SRAM-type, MPX, PCMCIA SRAM-type, DRAM, PCMCIA, MPX SRAM-type, MPX, PCMCIA 1 Transfer Destination External device with DACK Synchronous DRAM SRAM-type, MPX, PCMCIA *2 Synchronous DRAM SRAM-type, MPX, PCMCIA *2 SRAM-type, DRAM, PCMCIA, MPX * 2 Usable Address DMAC Mode Channels Single Single Dual Dual *2 Dual Dual 0, 1, 2, 3 0, 1, 2, 3 0, 1, 2, 3 0, 1, 2, 3 0, 1, 2, 3 0, 1, 2, 3 External device with DACK "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting. Notes: 1. The only memory interface on which single address mode transfer is possible in DDT mode is synchronous DRAM. 2. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. *1 In SH7750, the bus width must be 64 bits *2 DACK output setting in dual address mode transfer Bus Mode and Channel Priority Order When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to channel 0, which has a higher priority, the channel 0 transfer is started immediately. If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set for channel 0. If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for channel 0. Channel execution alternates in the order: channel 1 channel 0 channel 1 channel 0. An example of round robin mode operation is shown in figure 14.11. Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the CPU until channel 1 transfer ends. Rev. 6.0, 07/02, page 526 of 986 CPU DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1 CPU CH0 CPU DMAC channel 1 burst mode CH1 CH0 DMAC channel 1 burst mode CPU DMAC channel 0 and channel 1 round robin mode Priority system: Round robin mode Channel 0: Cycle steal mode Channel 1: Burst mode (edge-sensing) Figure 14.11 Bus Handling with Two DMAC Channels Operating Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the bus is passed to the CPU during a break in requests. 14.3.5 Number of Bus Cycle States and '5(4 Pin Sampling Timing Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. See section 13, Bus State Controller (BSC), for details. '5(4 Pin Sampling Timing: In external request mode, the '5(4 pin is sampled at the rising edge of CKIO clock pulses. When '5(4 input is detected, a DMAC bus cycle is generated and DMA transfer executed after four CKIO cycles at the earliest. The second and subsequent '5(4 sampling operations are performed one cycle after the start of the first DMAC transfer bus cycle (in the case of single address mode). DRAK is output for one cycle only, once each time '5(4 is detected, regardless of the transfer mode or '5(4 detection method. In the case of burst mode edge detection, '5(4 is sampled in the first cycle only, and so DRAK is output in the first cycle only . Operation: Figures 14.12 to 14.22 show the timing in each mode. 1. Cycle Steal Mode In cycle steal mode, The '5(4 sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of '5(4. For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. If '5(4 is not detected at this time, sampling is executed in every subsequent cycle. Rev. 6.0, 07/02, page 527 of 986 In figure 14.13 (cycle steal mode, dual address mode, edge detection), DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. The second sampling operation begins from the cycle in which the first DMAC transfer read cycle ends. If '5(4 is not detected at this time, sampling is executed in every subsequent cycle. For details of the timing for various kinds of memory access, see section 13, Bus State Controller (BSC). Figure 14.18 shows the case of cycle steal mode, single address mode, and level detection. In this case, too, transfer is started, at the earliest, four CKIO cycles after the first '5(4 sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer bus cycle. Figure 14.19 shows the case of cycle steal mode, single address mode, and edge detection. In this case, transfer is started, at the earliest, five CKIO cycles after the first '5(4 sampling operation. The second sampling begins one cycle after the first assertion of DRAK. In single address mode, the DACK signal is output every DMAC transfer cycle. 2. Burst Mode, Dual Address Mode, Level Detection '5(4 sampling timing in burst mode using dual address mode and level detection is virtually the same as for cycle steal mode. For example, in figure 14.14, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. 3. Burst Mode, Single Address Mode, Level Detection '5(4 sampling timing in burst mode using single address mode and level detection is shown in figure 14.20. In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first DMAC transfer bus cycle. In single address mode, the DACK signal is output every DMAC transfer cycle. In figure 14.22, with a 32-byte data size, 64-bit bus width, and SDRAM: row hit write, DMAC transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second sampling operation begins one cycle after DACK is asserted for the first DMAC transfer. 4. Burst Mode, Dual Address Mode, Edge Detection In burst mode using dual address mode and edge detection, '5(4 sampling is performed in the first cycle only. Rev. 6.0, 07/02, page 528 of 986 For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. '5(4 is not sampled during this time, and therefore DRAK is output in the first cycle only. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. 5. Burst Mode, Single Address Mode, Edge Detection In burst mode using single address mode and edge detection, '5(4 sampling is performed only in the first cycle. For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. '5(4 is not sampled during this time, and therefore DRAK is output in the first cycle only. In single address mode, the DACK signal is output every DMAC transfer cycle. Suspension of DMA Transfer in Case of '5(4 Level Detection With '5(4 level detection in burst mode or cycle steal mode, and in dual address mode or single address mode, the external device for which DMA transfer is being executed can judge from the rising edge of CKIO that DARK has been asserted, and suspend DMA transfer by negating '5(4. In this case, the next DARK signal is not output. Rev. 6.0, 07/02, page 529 of 986 CKIO Bus locked Source address Destination address Source address Destination address Bus locked A[25:0] Rev. 6.0, 07/02, page 530 of 986 Read Write Read Write D[63:0] (level detection) 1st acceptance 2nd acceptance DRAK0 Bus cycle CPU DMAC CPU DMAC CPU Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus External Bus/'5(4 (Level Detection), DACK (Read Cycle) '5(4 : sampling and determination of channel priority DACK0 CKIO Bus locked Source address Destination address Source address Destination address Bus locked Source address A[25:0] D[63:0] Read Write Read Write Read (edge detection) 1st acceptance 2nd acceptance 3rd acceptance 4th acceptance DRAK0 Bus cycle CPU DMAC CPU DMAC CPU DMAC Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus External Bus/'5(4 (Edge Detection), DACK (Read Cycle) '5(4 : sampling and determination of channel priority Rev. 6.0, 07/02, page 531 of 986 DACK0 CKIO Bus locked Source address Destination address Source address Destination address Bus locked A[25:0] Rev. 6.0, 07/02, page 532 of 986 Read Write Read Write D[63:0] (level detection) 1st acceptance 2nd acceptance DRAK0 Bus cycle CPU DMAC-1 DMAC-2 CPU Figure 14.14 Dual Address Mode/Burst Mode External Bus External Bus/'5(4 (Level Detection), DACK (Read Cycle) '5(4 : sampling and determination of channel priority DACK0 CKIO Bus locked Source address Destination address Source address Destination address Bus locked A[25:0] D[63:0] Read Write Read Write (edge detection) 1st acceptance TE bit: transfer end DRAK0 Bus cycle CPU DMAC-1 DMAC-2 CPU Figure 14.15 Dual Address Mode/Burst Mode External Bus External Bus/'5(4 (Edge Detection), DACK (Read Cycle) '5(4 : sampling and determination of channel priority Rev. 6.0, 07/02, page 533 of 986 DACK0 CKIO On-chip peripheral address bus Source address Source address Source address Rev. 6.0, 07/02, page 534 of 986 Read Read Read On-chip peripheral data bus Destination address Destination address Destination address A[25:0] D[63:0] Write Write Write Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) External Bus CPU CPU DMAC DMAC CPU (Bcyc:Pcyc = 1:1) Bus cycle DMAC CPU CKIO Source address Source address Source address A[25:0] D[63:0] Read Read Read On-chip peripheral address bus Destination address Destination address Destination address On-chip peripheral data bus Write Write Write T1 T2 T1 T2 T1 T2 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus On-Chip SCI (Level Detection) CPU CPU DMAC DMAC CPU DMAC (Bcyc:Pcyc = 1:1) Bus cycle Rev. 6.0, 07/02, page 535 of 986 CKIO Source address Source address Source address Source address A[25:0] Rev. 6.0, 07/02, page 536 of 986 Read Read Read Read D[63:0] (level detection) 1st acceptance 2nd acceptance 3rd acceptance 4th acceptance DRAK0 Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus External Bus/'5(4 (Level Detection) '5(4 CPU DMAC CPU DMAC CPU DMAC CPU : sampling and determination of channel priority Bus cycle DMAC CPU DACK0 CKIO Source address Source address Source address A[25:0] D[63:0] Read Read Read (edge detection) 1st acceptance 2nd acceptance 3rd acceptance DRAK0 Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus External Bus/'5(4 (Edge Detection) '5(4 CPU DMAC CPU DMAC CPU : sampling and determination of channel priority Bus cycle DMAC CPU Rev. 6.0, 07/02, page 537 of 986 DACK0 CKIO Source address Source address Source address Source address A[25:0] Rev. 6.0, 07/02, page 538 of 986 Read Read Read Read D[63:0] (level detection) 1st acceptance 2nd acceptance 3rd acceptance 4th acceptance DRAK0 Figure 14.20 Single Address Mode/Burst Mode External Bus External Bus/'5(4 (Level Detection) '5(4 CPU DMAC-1 DMAC-2 DMAC-3 CPU : sampling and determination of channel priority Bus cycle DMAC-4 DACK0 CKIO Source address Source address Source address Source address A[25:0] D[63:0] Read Read Read Read (edge detection) 1st acceptance TE bit: transfer end DRAK0 Figure 14.21 Single Address Mode/Burst Mode External Bus External Bus/'5(4 (Edge Detection) '5(4 CPU DMAC-1 DMAC-2 DMAC-3 DMAC-4 : sampling and determination of channel priority Bus cycle CPU Rev. 6.0, 07/02, page 539 of 986 DACK0 CKIO Destination address Destination address Destination address A[25:0] Rev. 6.0, 07/02, page 540 of 986 D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 D[63:0] (level detection) 1st acceptance 2nd acceptance 3rd acceptance DRAK0 DMAC-1 CPU Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle DMAC-2 DMAC-3 CPU Bus cycle DACK0 Figure 14.22 Single Address Mode/Burst Mode External Bus External Bus/'5(4 (Level Detection)/32-Byte Block Transfer '5(4 (Bus Width: 64 Bits, SDRAM: Row Hit Write) : sampling and determination of channel priority 14.3.6 Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer. 1. Cycle Steal Mode (External Request, On-Chip Peripheral Module Request, Auto-Request) When a transfer end condition is satisfied, acceptance of DMAC transfer requests is suspended. The DMAC completes transfer for the transfer requests accepted up to the point at which the transfer end condition was satisfied, then stops. In cycle steal mode, the operation is the same for both edge and level transfer request detection. 2. Burst Mode, Edge Detection (External Request, On-Chip Peripheral Module Request, AutoRequest) The delay between the point at which a transfer end condition is satisfied and the point at which the DMAC actually stops is the same as in cycle steal mode. In burst mode with edge detection, only the first transfer request activates the DMAC, but the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in 4 and 5 under Operation in section 14.3.5. Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 3. Burst Mode, Level Detection (External Request) The delay between the point at which a transfer end condition is satisfied and the point at which the DMAC actually stops is the same as in cycle steal mode. As in the case of burst mode with edge detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in 2 and 3 under Operation in section 14.3.5. Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 4. Transfer Suspension Bus Timing Transfer suspension is executed on completion of processing for one transfer unit. In dual address mode transfer, write cycle processing is executed even if a transfer end condition is satisfied during the read cycle, and the transfers covered in 1, 2, and 3 above are also executed before operation is suspended. Rev. 6.0, 07/02, page 541 of 986 Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied: * The value in the DMA transfer count register (DMATCR) reaches 0. * The DE bit in the DMA channel control register (CHCR) is cleared to 0. 1. End of transfer when DMATCR = 0 When the DMATCR value reaches 0, DMA transfer ends on the corresponding channel and the transfer end flag (TE) in CHCR is set. If the interrupt enable bit (IE) is set at this time, an interrupt (DMTE) request is sent to the CPU. Transfer ending when DMATCR = 0 does not follow the procedures described in 1, 2, 3, and 4 in section 14.3.6. 2. End of transfer when DE = 0 in CHCR When the DMA enable bit (DE) in CHCR is cleared, DMA transfer is suspended on the corresponding channel. The TE bit is not set in this case. Transfer ending in this case follows the procedures described in 1, 2, 3, and 4 in section 14.3.6. Conditions for Ending Transfer Simultaneously on All Channels: Transfer ends on all channels simultaneously when either of the following conditions is satisfied: * The address error bit (AE) or NMI flag (NMIF) in the DMA operation register (DMAOR) is set to 1. * The DMA master enable bit (DME) in DMAOR is cleared to 0. 1. End of transfer when AE = 1 in DMAOR If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU. Therefore, when AE is set to 1, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set in this case. Before resuming transfer, it is necessary to make a new setting for the channel that caused the address error, then write 0 to the AE bit after first reading 1 from it. Acceptance of external requests is suspended while AE is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. Rev. 6.0, 07/02, page 542 of 986 2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU. Therefore, when NMIF is set to 1, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set in this case. Before resuming transfer after NMI interrupt handling is completed, 0 must be written to the NMIF bit after first reading 1 from it. As in the case of AE being set to 1, acceptance of external requests is suspended while NMIF is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. 3. End of transfer when DME = 0 in DMAOR If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU. The TE bit is not set in this case. When DME is cleared to 0, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. When resuming transfer, DME must be set to 1. Operation will then be resumed from the next transfer. Rev. 6.0, 07/02, page 543 of 986 14.4 14.4.1 Examples of Use Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here. Table 14.10 shows the transfer conditions and the corresponding register settings. Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings Transfer Conditions Transfer source: external memory Transfer source: external device with DACK Number of transfers: 32 Transfer source address: decremented Transfer destination address: (setting invalid) Transfer request source: external pin ('5(44) edge detection Bus mode: burst Transfer unit: word No interrupt request at end of transfer Channel priority order: 2 > 0 > 1 > 3 DMAOR H'00000201 Register SAR1 DAR1 DMATCR1 CHCR1 Set Value H'0C000000 (Accessed by DACK) H'00000020 H'000022A5 Rev. 6.0, 07/02, page 544 of 986 14.5 14.5.1 On-Demand Data Transfer Mode (DDT Mode) Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to specify direct single address mode transfer to channel 0 via the data bus and DDT module, and simultaneously issue a transfer request, using the '%5(4, %$9/, 75, 7'$&., and ID [1:0] signals between an external device and the DMAC. Figure 14.23 shows a block diagram of the DMAC, DDT, BSC, and an external device (with '%5(4, %$9/, 75, 7'$&., ID [1:0], and D [63:0] = DTR pins). DMAC SAR0 DAR0 DMATCR0 CHCR0 DREQ0-3 Request ddtmode controller bavl Data buffer DDT Memory Address bus Data bus ddtmode tdack id[1:0] BSC Data buffer DTR External device (with , , , , and ID [1:0]) FIFO or memory ID[1:0] Figure 14.23 On-Demand Transfer Mode Block Diagram For channels 0 to 3, after making the settings for normal DMA transfer using the CPU, a transfer request can be issued from an external device using the '%5(4, %$9/, 75, 7'$&., ID [1:0], and D [63:0] = DTR signals (handshake protocol using the data bus). A transfer request can also be issued simply by asserting 75, without using the external bus (handshake protocol without use of the data bus). For channel 2, after making the DMA transfer settings in the normal way, a transfer request can be issued directly from an external device (with '%5(4, %$9/, 75, 7'$&., ID [1:0], and D [63:0] = DTR pins) by asserting '%5(4 and 75 simultaneously. Note: DTR format = Data transfer request format In DDT mode, there is a choice of five modes for performing DMA transfer. Rev. 6.0, 07/02, page 545 of 986 1. Normal data transfer mode (channel 0) %$9/ (the data bus available signal) is asserted in response to '%5(4 (the data bus request signal) from an external device. Two CKIO-synchronous cycles after %$9/ is asserted, the external data bus drives the data transfer setting command (DTR command) in synchronization with 75 (the transfer request signal). The initial settings are then made in the DMAC channel 0 control register, and the DMA transfer is processed. 2. Normal data transfer mode (channels 1 to 3) In this mode, the data transfer settings are made in the DMAC from the CPU, and DMA transfer requests only are performed from the external device. As in 1 above, '%5(4 is asserted from the external device and the external bus is secured, then the DTR format is driven. The transfer request channel can be specified by means of the two ID bits in the DTR format. 3. Handshake protocol using the data bus (valid for channel 0 only) This mode is only valid for channel 0. After the initial settings have been made in the DMAC channel 0 control register by means of normal data transfer mode (channel 0) in the SH7750, or after the initial settings have been made in the DMAC channel 0 control register from the CPU or by means of normal data transfer mode (channel 0) in the SH7750S, the DDT module asserts a data transfer request for the DMAC by setting DTR format ID = 00, MD = 00, and SZ 101 or 110, and driving the DTR format. 4. Handshake protocol without use of the data bus The DDT module includes a function for recording the previously asserted request channel. By using this function, it is possible to assert a transfer request for the channel for which a request was asserted immediately before, by asserting 75 only from an external device after a transfer request has once been made to the channel for which an initial setting has been made in the DMAC control register (DTR format and data transfer setting by the CPU in the DMAC). 5. Direct data transfer mode (valid for channel 2 only) A data transfer request can be asserted for channel 2 by asserting '%5(4 and 75 simultaneously from an external device after the initial settings have been made in the DMAC channel 2 control register. Rev. 6.0, 07/02, page 546 of 986 14.5.2 Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. /DREQ0 /DRACK0 /DREQ1 /DACK0 SH7750 Series ID1, ID0/DRAK1, DACK1 CLK D63-D0 External device A25-A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM Figure 14.24 System Configuration in On-Demand Data Transfer Mode * '%5(4: Data bus release request signal for transmitting the data transfer request format (DTR '%5(4 format) or a DMA request from an external device to the DMAC If there is a wait for release of the data bus, an external device can have the data bus released by asserting '%5(4. When '%5(4 is accepted, the BSC asserts %$9/. * %$9/: Data bus D63-D0 release signal %$9/ Assertion of %$9/ means that the data bus will be released two cycles later. The SH-4 does not switch the data pins to output status for a total of three cycles: the cycle in which the data bus is released and the cycles preceding and following it. * 75 Transfer request signal 75: Assertion of 75 has the following different meanings. In normal data transfer mode (channel 0), 75 is asserted, and at the same time the DTR format is output, two cycles after %$9/ is asserted. In the case of the handshake protocol without use of the data bus, asserting 75 enables a transfer request to be issued for the channel for which a transfer request was made immediately before. This function can be used only when %$9/ is not asserted two cycles earlier. In the case of direct data transfer mode (valid only for channel 2), a direct transfer request can be made to channel 2 by asserting '%5(4 and 75 simultaneously. Rev. 6.0, 07/02, page 547 of 986 * 7'$&. Reply strobe signal for external device from DMAC 7'$&.: The assert timing of this signal is the same as the DACKn assert timing of the memory interfaces. Note that it is a low active signal. * ID1, ID0: Channel number notification signals 00: Channel 0 (means demand data transfer) 01: Channel 1 10: Channel 2 11: Channel 3 Data Transfer Request Format 63 61 60 59 ID R/W 57 MD 55 COUNT 48 (Reserved) 31 ADDRESS 0 SZ Figure 14.25 Data Transfer Request Format The data transfer request format (DTR format) consists of 64 bits, with connection to D[63:0]. In the case of normal data transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus, the transfer data size, read/write access, channel number, transfer request mode, number of transfers, and transfer source or transfer destination address are specified. A specification in bits 47-32 is invalid. In the SH7750, only single address mode can be set in normal data transfer mode (channel 0). With the DTR format, DS = (0: MD = 10, 11, 1: MD = 01), RL = 0, AL = 0, DM[1:0] = 01, SM[1:0] = 01, RS[3:0] = (0010: R/W = 0, 0011: R/W = 1), TM = (0: MD = 11, 1: MD = 01, 10), TS[2:0] = (SZ), and IE = 0 settings are made in DMA channel control register 0, COUNT is set in transfer count register 0, and ADDRESS is set in source/destination address register 0. Therefore, in DDT mode, the above control registers cannot be written to by the CPU, but can be read. In the SH7750S, DMAC control registers CHCR0, SAR0, DAR0, and DMATCR0 can be written to and read by the CPU even in normal data transfer mode (channel 0). Caution is necessary in this case, as a DMAC control register written to by the CPU will be overwritten by a subsequent transfer request (MD[1:0] = 01, 10, or 11) using the DTR format. Bits 63 to 61: Transmit Size (SZ2-SZ0) * 000: Byte size (8-bit) specification * 001: Word size (16-bit) specification * 010: Longword size (32-bit) specification Rev. 6.0, 07/02, page 548 of 986 * 011: Quadword size (64-bit) specification * 100: 32-byte block transfer specification * 101: Setting prohibited * 110: Request queue clear specification * 111: Transfer end specification Bit 60: Read/Write (R/W) * 0: Memory read specification * 1: Memory write specification Bits 59 and 58: Channel Number (ID1, ID0) * 00: Channel 0 (demand data transfer) * 01: Channel 1 * 10: Channel 2 * 11: Channel 3 Bits 57 and 56: Transfer Request Mode (MD1, MD0) * 00: Handshake protocol (data bus used) * 01: Burst mode (edge detection) specification * 10: Burst mode (level detection) specification * 11: Cycle steal mode specification Bits 55 to 48: Transfer Count (COUNT7-COUNT0) * Transfer count: 1 to 255 * 00000000: Maximum number of transfers (16M) Bits 47 to 32: Reserved Bits 31 to 0: Address (ADDRESS31-ADDRESS0) * R/W = 0: Transfer source address specification * R/W = 1: Transfer destination address specification Notes: 1. Only the ID field is valid for channels 1 to 3. 2. To start DMA transfer by means of demand data transfer on channel 0, the initial value of MD in the DTR format must be 01, 10, or 11. 3. The COUNT field is ignored if MD = 00. 4. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst mode and cycle steal mode, a handshake protocol is used to transfer each unit of data. 5. The maximum number of transfers can be specified by setting COUNT = 0 as DTR format initialization data. If the amount of data to be transferred is unknown, set COUNT = 0, start DMA transfer, and transfer the DTR format (ID = 00, MD 00, SZ Rev. 6.0, 07/02, page 549 of 986 = 111) when the required amount of data has been transferred. This will terminate DMA transfer on channel 0. In this case, the TE bit in DMA channel control register 0 is not set, but transfer cannot be restarted. 6. When port functions are used (BCR2.PORTEN = 1) and DDT mode is selected, input the DTR format for D[63:52] and D[31:0]. In this case, if ID[1:0] = 00, input MD[1:0] and SZ 101, 110. 14.5.3 Transfer Request Acceptance on Each Channel On channel 0, a DMA data transfer request can be made by means of the DTR format. No further transfer requests are accepted between DTR format acceptance and the end of the data transfer. On channels 1 to 3, output a transfer request from an external device by means of the DTR format (ID = 01, 10, or 11) after making DMAC control register settings in the same way as in normal DMA mode. Each of channels 1 to 3 has a request queue that can accept up to four transfer requests. When a request queue is full, the fifth and subsequent transfer requests will be ignored, and so transfer requests must not be output. When CHCR.TE = 1 when a transfer request remains in the request queue and a transfer is completed, the request queue retains it. When another transfer request is sent at that time, the transfer request is added to the request queue if the request queue is vacant. Rev. 6.0, 07/02, page 550 of 986 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk Tl Tm Tn To Tp Tq Tr Ts Tt Tu Tv Tw CKIO tAD Row tAD Row Row tCSD tRWD tRASD tRASD tCASD2 tCASD2 c1 tCSD H/L tAD BANK Precharge-sel Address n RD/ tDQMD tDTRS DTR1CKIO cycle (10nsF100MHz) [2CKIO cycle - tDTRS] (18nsF100MHz) tDTRH tRDS c1 tBSD tRDH c2 tBSD tDQMD DQMn c3 c4 D63-D0 (READ) tDBQS tBAVD tTRS tTRH tBAVD tDBQH tTDAD tIDD DMAC Channel tTDAD tIDD Figure 14.26 Single Address Mode: Synchronous DRAM External Device Longword Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01, CAS latency = 3, TPC[2:0] = 001) Rev. 6.0, 07/02, page 551 of 986 ID1-ID0 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk Tl Tm Tn To Tp Tq Tr Ts Tt Tu Tv Tw CKIO tAD Row tAD Row Row tCSD tRWD tRWD tCSD c1 H/L tAD BANK Precharge-sel Rev. 6.0, 07/02, page 552 of 986 tRASD tCASD2 tCASD2 tRASD tDQMD tDTRS tWDD c1 DTR 1CKIO cycle (10ns 100MHz) tBSD tDTRH tDQMD tWDD c2 tBSD c3 c4 tDBQS tBAVD tTRS tTRH tBAVD tDBQH [2CKIO cycle - tDTRS] (18ns F100MHz) tTDAD tIDD DMAC Channel tTDAD tIDD Address RD/ DQMn D63-D0 (READ) Figure 14.27 Single Address Mode: External Device Synchronous DRAM Longword Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01, TRWL[2:0] = 101, TPC[2:0] = 001) ID1-ID0 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk Tl Tm Tn To Tp Tq Tr Ts Tt CKIO tAD Row tAD tAD Row Row tCSD tRWD tRASD tRASD tCASD2 tCASD2 tCSD c1 H/L BANK Precharge-sel Addr RD/ tDQMD tDTRS DTR= 1CKIO cycle (= 10ns: 100MHz) [2CKIO cycles - tDTRS] (= 18ns: 100MHz) tBSD tDTRH tRDS c1 tRDH c2 tBSD tDQMD DQMn c3 c4 D63-D0 (READ) tDBQS tBAVD tBAVD tTRS tTRH tDBQH tTDAD tTDAD Figure 14.28 Dual Address Mode/Synchronous DRAM SRAM Longword Transfer DMAC Channel DMAC Channel Rev. 6.0, 07/02, page 553 of 986 ID1-ID0 CLK A25-A0 RA CA D63-D0 RAS, CAS, WE DTR D0 D1 D2 D3 BA RD ID1, ID0 00 Figure 14.29 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer CLK A25-A0 RA CA D63-D0 RAS, CAS, WE DTR D0 D1 D2 D3 D4 D5 BA WT ID1, ID0 Figure 14.30 Single Address Mode/Burst Mode/External Device External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev. 6.0, 07/02, page 554 of 986 CLK A25-A0 RA CA CA CA D63-D0 RAS, CAS, WE DQMn DTR BA RD D0 RD D1 RD ID1, ID0 00 00 Figure 14.31 Single Address Mode/Burst Mode/External Bus External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev. 6.0, 07/02, page 555 of 986 CLK A25-A0 RA CA CA D63-D0 RAS, CAS, WE DQMn DTR BA D0 WT D1 WT ID1, ID0 Figure 14.32 Single Address Mode/Burst Mode/External Device External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev. 6.0, 07/02, page 556 of 986 CLK A25-A0 CA CA D63-D0 DTR MD = 10 or 11 D0 D1 D2 D3 DTR MD = 00 D0 D1 CMD WT WT ID1, ID0 Start of data transfer Next transfer request Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) Rev. 6.0, 07/02, page 557 of 986 CLK A25-A0 CA CA D63-D0 CMD DTR MD = 10 or 11 D0 D1 D2 D3 D0 D1 D2 D3 WT WT ID1, ID0 Start of data transfer Next transfer request Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) Rev. 6.0, 07/02, page 558 of 986 CLK A25-A0 RA CA D63-D0 RAS, CAS, WE D0 D1 D2 D3 BA RD Figure 14.35 Read from Synchronous DRAM Precharge Bank CLK Transfer requests can be accepted A25-A0 RA CA D63-D0 RAS, CAS, WE D0 BA RD D1 D2 D3 PCH Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) Rev. 6.0, 07/02, page 559 of 986 CLK A25-A0 CA D63-D0 RAS, CAS, WE D0 D1 D2 D3 RD Figure 14.37 Read from Synchronous DRAM (Row Hit) CLK A25-A0 RA CA D63-D0 RAS, CAS, WE D0 D1 D2 D3 BA WT Figure 14.38 Write to Synchronous DRAM Precharge Bank Rev. 6.0, 07/02, page 560 of 986 CLK Transfer requests can be accepted A25-A0 RA CA D63-D0 RAS, CAS, WE D0 BA WT D1 D2 D3 PCH Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) CLK A25-A0 CA D63-D0 RAS, CAS, WE D0 D1 D2 D3 WT Figure 14.40 Write to Synchronous DRAM (Row Hit) Rev. 6.0, 07/02, page 561 of 986 CLK A25-A0 RA CA D63-D0 RAS, CAS, WE DTR D0 D1 D2 BA RD ID1, ID0 00 Figure 14.41 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev. 6.0, 07/02, page 562 of 986 DMA Operation Register (DMAOR) 31 15 9 8 4 2 10 PR[1:0] DDT DDT: 0: Normal DMA mode 1: On-demand data transfer mode COD (SH7750S) AE NMIF DME Figure 14.42 DDT Mode Setting CLK No DMA request sampling A25-A0 CA CA D63-D0 CMD DTR MD = 01 D0 D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 WT WT ID1, ID0 Start of data transfer Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device External Bus Data Transfer Rev. 6.0, 07/02, page 563 of 986 CLK Wait for next DMA request A25-A0 D63-D0 CMD DTR MD = 10 CA D0 RD CA D1 D2 D3 RD D0 D1 D2 D3 ID1, ID0 Start of data transfer Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus External Device Data Transfer CLK A25-A0 CA CA CA D63-D0 DTR MD = 01 RD D0 RD Idle cycle D2 Idle cycle RD D3 Idle cycle CMD DQMn ID1, ID0 Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus External Device Data Transfer Rev. 6.0, 07/02, page 564 of 986 CLK A25-A0 CA CA CA D63-D0 DTR MD = 01 D0 WT D1 WT D3 WT CMD DQMn Idle cycle Idle cycle Idle cycle ID1, ID0 Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device External Bus Data Transfer Rev. 6.0, 07/02, page 565 of 986 CLK A25-A0 RA CA D63-D0 RAS, CAS, WE DTR ID = 1, 2, or 3 BA RD D0 D1 D2 D3 ID1, ID0 01 or 10 or 11 Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1-3 Using Data Bus Rev. 6.0, 07/02, page 566 of 986 CLK A25-A0 RA CA D63-D0 RAS, CAS, WE D0 D1 D2 D3 D4 D5 D6 D7 BA RD ID1, ID0 No DTR cycle, so requests can be made at any time 10 Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus Rev. 6.0, 07/02, page 567 of 986 Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 4th 5th No more requests A25-A0 RA CA CA CA D63-D0 RAS, CAS, WE BA RD D0 D1 RD D2 D3 D0 D1 D2 RD D3 D0 D1 NOP D2 ID1, ID0 Must be ignored (no request transmitted) Figure 14.49 Single Address Mode/Burst Mode/External Bus External Device Data Transfer/Direct Data Transfer Request to Channel 2 Rev. 6.0, 07/02, page 568 of 986 Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 4th 5th A25-A0 RA CA CA D2 D2 CA CA D63-D0 RAS, CAS, WE BA D0 D1 D3 D0 D1 D3 D0 D1 D2 D3 WT WT WT WT ID1, ID0 Must be ignored (no request transmitted) Figure 14.50 Single Address Mode/Burst Mode/External Device External Bus Data Transfer/Direct Data Transfer Request to Channel 2 Rev. 6.0, 07/02, page 569 of 986 Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 4th 5th A25-A0 CA CA CA D2 D2 CA D63-D0 RAS, CAS, WE RD D0 D1 RD D3 D0 D1 RD D3 D0 D1 RD D2 ID1, ID0 Must be ignored (no request transmitted) Figure 14.51 Single Address Mode/Burst Mode/External Bus External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 Rev. 6.0, 07/02, page 570 of 986 Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 4th 5th A25-A0 CA CA CA CA D63-D0 RAS, CAS, WE D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 WT WT WT WT ID1, ID0 Must be ignored (no request transmitted) Figure 14.52 Single Address Mode/Burst Mode/External Device External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 14.5.4 Notes on Use of DDT Module 1. Normal data transfer mode (channel 0) Initial settings for channel 0 demand transfer must be DTR.ID = 00 and DTR.MD = 01, 10, or 11. In this case, only single address mode can be set for channel 0. 2. Normal data transfer mode (channels 1 to 3) If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored. 3. Handshake protocol using the data bus (valid on channel 0 only) a. The handshake protocol using the data bus can be executed only on channel 0. (Set DTR.ID = 00, DTR.MD = 00, DTR.SZ 101 or 110. Operation is not guaranteed if settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ = 101 or 110 are made.) b. If, during execution of the handshake protocol using the data bus for channel 0, a request is input for one of channels 1 to 3, and after that DMA transfer is executed settings of DTR.ID = 00, DTR.MD = 00, and DTR, SZ 101.110 are input in the handshake protocol using the data bus, a transfer request will be asserted for channel 0. Rev. 6.0, 07/02, page 571 of 986 c. In the SH7750S and SH7750R, initial settings can be made in the DMAC channel 0 control register from the CPU (possible settings are CHCR0.RS = 0000, 0010, or 0011). If settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ 101 or 110 are subsequently input, a transfer request to channel 0 will be asserted. 4. Handshake protocol without use of the data bus a. With the handshake protocol without use of the data bus, a DMA transfer request can be input to the DMAC again for the channel for which transfer was requested immediately before by asserting 75 only. b. When using the handshake protocol without use of the data bus, first make the necessary settings in the DMAC control registers. c. When not using the handshake protocol without use of the data bus, if 75 only is asserted without outputting DTR, a request will be issued for the channel for which DMA transfer was requested immediately before. Also, if the first DMA transfer request after a power-on reset is input by asserting 75 only, it will be ignored and the DMAC will not operate. d. If 75 only is asserted by means of the handshake protocol without use of the data bus and a DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE = 1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1. 5. Direct data transfer mode (valid on channel 2 only) a. If a DMA transfer request for channel 2 is input by simultaneous assertion of '%5(4 and 75 during DMA transfer execution with the handshake protocol without use of the data bus, it will be accepted if there is space in the DDT channel 2 request queue. b. In direct data transfer mode (with '%5(4 and 75 asserted simultaneously), '%5(4 is not interpreted as a bus arbitration signal, and therefore the %$9/ signal is never asserted. 6. Request queue transfer request acceptance a. The DDT has four request queues for each of channels 1 to 3. When these request queues are full, a DMA transfer request from an external device will be ignored. b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished (burst mode) or that a DMA bus cycle is not in progress (cycle steal mode). 7. DTR format a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows. When DTR.ID= 00 * * * * MD = 00, SZ 101, 110: Handshake protocol using the data bus MD 00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request) MD 10, SZ = 110: DDT request queue clear Transfer request to channels 1--3 (items other than ID ignored) When DTR.ID 00 Rev. 6.0, 07/02, page 572 of 986 8. Data transfer end request a. A data transfer end request (DTR.ID = 00, MD 00, SZ = 111) cannot be accepted during channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0, transfer cannot be ended midway. b. When a transfer end request (DTR.ID = 00, MD 00, SZ = 111) is accepted, the values set in CHCR0, SAR0, DAR0, and DMATCR0 are retained. With the SH7750, execution cannot be restarted from an external device in this case. To restart execution in the SH7750S and SH7750R, set CHCR0.DE = 1 with an MOV instruction. 9. Request queue clearance a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are all cleared. All external requests held on the DMAC side are also cleared. b. In case 4-d, the DMAC freeze state can be cleared. c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in case 11, the DMAC freeze state can be cleared. 10. '%5(4 assertion a. After '%5(4 is asserted, do not assert '%5(4 again until %$9/ is asserted, as this will result in a discrepancy between the number of '%5(4 and %$9/ assertions. b. The %$9/ assertion period due to '%5(4 assertion is one cycle. If a row address miss occurs in a read or write in the non-precharged bank during synchronous DRAM access, %$9/ is asserted for a number of cycles in accordance with the RAS precharge interval set in BSC.MCR.TCP. c. It takes one cycle for '%5(4 to be accepted by the DMAC after being asserted by an external device. If a row address miss occurs at this time in a read or write in the nonprecharged bank during synchronous DRAM access, and %$9/ is asserted, the '%5(4 signal asserted by the external device is ignored. Therefore, %$9/ is not asserted again due to this signal. 11. Clearing DDT mode Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode, the DMAC will freeze. This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT mode. 12. Confirming DMA transfer requests and number of transfers executed The channel associated with a DMA bus cycle being executed in response to a DMA transfer request can be confirmed by determining the level of external pins ID1 and ID0 at the rising edge of the CKIO clock while 7'$&. is asserted. (ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3) Rev. 6.0, 07/02, page 573 of 986 14.6 14.6.1 Configuration of the DMAC (SH7750R) Block Diagram of the DMAC Figure 14.53 is a block diagram of the DMAC in the SH7750R. DMAC module Count control SARn Registr control DARn Peripheral bus Internal bus DMATCRn Activation control CHCRn On-chip peripheral module DMAOR TMU SCI, SCIF Request priority control queclr0-7 DACK0, DACK1 DRAK0, DRAK1 Bus interface dmaqueclr0-7 External address/on-chip peripheral module address 8 Request SAR0, DAR0, DMATCR0, CHCR0 only DDT module DTR command buffer Request controller CH0 CH1 CH5 CH2 CH6 CH3 CH7 , 32B data buffer / D[63:0] ID[1:0] External bus Bus state controller DBREQ DDTMODE BAVL DDTD 48 bits id[2:0] tdack CH4 DMAORn: SARn: DARn: DMATCRn: CHCRn: n = 0 to 7 DMAC operation register DMAC source address register DMAC destination address register DMAC transfer count register DMAC channel control register Figure 14.53 Block Diagram of the DMAC Rev. 6.0, 07/02, page 574 of 986 14.6.2 Pin Configuration (SH7750R) Tables 14.11 and 14.12 show the pin configuration of the DMAC. Table 14.11 DMAC Pins Channel 0 Pin Name DMA transfer request '5(4 acceptance confirmation Abbreviation '5(43 DRAK0 I/O Input Output Function DMA transfer request input from external device to channel 0 Acceptance of request for DMA transfer from channel 0 to external device Notification to external device of start of execution DMA transfer end notification 1 DMA transfer request '5(4 acceptance confirmation DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device DMA transfer request input from external device to channel 1 Acceptance of request for DMA transfer from channel 1 to external device Notification to external device of start of execution DMA transfer end notification DACK1 Output Strobe output to external device of DMA transfer request from channel 1 to external device '5(44 DRAK1 Input Output Rev. 6.0, 07/02, page 575 of 986 Table 14.12 DMAC Pins in DDT Mode Pin Name Data bus request Data bus available Abbreviation '%5(4 ('5(43) %$9//,'5 (DRAK0) I/O Input Output Function Data bus release request from external device for DTR format input Data bus release notification Data bus can be used 2 cycles after %$9/ is asserted Notification of channel number to external device at same time as 7'$&. output Transfer request signal 75 ('5(44) Input If asserted 2 cycles after %$9/ assertion, DTR format is sent Only 75 asserted: DMA request '%5(4 and 75 asserted simultaneously: Direct request to channel 2 DMAC strobe Channel number notification 7'$&. (DACK0) ID[1:0] (DRAK1, DACK1) Output Output Reply strobe signal for external device from DMAC Notification of channel number to external device at same time as 7'$&. output (ID [1] = DRAK1, ID [0] = DACK1) Requests for DMA transfer from external devices are normally accepted only on channel 0 ('5(43) and channel 1 ('5(44). In DDT mode, the %$9/ pin functions as both the data-busavailable pin and channel-number-notification (,'5) pin. 14.6.3 Register Configuration (SH7750R) Table 14.13 shows the configuration of the DMAC's registers. The DMAC of the SH7750R has a total of 33 registers: four registers are assigned to each channel, and there is a control register for the overall control of the DMAC. Rev. 6.0, 07/02, page 576 of 986 Table 14.13 Register Configuration Channel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 Com- DMA operation mon register Abbreviation SAR0 DAR0 Read/ Write R/W* R/W* 2 Area 7 Initial Value P4 Address Address Undefined Undefined Undefined Access Size H'FFA00000 H'1FA00000 32 H'FFA00004 H'1FA00004 32 H'FFA00008 H'1FA00008 32 2 DMATCR0 R/W* CHCR0 SAR1 DAR1 2 R/W* * H'00000000 H'FFA0000C H'1FA0000C 32 R/W R/W Undefined Undefined Undefined 1 12 H'FFA00010 H'1FA00010 32 H'FFA00014 H'1FA00014 32 H'FFA00018 H'1FA00018 32 DMATCR1 R/W CHCR1 SAR2 DAR2 R/W* R/W R/W H'00000000 H'FFA0001C H'1FA0001C 32 Undefined Undefined Undefined H'FFA00020 H'1FA00020 32 H'FFA00024 H'1FA00024 32 H'FFA00028 H'1FA00028 32 DMATCR2 R/W CHCR2 SAR3 DAR3 R/W* R/W R/W 1 H'00000000 H'FFA0002C H'1FA0002C 32 Undefined Undefined Undefined H'FFA00030 H'1FA00030 32 H'FFA00034 H'1FA00034 32 H'FFA00038 H'1FA00038 32 DMATCR3 R/W CHCR3 DMAOR R/W* R/W* 1 H'00000000 H'FFA0003C H'1FA0003C 32 H'00000000 H'FFA00040 H'1FA00040 32 1 Rev. 6.0, 07/02, page 577 of 986 Table 14.13 Register Configuration (cont) Channel Name 4 DMA source address register 4 DMA destination address register 4 DMA transfer count register 4 DMA channel control register 4 5 DMA source address register 5 DMA destination address register 5 DMA transfer count register 5 DMA channel control register 5 6 DMA source address register 6 DMA destination address register 6 DMA transfer count register 6 DMA channel control register 6 7 DMA source address register 7 DMA destination address register 7 DMA transfer count register 7 DMA channel control register 7 Abbreviation SAR4 DAR4 Read/ Write R/W R/W Area 7 Initial Value P4 Address Address Undefined Undefined Undefined 1 Access Size H'FFA00050 H'1FA00050 32 H'FFA00054 H'1FA00054 32 H'FFA00058 H'1FA00058 32 DMATCR4 R/W CHCR4 SAR5 DAR5 R/W* R/W R/W H'00000000 H'FFA0005C H'1FA0005C 32 Undefined Undefined Undefined H'FFA00060 H'1FA00060 32 H'FFA00064 H'1FA00064 32 H'FFA00068 H'1FA00068 32 DMATCR5 R/W CHCR5 SAR6 DAR6 R/W* R/W R/W 1 H'00000000 H'FFA0006C H'1FA0006C 32 Undefined Undefined Undefined H'FFA00070 H'1FA00070 32 H'FFA00074 H'1FA00074 32 H'FFA00078 H'1FA00078 32 DMATCR6 R/W CHCR6 SAR7 DAR7 R/W* R/W R/W 1 H'00000000 H'FFA0007C H'1FA0007C 32 Undefined Undefined Undefined H'FFA00080 H'1FA00080 32 H'FFA00084 H'1FA00084 32 H'FFA00088 H'1FA00088 32 DMATCR7 R/W CHCR7 R/W* 1 H'00000000 H'FFA0008C H'1FA0008C 32 Notes: Longword access should be used for all control registers. If a different access width is used, reads will return all 0s and writes will not be possible. *1 Bit 1 of CHCR0-CHCR7 and bits 2 and 1 of DMAOR can only be written with 0 after being read as 1, to clear the flags. *2 In the SH7750R, writes from the CPU and writes from external I/O devices using the DTR format are possible in DDT mode. Rev. 6.0, 07/02, page 578 of 986 14.7 14.7.1 Register Descriptions (SH7750R) DMA Source Address Registers 0-7 (SAR0-SAR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA source address registers 0-7 (SAR0-SAR7) are 32-bit readable/writable registers that specify the source address for a DMA transfer. The functions of these registers are the same as on the SH7750 or SH7750S. For more information, see section 14.2.1, DMA Source Address Registers 0-3 (SAR0-SAR3). 14.7.2 DMA Destination Address Registers 0-7 (DAR0-DAR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA destination address registers 0-7 (DAR0-DAR7) are 32-bit readable/writable registers that specify the destination address for a DMA transfer. The functions of these registers are the same as on the SH7750 and SH7750S. For more information, see section 14.2.2, DMA Destination Address Registers 0-3 (DAR0-DAR3). Rev. 6.0, 07/02, page 579 of 986 14.7.3 DMA Transfer Count Registers 0-7 (DMATCR0-DMATCR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA transfer count registers 0-7 (DMATCR0-DMATCR7) are 32-bit readable/writable registers that specify the number of transfers in transfer operations for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). Functions of these registers are the same as the transfer-count registers of the SH7750 or SH7750S. For more information, see section 14.2.3, DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3). 14.7.4 DMA Channel Control Registers 0-7 (CHCR0-CHCR7) Bit: 31 30 29 28 27 26 25 24 23 -- 0 R 22 -- 0 R 21 -- 0 R 20 -- 0 R 19 DS 0 18 RL 0 17 AM 0 16 AL 0 SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W (R/W) R/W (R/W) Bit: 15 14 13 12 11 10 9 8 7 TM 0 6 5 4 3 2 IE 0 1 TE 0 0 DE 0 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value: 0 0 0 0 0 0 0 0 TS2 TS1 TS0 QCL 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/(W) R/W DMA channel control registers 0-7(CHCR0-CHCR7) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. Bits 31-28 and 27-24 correspond to the source address and destination address, respectively; these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA-interface space. In other cases, these bits should be cleared to 0. For more information about the PCMCIA interface, see section 13.3.7, PCMCIA Interface, in section 13, Bus State Controller. Rev. 6.0, 07/02, page 580 of 986 No function is assigned to bits 18 and 16 of the CHCR2-CHCR7 registers. Writing to these bits of the CHCR2-CHCR7 registers is invalid. If, however, a value is written to these bits, it should always be 0. These bits are always read as 0. These registers are initialized to H'00000000 by a power-on or manual reset. Their values are retained in standby, sleep, and deep-sleep modes. Bits 31 to 29--Source Address Space Attribute Specification (SSA2-SSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the SSA2SSA0 bits in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bit 28--Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. For details of the settings, see the description of the STC bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bits 27 to 25--Destination Address Space Attribute Specification (DSA2-DSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the DSA2-DSA0 bits in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bit 24--Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait cycle control for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. For details of the settings, see the description of the DTC bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bits 23 to 20--Reserved: These bits are always read as 0, and should only be written with 0. Bit 19--'5(4 Select (DS): Specifies either low level detection or falling edge detection as the '5(4 sampling method for the '5(4 pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0-CHCR7. For details of the settings, see the description of the DS bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bit 18--Request Check Level (RL): Selects whether the DRAK signal (that notifies an external device of the acceptance of '5(4) is an active-high or active-low output. This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For details of the settings, see the description of the RL bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Rev. 6.0, 07/02, page 581 of 986 Bit 17--Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0-CHCR7. (DDT mode: 7'$&.) For details of the settings, see the description of the AM bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bit 16--Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For details of the settings, see the description of the AL bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bits 15 and 14--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. For details of the settings, see the description of the DM1 and DM0 bits in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bits 13 and 12--Source Address Mode 1 and 0 (SM1, SM0): These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. For details of the settings, see the description of the SM1 and SM0 bits in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bits 11 to 8--Resource Select 3 to 0 (RS3-RS0): These bits specify the transfer request source. For details of the settings, see the description of the RS3-RS0 bits in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bit 7--Transmit Mode (TM): Specifies the bus mode for transfer. For details of the settings, see the description of the TM bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0- CHCR3). Bits 6 to 4--Transmit Size 2 to 0 (TS2-TS0): These bits specify the transfer data size (access size). For details of the settings, see the description of the TS2-TS0 bits in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bit 3Request Queue Clear (QCL): Writing a 1 to this bit clears the request queues of the corresponding channel as well as any external requests that have already been accepted. This bit is only functional when DMAOR.DDT = 1 and DMAOR.DBL = 1. Rev. 6.0, 07/02, page 582 of 986 CHCR Bit 3 QCL 0 Description This bit is always read as 0. Writing a 0 to this bit is invalid. 1 When DMAOR.DBL = 1, writing a 1 to this bit clears the request queues on the DDT side and any external requests stored in the DMAC. The written value is not retained. (Initial value) Bit 2--Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated after the number of data transfers specified in DMATCR (when TE = 1). For details of the settings, see the description of the IE bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). Bit 1--Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1, the transfer enabled state is not entered even if the DE bit is set to 1. For details of the settings, see the description of the TE bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0- CHCR3). Bit 0--DMAC Enable (DE): Enables operation of the corresponding channel. For details of the settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0-3 (CHCR0-CHCR3). 14.7.5 DMA Operation Register (DMAOR) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0 DDT DBL Initial value: 0 0 PR1 PR0 0 0 AE NMIF DME 0 0 0 R/W: R/W R/W R/W R/W R/(W) R/(W) R/W DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode. Rev. 6.0, 07/02, page 583 of 986 DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 16--Reserved: These bits are always read as 0, and should only be written with 0. Bit 15--On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. For details of the settings, see the description of the DDT bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 14Number of DDT-Mode Channels (DBL): Selects the number of channels that are able to accept external requests in DDT mode. Bit 14: DBL 0 1 Description Four DDT-mode channels Eight DDT-mode channels (Initial value) Note: When DMAOR.DBL = 0, channels 4 to 7 cannot accept external requests. When DMAOR.DBL = 1, one channel can be selected from among channels 0-7 by the combination of DTR.SZ and DTR.ID in the DTR format (see figure 14.54). Table 14.14 shows the channel selection by DTR format in the DDT mode. Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1) DTR.ID[1:0] 00 01 10 11 DTR.SZ[2:0] 101 CH0 CH1 CH2 CH3 DTR.SZ[2:0] = 101 CH4 CH5 CH6 CH7 63 SZ 61 60 59 58 57 56 55 R/W ID MD COUNT 4847 32 31 ADDRESS 0 (Reserved) Figure 14.54 DTR Format (Transfer Request Format) (SH7750R) Bits 13 to 10--Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8--Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. Rev. 6.0, 07/02, page 584 of 986 DMAOR Bit 9 PR1 0 0 1 1 DMAOR Bit 8 PR0 0 1 0 1 Description CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1 CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7 Round robin mode (Initial value) Bits 7 to 3--Reserved: These bits are always read as 0, and should only be written with 0. Bit 2--Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 1--NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 0--DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. For details of the settings, see the description of the DME bit in section 14.2.5, DMA Operation Register (DMAOR) Rev. 6.0, 07/02, page 585 of 986 14.8 Operation (SH7750R) Operation specific to the SH7750R is described here. For details of operation, see section 14.3, Operation. 14.8.1 Channel Specification for a Normal DMA Transfer In normal DMA transfer mode, the DMAC always operates with eight channels, and external requests are only accepted on channel 0 ('5(4) and channel 1 ('5(44). After setting the registers of the channels in use, including CHCR, SAR, DAR, and DMATCR, DMA transfer is started on receiving a DMA transfer request in the transfer-enabled state (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), in the order of predetermined priority. The transfer ends when the transfer-end condition is satisfied. There are three modes for transfer requests: autorequest, external request, and on-chip peripheral module request. The addressing modes for DMA transfer are the single-address mode and the dual-address mode. Bus mode is selectable between burst mode and cycle steal mode. 14.8.2 Channel Specification for DDT-Mode DMA Transfer For DMA transfer in DDT mode, the DMAOR.DBL setting selects either four or eight channels. External requests are accepted on channels 0-3 when DMAOR.DBL = 0, and on channels 0-7 when DMAOR.DBL = 1. For further information on these settings, see the entry on the DBL bit in section 14.7.5, DMA Operation Register (DMAOR). 14.8.3 Transfer Channel Notification in DDT Mode When the DMAC is set up for four-channel external request acceptance in DDT mode (DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel that is to be used. For more details, see section 14.5, On-Demand Data Transfer Mode. When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of 7'$&. assertion) assertion of ,'5 from the %$9/ (bus-release notification) pin are used to notify the external device of the DMAC channel that is to be used (see table 14.15, Notification of Transfer Channel in Eight-Channel DDT Mode). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), it is important to note that the %$9/#pin#has the two functions as shown in table 14.16. Rev. 6.0, 07/02, page 586 of 986 Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode %$9//,'5 %$9/ ,'5 1 ID[1:0] 00 01 10 11 0 00 01 10 11 Transfer Channel CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Table 14.16 Function of %$9/ Function of %$9/ 7'$&. = High 7'$&. = Low Bus available (data-bus enabled) Notification of channel number (,'5) 14.8.4 Clearing Request Queues by DTR Format In DDT mode, the request queues of any channel can be cleared by using DTR.ID, DTR.MD, DTR.SZ, and DTR.COUNT [7:4] in a DTR format. This function is only available when DMAOR.DBL = 1. Table 14.17 shows the DTR format settings for clearing request queues. Rev. 6.0, 07/02, page 587 of 986 Table 14.17 DTR Format for Clearing Request Queues DMAOR.DBL DTR.ID 0 00 DTR.MD 10 DTR.SZ 110 DTR.COUNT[7:4] * Description Clear the request queues of all channels (1-7). Clear the CH0 request-accepted flag 11 1 00 10 110 * Setting prohibited Clear the request queues of all channels (1-7). Clear the CH0 request-accepted flag. 11 0001 0010 0011 0100 0101 0110 0111 1000 Clear the CH0 request-accepted flag Clear the CH1 request queues. Clear the CH2 request queues. Clear the CH3 request queues. Clear the CH4 request queues. Clear the CH5 request queues. Clear the CH6 request queues. Clear the CH7 request queues. Note: (SH7750R) DTR.SZ = DTR[63:61], DTR.ID = DTR[59:58], DTR.MD = DTR[57:56], DTR.COUNT[7:4] = DTR[55:52] 14.8.5 Interrupt-Request Codes When the number of transfers specified in DMATCR has been finished and the interrupt request is enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each channel. Table 14.18 lists the interrupt-request codes that are associated with these transfer-end interrupts. Rev. 6.0, 07/02, page 588 of 986 Table 14.18 DMAC Interrupt-Request Codes Source of the Interrupt DMTE0 DMTE1 DMTE2 DMTE3 DMTE4 DMTE5 DMTE6 DMTE7 DMAE Description CH0 transfer-end interrupt CH1 transfer-end interrupt CH2 transfer-end interrupt CH3 transfer-end interrupt CH4 transfer-end interrupt CH5 transfer-end interrupt CH6 transfer-end interrupt CH7 transfer-end interrupt Address error interrupt INTEVT Code H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 Low Priority High DMTE4-DMTE7: These codes are not used in the SH7750 or SH7750S. CKIO / A25-A0 RA CA D63-D0 RAS, CAS, WE DTR D0 D1 D2 BA RD ID1, ID0 00 Figure 14.55 Single Address Mode/Burst Mode/External Bus External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev. 6.0, 07/02, page 589 of 986 CKIO / A25-A0 RA CA D63-D0 RAS, CAS, WE DTR D0 D1 D2 BA RD ID1, ID0 00 Figure 14.56 Single Address Mode/Burst Mode/External Bus External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 Rev. 6.0, 07/02, page 590 of 986 14.9 Usage Notes 1. When modifying SAR0-SAR3, DAR0-DAR3, DMATCR0-DMATCR3, and CHCR0- CHCR3 in the SH7750 or SH7750S or when modifying SAR0-SAR7, DAR0-DAR7, DMATCR0-DMATCR7, and CHCR0-CHCR7 in the SH7750R, first clear the DE bit for the relevant channel. 2. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not operating. Confirmation method when DMA transfer is not executed correctly: With the SH7750 and SH7750S, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0-CHCR3, and DMATCR0-DMATCR3. With the SH7750R, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0-CHCR7, and DMATCR0-DMATCR7. If NMIF was set before the transfer, the DMATCR transfer count will remain at the set value. If NMIF was set during the transfer, when the DE bit is 1 and the TE bit is 0 in CHCR0-CHCR3 in the SH7750 or SH7750S or CHCR0-CHCR7 in the SH7750R, the DMATCR value will indicate the remaining number of transfers. Also, the next addresses to be accessed can be found by reading SAR0-SAR3 and DAR0- DAR3 in the SH7750 or SH7750S or SAR0-SAR7 and DAR0-DAR7 in the SH7750R. If the AE bit has been set, an address error has occurred. Check the set values in CHCR, SAR, and DAR. 3. Check that DMA transfer is not in progress before making a transition to the module standby state, standby mode, or deep sleep mode. Either check that TE = 1 in the SH7750 or SH7750S's CHCR0-CHCR3 or in the SH7750R's CHCR0-CHCR7, or clear DME to 0 in DMAOR to terminate DMA transfer. When DME is cleared to 0 in DMAOR, transfer halts at the end of the currently executing DMA bus cycle. Note, therefore, that transfer may not end immediately, depending on the transfer data size. DMA operation is not guaranteed if the module standby state, standby mode, or deep sleep mode is entered without confirming that DMA transfer has ended. 4. Do not specify a DMAC, CCN, BSC, or UBC control register as the DMAC transfer source or destination. 5. When activating the DMAC, make the SAR, DAR, and DMATCR register settings for the relevant channel before setting DE to 1 in CHCR, or make the register settings with DE cleared to 0 in CHCR, then set DE to 1. It does not matter whether setting of the DME bit to 1 in DMAOR is carried out first or last. To operate the relevant channel, DME and DE must both be set to 1. The DMAC may not operate normally if the SAR, DAR, and DMATCR settings are not made (with the exception of the unused register in single address mode). 6. After the DMATCR count reaches 0 and DMA transfer ends normally, always write 0 to DMATCR even when executing the maximum number of transfers on the same channel. 7. When falling edge detection is used for external requests, keep the external request pin high when making DMAC settings. Rev. 6.0, 07/02, page 591 of 986 8. When using the DMAC in single address mode, set an external address as the address. All channels will halt due to an address error if an on-chip peripheral module address is set. 9. In external request ('5(4) edge detection in the SH7750R, an external request that has been accepted can be cancelled in the following way. Firstly, negate '5(4 and change the value of CHCR.DS from 1 to 0. After that, set the CHCR.DS bit back to 1, then assert '5(4. (Though the SH7750R does not have a DMAOR.COD bit, similar to when the DMAOR.COD bit is 1 in the SH7750S, external requests that have once been accepted can be cancelled when the external request ('5(4) edge is detected.) Rev. 6.0, 07/02, page 592 of 986 Section 15 Serial Communication Interface (SCI) 15.1 Overview The SH7750 Series is equipped with a single-channel serial communication interface (SCI) and a single-channel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF). The SCI can handle both asynchronous and synchronous serial communication. The SCI supports a smart card interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface function for IC card interface use. For details, see section 17, Smart Card Interface. The SCIF is a dedicated asynchronous communication serial interface with built-in 16-stage FIFO registers for both transmission and reception. For details, see section 16, Serial Communication Interface with FIFO (SCIF). 15.1.1 Features SCI features are listed below. * Choice of synchronous or asynchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided that enables serial data communication with a number of processors. There is a choice of 12 serial data transfer formats. Data length: Stop bit length: Parity: Multiprocessor bit: Break detection: 7 or 8 bits 1 or 2 bits Even/odd/none 1 or 0 A break can be detected by reading the RxD pin level directly from the serial port register (SCSPTR1) when a framing error occurs. Receive error detection: Parity, overrun, and framing errors Rev. 6.0, 07/02, page 593 of 986 Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data transfer format. Data length: 8 bits Receive error detection: Overrun errors * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected. * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin * Four interrupt sources There are four interrupt sources--transmit-data-empty, transmit-end, receive-data-full, and receive-error--that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute a data transfer. * When not in use, the SCI can be stopped by halting its clock supply to reduce power consumption. Rev. 6.0, 07/02, page 594 of 986 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus SCRDR1 RxD SCRSR1 SCTDR1 SCTSR1 TxD Parity generation Parity check SCK SCSSR1 SCSCR1 SCSMR1 SCSPTR1 Transmission/ reception control SCBRR1 P Baud rate generator P/4 P/16 P/64 Clock External clock TEI TXI RXI ERI SCI SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 15.1 Block Diagram of SCI Rev. 6.0, 07/02, page 595 of 986 15.1.3 Pin Configuration Table 15.1 shows the SCI pin configuration. Table 15.1 SCI Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation MD0/SCK RxD MD7/TxD I/O I/O Input Output Function Clock input/output Receive data input Transmit data output Note: The serial clock pin and transmit data pin function as mode input pins MD0 and MD7 after a power-on reset. They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/$ bit in SCSMR1. Break state transmission and detection, can be set in the SCI's SCSPTR1 register. 15.1.4 Register Configuration The SCI has the internal registers shown in table 15.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform transmitter/receiver control. With the exception of the serial port register, the SCI registers are initialized in standby mode and in the module standby state as well as after a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Table 15.2 SCI Registers Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Serial port register Abbreviation SCSMR1 SCBRR1 SCSCR1 SCTDR1 SCSSR1 SCRDR1 SCSPTR1 R/W R/W R/W R/W R/W R/(W)* R R/W 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00* 2 P4 Address H'FFE00000 H'FFE00004 H'FFE00008 H'FFE0000C H'FFE00010 H'FFE00014 H'FFE0001C Area 7 Address H'1FE00000 H'1FE00004 H'1FE00008 H'1FE0000C H'1FE00010 H'1FE00014 H'1FE0001C Access Size 8 8 8 8 8 8 8 Notes: *1 Only 0 can be written, to clear flags. *2 The value of bits 2 and 0 is undefined. Rev. 6.0, 07/02, page 596 of 986 15.2 15.2.1 Register Descriptions Receive Shift Register (SCRSR1) Bit: 7 6 5 4 3 2 1 0 R/W: -- -- -- -- -- -- -- -- SCRSR1 is the register used to receive serial data. The SCI sets serial data input from the RxD pin in SCRSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCRDR1 automatically. SCRSR1 cannot be directly read or written to by the CPU. 15.2.2 Receive Data Register (SCRDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R SCRDR1 is the register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received data from SCRSR1 to SCRDR1 where it is stored, and completes the receive operation. SCRSR1 is then enabled for reception. Since SCRSR1 and SCRDR1 function as a double buffer in this way, it is possible to receive data continuously. SCRDR1 is a read-only register, and cannot be written to by the CPU. SCRDR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Rev. 6.0, 07/02, page 597 of 986 15.2.3 Transmit Shift Register (SCTSR1) Bit: 7 6 5 4 3 2 1 0 R/W: -- -- -- -- -- -- -- -- SCTSR1 is the register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCTDR1 to SCTSR1, and transmission started, automatically. However, data transfer from SCTDR1 to SCTSR1 is not performed if the TDRE flag in the serial status register (SCSSR1) is set to 1. SCTSR1 cannot be directly read or written to by the CPU. 15.2.4 Transmit Data Register (SCTDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W SCTDR1 is an 8-bit register that stores data for serial transmission. When the SCI detects that SCTSR1 is empty, it transfers the transmit data written in SCTDR1 to SCTSR1 and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to SCTDR1 during serial transmission of the data in SCTSR1. SCTDR1 can be read or written to by the CPU at all times. SCTDR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. Rev. 6.0, 07/02, page 598 of 986 15.2.5 Serial Mode Register (SCSMR1) Bit: 7 C/$ Initial value: R/W: 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/( 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCSMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SCSMR1 can be read or written to by the CPU at all times. SCSMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7--Communication Mode (C/$): Selects asynchronous mode or synchronous mode as the $ SCI operating mode. Bit 7: C/$ $ 0 1 Description Asynchronous mode Synchronous mode (Initial value) Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting, Bit 6: CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of SCTDR1 is not transmitted. Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5: PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/( bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/( bit. Rev. 6.0, 07/02, page 599 of 986 Bit 4--Parity Mode (O/(): Selects either even or odd parity for use in parity addition and ( checking. The O/( bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/( bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4: O/( ( 0 1 Description Even parity* Odd parity* 2 1 (Initial value) Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set, the STOP bit setting is invalid since stop bits are not added. Bit 3: STOP 0 1 Description 1 stop bit* 1 (Initial value) 2 2 stop bits* Notes: *1 In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. *2 In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Rev. 6.0, 07/02, page 600 of 986 Bit 2--Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, the PE bit and O/( bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function including notes on use, see section 15.3.3, Multiprocessor Communication Function. Bit 2: MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from P, P/4, P/16, and P/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.9, Bit Rate Register (SCBRR1). Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Note: P: Peripheral clock Description P clock P/4 clock P/16 clock P/64 clock (Initial value) 15.2.6 Serial Control Register (SCSCR1) Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCSCR1 can be read or written to by the CPU at all times. SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Rev. 6.0, 07/02, page 601 of 986 Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and the TDRE flag in SCSSR1 is set to 1. Bit 7: TIE 0 1 Description Transmit-data-empty interrupt (TXI) request disabled* Transmit-data-empty interrupt (TXI) request enabled (Initial value) Note: * TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1. Bit 6: RIE 0 1 Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5: TE 0 1 Description Transmission disabled* Transmission enabled* 1 (Initial value) 2 Notes: *1 The TDRE flag in SCSSR1 is fixed at 1. *2 In this state, serial transmission is started when transmit data is written to SCTDR1 and the TDRE flag in SCSSR1 is cleared to 0. SCSMR1 setting must be performed to decide the transmit format before setting the TE bit to 1. Rev. 6.0, 07/02, page 602 of 986 Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4: RE 0 1 Description Reception disabled* Reception enabled* 1 (Initial value) 2 Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. *2 Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SCSMR1 setting must be performed to decide the receive format before setting the RE bit to 1. Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When data with MPB = 1 is received Multiprocessor interrupts enabled* Note: * When receive data including MPB = 1 is received, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCSCR1 are set to 1) and FER and ORER flag setting is enabled. Bit 2--Transmit-End interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation when there is no valid transmit data in SCTDR1 at the time for MSB data transmission. Bit 2: TEIE 0 1 Description Transmit-end interrupt (TEI) request disabled* Transmit-end interrupt (TEI) request enabled* (Initial value) Note: * TEI interrupt requests can be cleared by reading 1 from the TDRE flag in SCSSR1, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. Rev. 6.0, 07/02, page 603 of 986 Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining the SCI's operating mode with SCSMR1. For details of clock source selection, see table 15.9 in section 15.3, Operation. Bit 1: CKE1 0 Bit 0: CKE0 0 Description Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as 1 input pin (input signal ignored)* Internal clock/SCK pin functions as 1 serial clock output* Internal clock/SCK pin functions as 2 clock output* Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as 3 clock input* External clock/SCK pin functions as serial clock input External clock/SCK pin functions as 3 clock input* External clock/SCK pin functions as serial clock input Notes: *1 Initial value *2 Outputs a clock of the same frequency as the bit rate. *3 Inputs a clock with a frequency 16 times the bit rate. Rev. 6.0, 07/02, page 604 of 986 15.2.7 Serial Status Register (SCSSR1) Bit: 7 TDRE Initial value: R/W: 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB -- R 0 MPBT 0 R/W Note: * Only 0 can be written, to clear the flag. SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SCSSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SCSSR1 is initialized to H'84 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1. Bit 7: TDRE 0 Description Valid transmit data has been written to SCTDR1 [Clearing conditions] * * 1 When 0 is written to TDRE after reading TDRE = 1 When data is written to SCTDR1 by the DMAC (Initial value) There is no valid transmit data in SCTDR1 [Setting conditions] * * * Power-on reset, manual reset, standby mode, or module standby When the TE bit in SCSCR1 is 0 When data is transferred from SCTDR1 to SCTSR1 and data can be written to SCTDR1 Rev. 6.0, 07/02, page 605 of 986 Bit 6--Receive Data Register Full (RDRF): Indicates that the received data has been stored in SCRDR1. Bit 6: RDRF 0 Description There is no valid receive data in SCRDR1 [Clearing conditions] * * * 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to RDRF after reading RDRF = 1 When data in SCRDR1 is read by the DMAC (Initial value) There is valid receive data in SCRDR1 [Setting condition] When serial reception ends normally and receive data is transferred from SCRSR1 to SCRDR1 Note: SCRDR1 and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCSCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5: ORER 0 Description Reception in progress, or reception has ended normally* [Clearing conditions] * * 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to ORER after reading ORER = 1 2 1 (Initial value) An overrun error occurred during reception* [Setting condition] When the next serial reception is completed while RDRF = 1 Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. *2 The receive data prior to the overrun error is retained in SCRDR1, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued either. Rev. 6.0, 07/02, page 606 of 986 Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4: FER 0 Description Reception in progress, or reception has ended normally* [Clearing conditions] * * 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to FER after reading FER = 1 1 (Initial value) A framing error occurred during reception [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 2 when reception ends, and the stop bit is 0* Notes: *1 The FER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. *2 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception with parity addition in asynchronous mode, causing abnormal termination. Bit 3: PER 0 Description Reception in progress, or reception has ended normally* [Clearing conditions] * * 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to PER after reading PER = 1 2 1 (Initial value) A parity error occurred during reception * [Setting condition] When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/( bit in SCSMR1 Notes: *1 The PER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. *2 If a parity error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. Rev. 6.0, 07/02, page 607 of 986 Bit 2--Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2: TEND 0 Description Transmission is in progress [Clearing conditions] * * 1 When 0 is written to TDRE after reading TDRE = 1 When data is written to SCTDR1 by the DMAC (Initial value) Transmission has been ended [Setting conditions] * * * Power-on reset, manual reset, standby mode, or module standby When the TE bit in SCSCR1 is 0 When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit character Bit 1--Multiprocessor Bit (MPB)*: This bit is read-only and cannot be written to. The read value is undefined. Note: * This bit is prepared for storing a multi-processor bit in the received data when the receipt is carried out with a multi-processor format in asynchronous mode. This bit does not function correctly in this LSI. However, do not use the read value from this bit. Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used, and when the operation is not transmission. Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether transmission has been completed before changing its value. Bit 0: MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) Rev. 6.0, 07/02, page 608 of 986 15.2.8 Serial Port Register (SCSPTR1) Bit: 7 EIO 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 2 1 0 SPB1IO SPB1DT SPB0IO SPB0DT 0 R/W -- R/W 0 R/W -- R/W Initial value: R/W: 0 R/W SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to H'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7--Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another peripheral module. This bit specifies enabling or disabling of the RXI interrupt. Bit 7: EIO 0 1 Description When the RIE bit is 1, RXI and ERI interrupts are sent to INTC(Initial value) When the RIE bit is 1, only ERI interrupts are sent to INTC Bits 6 to 4--Reserved: These bits are always read as 0, and should only be written with 0. Bit 3--Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO 0 1 Description SPB1DT bit value is not output to the SCK pin SPB1DT bit value is output to the SCK pin (Initial value) Rev. 6.0, 07/02, page 609 of 986 Bit 2--Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 2: SPB1DT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 1--Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO 0 1 Description SPB0DT bit value is not output to the TxD pin SPB0DT bit value is output to the TxD pin (Initial value) Bit 0--Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 0: SPB0DT 0 1 Description Input/output data is low-level Input/output data is high-level SCI I/O port block diagrams are shown in figures 15.2 to 15.4. Rev. 6.0, 07/02, page 610 of 986 Reset R Q D SPB1IO C SPTRW Reset MD0/SCK D SPB1DT C SPTRW Mode setting register Q R SCI Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal * Internal data bus SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/ bit in SCSMR1. Figure 15.2 MD0/SCK Pin Rev. 6.0, 07/02, page 611 of 986 Reset R Q D SPB0IO C SPTRW Reset MD7/TxD R Q D SPB0DT C SPTRW Mode setting register Serial transmit data SPTRW: Write to SPTR Internal data bus SCI Transmit enable signal Figure 15.3 MD7/TxD Pin RxD SCI Serial receive data Internal data bus SPTRR SPTRR: Read SPTR Figure 15.4 RxD Pin Rev. 6.0, 07/02, page 612 of 986 15.2.9 Bit Rate Register (SCBRR1) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR1. SCBRR1 can be read or written to by the CPU at all times. SCBRR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. The SCBRR1 setting is found from the following equations. Asynchronous mode: N= P x 106 - 1 64 x 22n-1 x B Synchronous mode: N= P 8x 22n-1 xB x 106 - 1 Where B: N: P: n: Bit rate (bits/s) SCBRR1 setting for baud rate generator (0 N 255) Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR1 Setting n 0 1 2 3 Clock P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Rev. 6.0, 07/02, page 613 of 986 The bit rate error in asynchronous mode is found from the following equation: Error (%) = P x 106 - 1 x 100 (N + 1) x B x 64 x 22n-1 Table 15.3 shows sample SCBRR1 settings in asynchronous mode, and table 15.4 shows sample SCBRR1 settings in synchronous mode. Rev. 6.0, 07/02, page 614 of 986 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode P (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 n 1 1 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 n 1 1 0 0 0 0 0 0 0 0 2.4576 N 174 127 255 127 63 31 15 7 3 1 1 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 n 1 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 19 9 4 2 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -18.62 0 -14.67 0 P (MHz) 3.6864 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 70 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 207 103 207 103 51 25 12 6 3 2 129 64 129 64 32 15 7 4 3 Legend Blank: No setting is available. --: A setting is available but error occurs. Rev. 6.0, 07/02, page 615 of 986 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont) P (MHz) 6 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 7.37288 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 P (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Rev. 6.0, 07/02, page 616 of 986 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont) P (MHz) 14.7456 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 P (MHz) 24 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 3 3 2 2 1 1 0 0 0 0 0 24.576 N 108 79 159 79 159 79 159 79 39 24 19 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 126 92 186 92 186 92 186 92 46 28 22 28.7 Error (%) 0.31 0.46 -0.08 0.46 -0.08 0.46 -0.08 0.46 -0.61 -1.03 1.55 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 Rev. 6.0, 07/02, page 617 of 986 Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode P (MHz) 4 Bit Rate (bits/s) 10 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M n -- 2 2 1 1 0 0 0 0 0 0 0 0 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 n -- -- 3 3 2 2 1 1 0 0 -- -- -- -- 28.7 N -- -- 223 111 178 89 178 71 143 71 -- -- -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 -- -- 30 N -- -- 233 116 187 93 187 74 149 74 29 14 -- -- Note: As far as possible, the setting should be made so that the error is within 1%. Legend Blank: No setting is available. --: A setting is available but error occurs. Continuous transmission/reception is not possible. * Rev. 6.0, 07/02, page 618 of 986 Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 6.0, 07/02, page 619 of 986 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) P (MHz) 8 16 24 28.7 30 External Input Clock (MHz) 1.3333 2.6667 4.0000 4.7833 5.0000 Maximum Bit Rate (bits/s) 1333333.3 2666666.7 4000000.0 4783333.3 5000000.0 Rev. 6.0, 07/02, page 620 of 986 15.3 15.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SCSMR1 as shown in table 15.8. The SCI clock source is determined by a combination of the C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1, as shown in table 15.9. * Asynchronous mode Data length: Choice of 7 or 8 bits Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) Detection of framing, parity, and overrun errors, and breaks, during reception Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). * Synchronous mode Transfer format: Fixed 8-bit data Detection of overrun errors during reception Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip. When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock. Rev. 6.0, 07/02, page 621 of 986 Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection SCSMR1 Settings Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: C/$ CHR MP PE STOP Mode $ 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 * 0 1 1 0 1 1 * * * * Synchronous mode 8-bit data No Asynchronous 8-bit data mode (multiprocessor 7-bit data format) Yes No Yes 7-bit data No Asynchronous mode Data Length 8-bit data SCI Transfer Format Multiprocessor Parity Stop Bit Bit Bit Length No No 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Note: An asterisk in the table means "Don't care." Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 Bit 7: C/$ $ 0 SCSCR1 Setting Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Synchronous mode Internal Outputs serial clock Mode Asynchronous mode SCI Transmit/Receive Clock Clock Source Internal SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate External Inputs serial clock Rev. 6.0, 07/02, page 622 of 986 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.5 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 Parity bit 1 bit, or none 1 Stop bit(s) 1 or 2 bits 1 1 Transmit/receive data 7 or 8 bits One unit of transfer data (character or frame) Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR1 setting. Rev. 6.0, 07/02, page 623 of 986 Table 15.10 Serial Transfer Formats (Asynchronous Mode) SCSMR1 Settings CHR PE 0 0 MP STOP 0 0 1 S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 * 1 0 S 8-bit data MPB STOP 0 * 1 1 S 8-bit data MPB STOP STOP 1 * 1 0 S 7-bit data MPB STOP 1 * 1 1 S 7-bit data MPB STOP STOP S: STOP: P: MPB: Note: Start bit Stop bit Parity bit Multiprocessor bit An asterisk in the table means "Don't care." Rev. 6.0, 07/02, page 624 of 986 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 One frame Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 15.7 shows a sample SCI initialization flowchart. Rev. 6.0, 07/02, page 625 of 986 Initialization 1. Set the clock selection in SCSCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR1 to 0 Set CKE1 and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR1 Set value in SCBRR1 Wait No When clock output is selected in asynchronous mode, it is output immediately after SCSCR1 settings are made. 2. Set the transmit/receive format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCI will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits End Figure 15.7 Sample SCI Initialization Flowchart Serial Data Transmission (Asynchronous Mode): Figure 15.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. Rev. 6.0, 07/02, page 626 of 986 Start of transmission Read TDRE flag in SCSSR1 No 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) 3. Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB0DT bit to 0 and set the SPB0IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR1 to 0. TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? Yes Read TEND flag in SCSSR1 No TEND = 1? Yes Break output? Yes Clear SPB0DT to 0 and set SPB0IO to 1 Clear TE bit in SCSCR1 to 0 No No End of transmission Figure 15.8 Sample Serial Transmission Flowchart Rev. 6.0, 07/02, page 627 of 986 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. If the TEIE bit in SCSCR1 is set to 1 at this time, a TEI interrupt request is generated. Figure 15.9 shows an example of the operation for transmission in asynchronous mode. Rev. 6.0, 07/02, page 628 of 986 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt TXI interrupt request request Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler One frame TEI interrupt request Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. Rev. 6.0, 07/02, page 629 of 986 Start of reception Read ORER, PER, and FER flags in SCSSR1 PER or FER or ORER = 1? No Read RDRF flag in SCSSR1 No Yes Error handling 1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SCSSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the RxD pin. 2. SCI status check and receive data read : Read SCSSR1 and check that RDRF = 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. 3. Serial reception continuation procedure: To continue serial reception, complete zeroclearing of the RDRF flag before the stop bit for the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by an RXI interrupt and the SCRDR1 value is read.) RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 End of reception Figure 15.10 Sample Serial Reception Flowchart (1) Rev. 6.0, 07/02, page 630 of 986 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCSCR1 to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SCSSR1 to 0 End Figure 15.10 Sample Serial Reception Flowchart (2) Rev. 6.0, 07/02, page 631 of 986 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a. Parity check: The SCI checks whether the number of 1-bits in the receive data agrees with the parity (even or odd) set in the O/( bit in SCSMR1. b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Note: No further receive operations can be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. A receive-data-full request is always output to the DMAC when the RDRF flag changes to 1. Table 15.11 Receive Error Conditions Receive Error Overrun error Abbreviation ORER Condition Reception of next data is completed while RDRF flag in SCSSR1 is set to 1 Stop bit is 0 Received data parity differs from that (even or odd) set in SCSMR1 Data Transfer Receive data is not transferred from SCRSR1 to SCRDR1 Receive data is transferred from SCRSR1 to SCRDR1 Receive data is transferred from SCRSR1 to SCRDR1 Framing error Parity error FER PER Figure 15.11 shows an example of the operation for reception in asynchronous mode. Rev. 6.0, 07/02, page 632 of 986 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 0/1 RDRF FER RXI interrupt request One frame SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ERI interrupt request generated by framing error Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 6.0, 07/02, page 633 of 986 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a serial transmission line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent*. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received*. In this way, data communication is carried out among a number of processors. Figure 15.12 shows an example of inter-processor communication using a multiprocessor format. Note: * With this LSI, the RDRF flag in SCSSR1 is also set to 1 when data with a 0 multiprocessor bit transmitted to another station is received. When the RDRF flag in SCSSR1 is set to 1, check the state of the MPIE bit in SCSCR1 with the exception handling routine, and if the MPIE bit is 1, skip the data. That is to say, data skipping is implemented in cooperation with the exception handling routine. Rev. 6.0, 07/02, page 634 of 986 Transmitting station Serial transmission line Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial data H'01 (MPB = 1) ID transmission cycle: Receiving station specification H'AA (MPB = 0) Data transmission cycle: Data transmission to receiving station specified by ID MPB: Multiprocessor bit Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Formats There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 15.10. Clock See the description under Clock in section 15.3.2. Data Transfer Operations Multiprocessor Serial Data Transmission: Figure 15.13 shows a sample flowchart for multiprocessor serial data transmission. Use the following procedure for multiprocessor serial data transmission after enabling the SCI for transmission. Rev. 6.0, 07/02, page 635 of 986 Start of transmission 1. SCI status check and ID data write: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1. Finally, clear the TDRE flag to 0. 2. Preparation for data transfer: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1. 3. Serial data transmission: Write the first transmit data to SCTDR1, then clear the TDRE flag to 0. To continue data transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Read TEND flag in SCSSR1 No TEND = 1? Yes Set MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1 Clear TDRE flag to 0 Read TEND flag in SCSSR1 No TEND = 1? Yes Clear MPBT bit in SCSSR1 to 0 Write data to SCTDR1 Clear TDRE flag to 0 Read TDRE flag in SCSSR1 No TDRE = 1? Yes No All data transmitted? Yes End of transmission Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart Rev. 6.0, 07/02, page 636 of 986 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. The SCI monitors the TDRE flag. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 5. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE bit) in SCSCR1 is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The order of transmission is the same as in step 2. Figure 15.14 shows an example of SCI operation for transmission using a multiprocessor format. Rev. 6.0, 07/02, page 637 of 986 1 Serial data Start bit Data Multiproces- Stop sor bit bit Start bit Data Multiproces- Stop Start bit sor bit bit Data Multiproces- Stop sor bit bit 1 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 0 D0 D1 D7 0 Idle state (mark state) TDRE TEND One frame Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler MPBT bit cleared to 0, data written to SCTDR1, and TDRE flag cleared to 0 by TEI interrupt handler TXI interrupt request TEI interrupt request Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for multiprocessor serial reception. Use the following procedure for multiprocessor serial data reception after enabling the SCI for reception. Rev. 6.0, 07/02, page 638 of 986 Start of reception Set MPIE bit in SCSCR1 to 1 Read ORER and FER flags in SCSSR1 FER = 1 or ORER = 1? No Read RDRF flag in SCSSR1 Read MPIE bit in SCSCR1 No RDRF = 1 and MPIE = 0? Yes Read receive data in SCRDR1 No This station's ID? Yes Read ORER and FER flags in SCSSR1 FER = 1 or ORER = 1? No Read RDRF flag in SCSSR1 RDRF = 1? Yes Read receive data in SCRDR1 All data received? Yes No No Yes Yes 1. ID reception cycle: Set the MPIE bit in SCSCR1 to 1. 2. SCI status check, ID reception and comparison: Read SCSSR1 and SCSCR1, and check that the RDRF flag is set to 1 and MPIE bit is set to 0, then read the receive data in SCRDR1 and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. 3. SCI status check and data reception: Read SCSSR1 and check that the RDRF flag is set to 1, then read the data in SCRDR1. 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SCSSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Error handling End of reception Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 6.0, 07/02, page 639 of 986 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCSCR1 to 0 Yes Clear ORER and FER flags in SCSSR1 to 0 End Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 6.0, 07/02, page 640 of 986 Figure 15.16 shows an example of SCI operation for multiprocessor format reception. Start Data (ID1) bit 0 D0 D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data1) D0 D1 D7 Stop MPB bit 0 1 1 Serial data 1 Idle state (mark state) MPIE RDRF SCRDR1 value RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ID1 As data is not this RXI interrupt station's ID, MPIE request bit is set to 1 again The RDRF flag is cleared to 0 by the RXI interrupt handler. (a) Data does not match station's ID Start Data (ID2) bit 0 D0 D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data2) D0 D1 D7 Stop MPB bit 0 1 1 Serial data 1 Idle state (mark state) MPIE RDRF SCRDR1 value ID1 ID2 Data2 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data matches this station's ID, reception continues and data is received by RXI interrupt handler MPIE bit set to 1 again (b) Data matches station's ID Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 6.0, 07/02, page 641 of 986 In multiprocessor mode serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. If the MPIE bit is 1, MPIE is cleared to 0 when a 1 is received in the multiprocessor bit position. If the multiprocessor bit is 0, the MPIE bit is not changed. 4. If the MPIE bit is 0, RDRF is checked at the stop bit position, and if RDRF is 1 the overrun error bit is set. If the stop bit is not 0, the framing error bit is set. If RDRF is 0, the value in SCRSR1 is transferred to SCRDR1, and if the stop bit is 0, RDRF is set to 1. 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.17 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * Serial clock LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 * MSB Bit 7 Don't care Note: * High except in continuous transmission/reception Figure 15.17 Data Format in Synchronous Communication In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. Rev. 6.0, 07/02, page 642 of 986 In serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the falling edge of the serial clock. Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. In reception only, if an on-chip clock source is selected, clock pulses are output while RE = 1. When the last data is received, RE should be cleared to 0 before the end of bit 7. Data Transfer Operations SCI Initialization (Synchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. Figure 15.18 shows a sample SCI initialization flowchart. Rev. 6.0, 07/02, page 643 of 986 Initialization 1. Set the clock selection in SCSCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. 2. Set transmit/receive format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Clear TE and RE bits in SCSCR1 to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR1 Set value in SCBRR1 Wait No 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits End Figure 15.18 Sample SCI Initialization Flowchart Rev. 6.0, 07/02, page 644 of 986 Serial Data Transmission (Synchronous Mode): Figure 15.19 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. No 2. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Start of transmission Read TDRE flag in SCSSR1 TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? Yes Read TEND flag in SCSSR1 No TEND = 1? Yes Clear TE bit in SCSCR1 to 0 No End Figure 15.19 Sample Serial Transmission Flowchart Rev. 6.0, 07/02, page 645 of 986 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. After completion of serial transmission, the SCK pin is fixed high. Figure 15.20 shows an example of SCI operation in transmission. Transfer direction Serial clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND Data written to SCTDR1 and TDRE flag cleared to 0 in TXI interrupt handler One frame TXI interrupt request TEI interrupt request TXI interrupt request Figure 15.20 Example of SCI Transmit Operation Rev. 6.0, 07/02, page 646 of 986 Serial Data Reception (Synchronous Mode): Figure 15.21 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. 1. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. 2. SCI status check and receive data read: Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Start of reception Read ORER flag in SCSSR1 ORER = 1? No Read RDRF flag in SCSSR1 No Yes Error handling RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 End of reception Figure 15.21 Sample Serial Reception Flowchart (1) Rev. 6.0, 07/02, page 647 of 986 Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCSSR1 to 0 End Figure 15.21 Sample Serial Reception Flowchart (2) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. Also, as the RDRF flag is not set to 1 when receiving, the flag must be cleared to 0. 3. If the RIE bit in SCRSR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCRSR1 is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Figure 15.22 shows an example of SCI operation in reception. Rev. 6.0, 07/02, page 648 of 986 Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Data read from SCRDR1 and RDRF flag cleared to 0 in RXI interrupt handler One frame RXI interrupt request ERI interrupt request due to overrun error Figure 15.22 Example of SCI Receive Operation Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.23 shows a sample flowchart for simultaneous serial transmit and receive operations. Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCI for transmission and reception. Rev. 6.0, 07/02, page 649 of 986 Start of transmission/reception Read TDRE flag in SCSSR1 No TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. 2. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. 3. SCI status check and receive data read: Read ORER flag in SCSSR1 Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the Yes ORER = 1? RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. No Error handling Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data transferred? Yes Clear TE and RE bits in SCRSR1 to 0 End of transmission/reception 4. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1 and clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the DMAC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1. Similarly, the RDRF flag is cleared automatically when the DMAC is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1. Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception Rev. 6.0, 07/02, page 650 of 986 15.4 SCI Interrupt Sources and DMAC The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in SCSPTR1. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in the serial status register (SCSSR1) is set to 1, a TDR-empty request is generated separately from the interrupt request. A TDR-empty request can activate the direct memory access controller (DMAC) to perform data transfer. The TDRE flag is cleared to 0 automatically when a write to the transmit data register (SCTDR1) is performed by the DMAC. When the RDRF flag in SCSSR1 is set to 1, an RDR-full request is generated separately from the interrupt request. An RDR-full request can activate the DMAC to perform data transfer. The RDRF flag is cleared to 0 automatically when a receive data register (SCRDR1) read is performed by the DMAC. When the ORER, FER, or PER flag in SCSSR1 is set to 1, an ERI interrupt request is generated. The DMAC cannot be activated by an ERI interrupt request. When receive data processing is to be carried out by the DMAC and receive error handling is to be performed by means of an interrupt to the CPU, set the RIE bit to 1 and also set the EIO bit in SCSPTR1 to 1 so that an interrupt error occurs only for a receive error. If the EIO bit is cleared to 0, interrupts to the CPU will be generated even during normal data reception. When the TEND flag in SCSSR1 is set to 1, a TEI interrupt request is generated. The DMAC cannot be activated by a TEI interrupt request. A TXI interrupt indicates that transmit data can be written, and a TEI interrupt indicates that the transmit operation has ended. Table 15.12 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, FER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) DMAC Activation Priority on Reset Release Not possible High Possible Possible Not possible Low See section 5, Exceptions, for the priority order and relation to non-SCI interrupts. Rev. 6.0, 07/02, page 651 of 986 15.5 Usage Notes The following points should be noted when using the SCI. SCTDR1 Writing and the TDRE Flag: The TDRE flag in SCSSR1 is a status flag that indicates that transmit data has been transferred from SCTDR1 to SCTSR1. When the SCI transfers data from SCTDR1 to SCTSR1, the TDRE flag is set to 1. Data can be written to SCTDR1 regardless of the state of the TDRE flag. However, if new data is written to SCTDR1 when the TDRE flag is cleared to 0, the data stored in SCTDR1 will be lost since it has not yet been transferred to SCTSR1. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to SCTDR1. Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the state of the status flags in SCSSR1 is as shown in table 15.13. If there is an overrun error, data is not transferred from SCRSR1 to SCRDR1, and the receive data is lost. Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Errors Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer SCRSR1 SCRDR1 X O O X X O X O: Receive data is transferred from SCRSR1 to SCRDR1. X: Receive data is not transferred from SCRSR1 to SCRDR1. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that the SCI receiver continues to operate in the break state, so if the FER flag is cleared to 0 it will be set to 1 again. Rev. 6.0, 07/02, page 652 of 986 Sending a Break Signal: The input/output condition and level of the TxD pin are determined by bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD pin function is not selected and the value of the SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB0IO and SPB0DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB0DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of its current state, and the TxD pin becomes an output port outputting the value 0. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: The SCI operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 15.24. Rev. 6.0, 07/02, page 653 of 986 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock -7.5 clocks +7.5 clocks Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 - 1 | D - 0.5 | ) - (L - 0.5) F - (1 + F) x 100% ................. (1) 2N N M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% ............................................ (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 6.0, 07/02, page 654 of 986 When Using the DMAC: * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is updated. (See figure 15.25) SCK t TDRE TxD D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4. Figure 15.25 Example of Synchronous Transmission by DMAC * When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI) as the activation source with bits RS3 to RS0 in CHCR. * When using the DMAC for transmission/reception, making a setting to disable RXI and TXI interrupt requests to the interrupt controller. Even if issuance of interrupt requests is set, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program. When Using Synchronous External Clock Mode: * Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock SCK has changed from 0 to 1. * Only set both TE and RE to 1 when external clock SCK is 1. * In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using DMAC: When using the DMAC for transmission/reception, make a setting to suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program. Rev. 6.0, 07/02, page 655 of 986 Rev. 6.0, 07/02, page 656 of 986 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview The SH7750 Series is equipped with a single-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous serial communication. Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1.1 Features SCIF features are listed below. * Asynchronous serial communication Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Receive error detection: Parity, framing, and overrun errors Break detection: If the receive data following that in which a framing error occurred is also at the space "0" level, and there is a frame error, a break is detected. When a framing error occurs, a break can also be detected by reading the RxD2 pin level directly from the serial port register (SCSPTR2). * Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and continuous serial data transmission and reception. * On-chip baud rate generator allows any bit rate to be selected. * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK2 pin Rev. 6.0, 07/02, page 657 of 986 * Four interrupt sources There are four interrupt sources--transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error--that can issue requests independently. * The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. * When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. * Modem control functions (5765 and &765) are provided. * The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained. * A timeout error (DR) can be detected during reception. Rev. 6.0, 07/02, page 658 of 986 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the SCIF. Bus interface Module data bus Internal data bus SCFRDR2 (16-stage) SCFTDR2 (16-stage) RxD2 SCRSR2 SCTSR2 SCSMR2 SCLSR2 SCFDR2 SCFCR2 SCFSR2 SCSCR2 SCSPTR2 Transmission/ reception control SCBRR2 P Baud rate generator P/4 P/16 P/64 Clock TxD2 Parity generation Parity check SCK2 External clock TXI RXI ERI BRI SCIF SCRSR2: SCFRDR2: SCTSR2: SCFTDR2: SCSMR2: SCSCR2: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SCFSR2: SCBRR2: SCSPTR2: SCFCR2: SCFDR2: SCLSR2: Serial status register Bit rate register Serial port register FIFO control register FIFO data count register Line status register Figure 16.1 Block Diagram of SCIF Rev. 6.0, 07/02, page 659 of 986 16.1.3 Pin Configuration Table 16.1 shows the SCIF pin configuration. Table 16.1 SCIF Pins Pin Name Serial clock pin Receive data pin Transmit data pin Modem control pin Modem control pin Abbreviation SCK2/05(6(7 MD2/RxD2 MD1/TxD2 &765 MD8/5765 I/O Input Input Output I/O I/O Function Clock input Receive data input Transmit data output Transmission enabled Transmission request Note: After a power-on reset, these pins function as mode input pins MD0, MD1, MD2, MD7, and MD8. These pins can function as serial pins by setting the SCIF operation with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2. These pins are made to function as serial pins by performing SCIF operation settings with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. Rev. 6.0, 07/02, page 660 of 986 16.1.4 Register Configuration The SCIF has the internal registers shown in table 16.2. These registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. Table 16.2 SCIF Registers Name Serial mode register Bit rate register Serial control register Abbreviation R/W SCSMR2 SCBRR2 SCSCR2 R/W R/W R/W Initial Value H'0000 H'FF H'0000 P4 Address Area 7 Address Access Size H'FFE80000 H'IFE80000 16 H'FFE80004 H'IFE80004 8 H'FFE80008 H'IFE80008 16 Transmit FIFO data register SCFTDR2 W Serial status register SCFSR2 Undefined H'FFE8000C H'IFE8000C 8 H'FFE80010 H'IFE80010 16 1 R/(W)* H'0060 Receive FIFO data register SCFRDR2 R FIFO control register FIFO data count register Serial port register Line status register SCFCR2 SCFDR2 R/W R R/(W)* 3 Undefined H'FFE80014 H'IFE80014 8 H'0000 H'0000 H'0000* H'0000 2 H'FFE80018 H'IFE80018 16 H'FFE8001C H'IFE8001C 16 H'FFE80020 H'IFE80020 16 H'FFE80024 H'IFE80024 16 SCSPTR2 R/W SCLSR2 Notes: *1 Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot be modified. *2 The value of bits 6, 4, and 0 is undefined. *3 Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified. 16.2 16.2.1 Register Descriptions Receive Shift Register (SCRSR2) Bit: 7 6 5 4 3 2 1 0 R/W: -- -- -- -- -- -- -- -- SCRSR2 is the register used to receive serial data. The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO register, SCFRDR2, automatically. SCRSR2 cannot be directly read or written to by the CPU. Rev. 6.0, 07/02, page 661 of 986 16.2.2 Receive FIFO Data Register (SCFRDR2) Bit: 7 6 5 4 3 2 1 0 R/W: R R R R R R R R SCFRDR2 is a 16-stage FIFO register that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO register is full (16 data bytes). SCFRDR2 is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in the receive FIFO register, an undefined value will be returned. When the receive FIFO register is full of receive data, subsequent serial data is lost. The contents of SCFRDR2 are undefined after a power-on reset or manual reset. 16.2.3 Transmit Shift Register (SCTSR2) Bit: 7 6 5 4 3 2 1 0 R/W: -- -- -- -- -- -- -- -- SCTSR2 is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR2 to SCTSR2, then sends the data to the TxD2 pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR2 to SCTSR2, and transmission started, automatically. SCTSR2 cannot be directly read or written to by the CPU. Rev. 6.0, 07/02, page 662 of 986 16.2.4 Transmit FIFO Data Register (SCFTDR2) Bit: 7 6 5 4 3 2 1 0 R/W: W W W W W W W W SCFTDR2 is an 8-bit 16-stage FIFO register that stores data for serial transmission. If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission. SCFTDR2 is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR2 is filled with 16 bytes of transmit data. Data written in this case is ignored. The contents of SCFTDR2 are undefined after a power-on reset or manual reset. 16.2.5 Serial Mode Register (SCSMR2) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 CHR 0 R/W 13 -- 0 R 5 PE 0 R/W 12 -- 0 R 4 O/( 0 R/W 11 -- 0 R 3 STOP 0 R/W 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 CKS1 0 R/W 8 -- 0 R 0 CKS0 0 R/W SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source. SCSMR2 can be read or written to by the CPU at all times. SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 7--Reserved: These bits are always read as 0, and should only be written with 0. Rev. 6.0, 07/02, page 663 of 986 Bit 6--Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length. Bit 6: CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted. Bit 5--Parity Enable (PE): Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. Bit 5: PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/( bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/( bit. Bit 4--Parity Mode (O/(): Selects either even or odd parity for use in parity addition and ( checking. The O/( bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. The O/( bit setting is invalid when parity addition and checking is disabled. Bit 4: O/( ( 0 1 Description Even parity* Odd parity* 2 1 (Initial value) Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length. Bit 3: STOP 0 1 Description 1 stop bit* 1 (Initial value) 2 2 stop bits* Notes: *1 In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. *2 In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. Rev. 6.0, 07/02, page 664 of 986 In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2--Reserved: This bit is always read as 0, and should only be written with 0. Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from P, P/4, P/16, and P/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, Bit Rate Register (SCBRR2). Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Note: P: Peripheral clock Description P clock P/4 clock P/16 clock P/64 clock (Initial value) 16.2.6 Serial Control Register (SCSCR2) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 TIE Initial value: R/W: 0 R/W 14 -- 0 R 6 RIE 0 R/W 13 -- 0 R 5 TE 0 R/W 12 -- 0 R 4 RE 0 R/W 11 -- 0 R 3 REIE 0 R/W 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 CKE1 0 R/W 8 -- 0 R 0 -- 0 R The SCSCR2 register performs enabling or disabling of SCIF transfer operations, and interrupt requests, and selection of the serial clock source. SCSCR2 can be read or written to by the CPU at all times. SCSCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Rev. 6.0, 07/02, page 665 of 986 Bits 15 to 8, 2, and 0--Reserved: These bits are always read as 0, and should only be written with 0. Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1. Bit 7: TIE 0 1 Description Transmit-FIFO-data-empty interrupt (TXI) request disabled* Transmit-FIFO-data-empty interrupt (TXI) request enabled (Initial value) Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR2 after reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0. Bit 6--Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1. Bit 6: RIE 0 1 Description Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request disabled* (Initial value) Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request enabled Note: * An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF. Bit 5: TE 0 1 Description Transmission disabled Transmission enabled* (Initial value) Note: * Serial transmission is started when transmit data is written to SCFTDR2 in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1. Rev. 6.0, 07/02, page 666 of 986 Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCIF. Bit 4: RE 0 1 Description Reception disabled* Reception enabled* 1 (Initial value) 2 Notes: *1 Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states. *2 Serial transmission is started when a start bit is detected in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1. Bit 3--Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Bit 3: REIE 0 1 Description Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled* (Initial value) Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled Note: * Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests. Bit 1--Clock Enable 1 (CKE1): Selects the SCIF clock source. The CKE1 bit must be set before determining the SCIF's operating mode with SCSMR2. Bit 1: CKE1 0 1 Description Internal clock/SCK2 pin functions as port External clock/SCK2 pin functions as clock input* (Initial value) Note: * Inputs a clock with a frequency 16 times the bit rate. Rev. 6.0, 07/02, page 667 of 986 16.2.7 Serial Status Register (SCFSR2) Bit: 15 PER3 Initial value: R/W: Bit: 0 R 7 ER Initial value: R/W: 0 R/(W)* 14 PER2 0 R 6 TEND 1 R/(W)* 13 PER1 0 R 5 TDFE 1 R/(W)* 12 PER0 0 R 4 BRK 0 R/(W)* 11 FER3 0 R 3 FER 0 R 10 FER2 0 R 2 PER 0 R 9 FER1 0 R 1 RDF 0 R/(W)* 8 FER0 0 R 0 DR 0 R/(W)* Note: * Only 0 can be written, to clear the flag. SCFSR2 is a 16-bit register. The lower 8 bits consist of status flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the receive FIFO register. SCFSR2 can be read or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified. SCFSR2 is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 12--Number of Parity Errors (PER3-PER0): These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 15 to 12 is the number of data bytes in which a parity error occurred. If all 16 bytes of receive data in SCFRDR2 have parity errors, the value indicated by bits PER3 to PER0 will be 0. Bits 11 to 8--Number of Framing Errors (FER3-FER0): These bits indicate the number of data bytes in which a framing error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 11 to 8 is the number of data bytes in which a framing error occurred. If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3 to FER0 will be 0. Rev. 6.0, 07/02, page 668 of 986 Bit 7--Receive Error (ER): Indicates that a framing error or parity error occurred during reception.* Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR2, and reception continues. The FER and PER bits in SCFSR2 can be used to determine whether there is a receive error that is to be from SCFRDR2. Bit 7: ER 0 Description No framing error or parity error occurred during reception [Clearing conditions] * * 1 Power-on reset or manual reset When 0 is written to ER after reading ER = 1 (Initial value) A framing error or parity error occurred during reception [Setting conditions] * * When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0* When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/( bit in SCSMR2 Note: * In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. Rev. 6.0, 07/02, page 669 of 986 Bit 6--Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND 0 Description Transmission is in progress [Clearing conditions] * * 1 When transmit data is written to SCFTDR2, and 0 is written to TEND after reading TEND = 1 When data is written to SCFTDR2 by the DMAC (Initial value) Transmission has been ended [Setting conditions] * * * Power-on reset or manual reset When the TE bit in SCSCR2 is 0 When there is no transmit data in SCFTDR2 on transmission of the last bit of a 1-byte serial transmit character Rev. 6.0, 07/02, page 670 of 986 Bit 5--Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and new transmit data can be written to SCFTDR2. Bit 5: TDFE 0 Description A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR2 [Clearing conditions] * * When transmit data exceeding the transmit trigger set number is written to SCFTDR2 after reading TDFE = 1, and 0 is written to TDFE When transmit data exceeding the transmit trigger set number is written to SCFTDR2 by the DMAC 1 The number of transmit data bytes in SCFTDR2 does not exceed the transmit trigger set number (Initial value) [Setting conditions] * * Power-on reset or manual reset When the number of SCFTDR2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation* Note: * As SCFTDR2 is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be ignored. The number of data bytes in SCFTDR2 is indicated by the upper bits of SCFDR2. Bit 4--Break Detect (BRK): Indicates that a receive data break signal has been detected. Bit 4: BRK 0 Description A break signal has not been received [Clearing conditions] * * 1 Power-on reset or manual reset When 0 is written to BRK after reading BRK = 1 (Initial value) A break signal has been received* [Setting condition] When data with a framing error is received, followed by the space "0" level (low level ) for at least one frame length Note: * When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR2. When the break ends and the receive signal returns to mark "1", receive data transfer is resumed. Rev. 6.0, 07/02, page 671 of 986 Bit 3--Framing Error (FER): Indicates whether or not a framing error has been found in the data that is to be read next from SCFRDR2. Bit 3: FER 0 Description There is no framing error that is to be read from SCFRDR2 [Clearing conditions] * * Power-on reset or manual reset When there is no framing error in the data that is to be read next from SCFRDR2 (Initial value) 1 There is a framing error that is to be read from SCFRDR2 [Setting condition] When there is a framing error in the data that is to be read next from SCFRDR2 Bit 2--Parity Error (PER): Indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR2. Bit 2: PER 0 Description There is no parity error that is to be read from SCFRDR2 (Initial value) [Clearing conditions] * * Power-on reset or manual reset When there is no parity error in the data that is to be read next from SCFRDR2 1 There is a parity error in the receive data that is to be read from SCFRDR2 [Setting condition] When there is a parity error in the data that is to be read next from SCFRDR2 Rev. 6.0, 07/02, page 672 of 986 Bit 1--Receive FIFO Data Full (RDF): Indicates that the received data has been transferred from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2). Bit 1: RDF 0 Description The number of receive data bytes in SCFRDR2 is less than the receive trigger set number (Initial value) [Clearing conditions] * * Power-on reset or manual reset When SCFRDR2 is read until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number after reading RDF = 1, and 0 is written to RDF When SCFRDR2 is read by the DMAC until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number * 1 The number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR2 contains at least the receive trigger set number of receive data bytes* Note: * SCFRDR2 is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR2 is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR2 is indicated by the lower bits of SCFDR2. Rev. 6.0, 07/02, page 673 of 986 Bit 0--Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. Bit 0: DR 0 Description Reception is in progress or has ended normally and there is no receive data left in SCFRDR2 (Initial value) [Clearing conditions] * * * 1 Power-on reset or manual reset When all the receive data in SCFRDR2 has been read after reading DR = 1, and 0 is written to DR When all the receive data in SCFRDR2 has been read by the DMAC No further receive data has arrived [Setting condition] When SCFRDR2 contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received* Note: * Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: Elementary time unit (time for transfer of 1 bit) 16.2.8 Bit Rate Register (SCBRR2) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR2. SCBRR2 can be read or written to by the CPU at all times. SCBRR2 is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Rev. 6.0, 07/02, page 674 of 986 The SCBRR2 setting is found from the following equation. Asynchronous mode: N= P x 106 - 1 64 x 22n-1 x B Where B: N: P: n: Bit rate (bits/s) SCBRR2 setting for baud rate generator (0 N 255) Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR2 Setting n 0 1 2 3 Clock P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following equation: Error (%) = P x 106 - 1 x 100 (N + 1) x B x 64 x 22n-1 16.2.9 FIFO Control Register (SCFCR2) Bit: 15 -- 14 -- 0 R 6 RTRG0 0 R/W 13 -- 0 R 5 TTRG1 0 R/W 12 -- 0 R 4 TTRG0 0 R/W 11 -- 0 R 3 MCE 0 R/W 10 9 8 RSTRG2* RSTRG1* RSTRG0* Initial value: R/W: Bit: 0 R 7 RTRG1 0 R/W 2 TFRST 0 R/W 0 R/W 1 RFRST 0 R/W 0 R/W 0 LOOP 0 R/W Initial value: R/W: 0 R/W Note: * Reserved bit in the SH7750. Rev. 6.0, 07/02, page 675 of 986 SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR2 can be read or written to by the CPU at all times. SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 11--Reserved: These bits are always read as 0, and should only be written with 0. Bits 10 to 8 (SH7750)--Reserved: These bits are always read as 0, and should only be written with 0. Bits 10 to 8 (SH7750S, SH7750R)--5765 Output Active Trigger (RSTRG2, RSTG1, and 5765 RSTG0): These bits output the high level to the 5765 signal when the number of received data stored in the receive FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the table below. Bit 10: RSTRG2 0 Bit 9: RSTRG1 0 Bit 8: RSTRG0 0 1 1 0 1 1 0 0 1 1 0 1 5765 Output Active Trigger 15 1 4 6 8 10 12 14 (Initial value) Bits 7 and 6--Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register (SCFSR2). The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than the trigger set number shown in the following table. Bit 7: RTRG1 0 Bit 6: RTRG0 0 1 1 0 1 Receive Trigger Number 1 4 8 14 (Initial value) Rev. 6.0, 07/02, page 676 of 986 Bits 5 and 4--Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the following table. Bit 5: TTRG1 0 Bit 4: TTRG0 0 1 1 0 1 Transmit Trigger Number 8 (8) 4 (12) 2 (14) 1 (15) (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. Bit 3--Modem Control Enable (MCE): Enables the &765 and 5765 modem control signals. Bit 3: MCE 0 1 Description Modem signals disabled* Modem signals enabled (Initial value) Note: * &765 is fixed at active-0 regardless of the input value, and 5765 output is also fixed at 0. Bit 2--Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. Bit 2: TFRST 0 1 Description Reset operation disabled* Reset operation enabled (Initial value) Note: * A reset operation is performed in the event of a power-on reset or manual reset. Bit 1--Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive FIFO data register and resets it to the empty state. Bit 1: RFRST 0 1 Description Reset operation disabled* Reset operation enabled (Initial value) Note: * A reset operation is performed in the event of a power-on reset or manual reset. Rev. 6.0, 07/02, page 677 of 986 Bit 0--Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive input pin (RxD2), and the 5765 pin and &765 pin, enabling loopback testing. Bit 0: LOOP 0 1 Description Loopback test disabled Loopback test enabled (Initial value) 16.2.10 FIFO Data Count Register (SCFDR2) SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and SCFRDR2. The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show the number of receive data bytes in SCFRDR2. SCFDR2 can be read by the CPU at all times. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 T4 0 R 11 T3 0 R 10 T2 0 R 9 T1 0 R 8 T0 0 R These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 R4 0 R 3 R3 0 R 2 R2 0 R 1 R1 0 R 0 R0 0 R These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data. Rev. 6.0, 07/02, page 678 of 986 16.2.11 Serial Port Register (SCSPTR2) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 RTSIO Initial value: R/W: 0 R/W 14 -- 0 R 6 RTSDT -- R/W 13 -- 0 R 5 CTSIO 0 R/W 12 -- 0 R 4 CTSDT -- R/W 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 8 -- 0 R 0 SPB2IO SPB2DT 0 R/W -- R/W SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. Data can be read from, and output data written to, the &765 pin by means of bits 5 and 4. Data can be read from, and output data written to, the 5765 pin by means of bits 6 and 7. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8--Reserved: These bits are always read as 0, and should only be written with 0. Bit 7--Serial Port RTS Port I/O (RTSIO): Specifies the serial port 5765 pin input/output condition. When the 5765 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO 0 1 Description RTSDT bit value is not output to 5765 pin RTSDT bit value is output to 5765 pin (Initial value) Rev. 6.0, 07/02, page 679 of 986 Bit 6--Serial Port RTS Port Data (RTSDT): Specifies the serial port 5765 pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details). In output mode, the RTSDT bit value is output to the 5765 pin. The 5765 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 5--Serial Port CTS Port I/O (CTSIO): Specifies the serial port &765 pin input/output condition. When the &765 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO 0 1 Description CTSDT bit value is not output to &765 pin CTSDT bit value is output to &765 pin (Initial value) Bit 4--Serial Port CTS Port Data (CTSDT): Specifies the serial port &765 pin input/output data. Input or output is specified by the CTSIO bit (see the description of bit 5, CTSIO, for details). In output mode, the CTSDT bit value is output to the &765 pin. The &765 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT 0 1 Description Input/output data is low-level Input/output data is high-level Bits 3 and 2--Reserved: These bits are always read as 0, and should only be written with 0. Bit 1--Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO 0 1 Description SPB2DT bit value is not output to the TxD2 pin SPB2DT bit value is output to the TxD2 pin (Initial value) Rev. 6.0, 07/02, page 680 of 986 Bit 0--Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT 0 1 Description Input/output data is low-level Input/output data is high-level SCIF I/O port block diagrams are shown in figures 16.2 to 16.5. Reset R D7 Q D RTSIO C Internal data bus SPTRW MD8/ Reset R D6 Q D RTSDT C SCIF Modem control enable signal* signal SPTRW Mode setting register SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.2 MD8/5765 Pin 5765 Rev. 6.0, 07/02, page 681 of 986 Reset R Q D CTSIO C D5 Internal data bus SPTRW Reset R Q D CTSDT C D4 SCIF SPTRW signal Modem control enable signal* SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.3 &765 Pin Rev. 6.0, 07/02, page 682 of 986 Reset R Q D SPB2IO C D1 Internal data bus SPTRW MD1/TxD2 Reset R Q D SPB2DT C D0 SCIF Transmit enable signal SPTRW Mode setting register SPTRW: Write to SPTR Serial transmit data Figure 16.4 MD1/TxD2 Pin MD2/RxD2 SCIF Mode setting register D0 Internal data bus SPTRR SPTRR: Read SPTR Serial receive data Figure 16.5 MD2/RxD2 Pin Rev. 6.0, 07/02, page 683 of 986 16.2.12 Line Status Register (SCLSR2) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 ORER 0 (R/W)* Note: * Only 0 can be written, to clear the flag. Bits 15 to 1--Reserved: These bits are always read as 0, and should only be written with 0. Bit 0--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 0: ORER 0 Description Reception in progress, or reception has ended normally* [Clearing conditions] * * 1 Power-on reset or manual reset When 0 is written to ORER after reading ORER = 1 2 1 (Initial value) An overrun error occurred during reception* [Setting condition] When the next serial reception is completed while the receive FIFO is full Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. *2 The receive data prior to the overrun error is retained in SCFRDR2, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Rev. 6.0, 07/02, page 684 of 986 16.3 16.3.1 Operation Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. 5765 and &765 signals are also provided as modem control signals. The transmission format is selected using the serial mode register (SCSMR2), as shown in table 16.3. The SCIF clock source is determined by the CKE1 bit in the serial control register (SCSCR2), as shown in table 16.4. * Data length: Choice of 7 or 8 bits * Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receivedata-ready state, and breaks, during reception * Indication of the number of data bytes stored in the transmit and receive FIFO registers * Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock, and can output a clock with a frequency of 16 times the bit rate. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection SCSMR2 Settings Bit 6: CHR 0 Bit 5: PE 0 Bit 3: STOP 0 1 1 0 1 1 0 0 1 1 0 1 Yes 7-bit data No Yes Mode Asynchronous mode Data Length SCIF Transfer Format Multiprocessor Bit Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 8-bit data No Rev. 6.0, 07/02, page 685 of 986 Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection SCSCR2 Setting Bit 1: CKE1 0 1 Mode Asynchronous mode SCIF Transmit/Receive Clock Clock Source Internal External SCK2 Pin Function SCIF does not use SCK2 pin Inputs clock with frequency of 16 times the bit rate 16.3.2 Serial Operation Transmit/Receive Format Table 16.5 shows the transmit/receive formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR2 settings. Rev. 6.0, 07/02, page 686 of 986 Table 16.5 Serial Transmit/Receive Formats SCSMR2 Settings CHR PE 0 0 STOP 0 1 S 2 Serial Transmit/Receive Format and Frame Length 3 4 5 8-bit data 6 7 8 9 10 STOP 11 12 0 0 1 S 8-bit data STOP STOP 0 1 0 S 8-bit data P STOP 0 1 1 S 8-bit data P STOP STOP 1 0 0 S 7-bit data STOP 1 0 1 S 7-bit data STOP STOP 1 1 0 S 7-bit data P STOP 1 1 1 S 7-bit data P STOP STOP S: Start bit STOP: Stop bit P: Parity bit Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK2 pin can be selected as the SCIF's serial clock, according to the setting of the CKE1 bit in SCSCR2. For details of SCIF clock source selection, see table 16.4. When an external clock is input at the SCK2 pin, the clock frequency should be 16 times the bit rate used. Rev. 6.0, 07/02, page 687 of 986 Data Transfer Operations SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR2 to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR2 is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2, SCFTDR2, or SCFRDR2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR2 has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFRST bit in SCFCR2 should first be set to 1 to reset SCFTDR2. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 16.6 shows a sample SCIF initialization flowchart. Rev. 6.0, 07/02, page 688 of 986 Initialization 1. Set the clock selection in SCSCR2. Be sure to clear bits RIE and TIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR2 to 0 Set TFRST and RFRST bits in SCFCR2 to 1 Set CKE1 bit in SCSCR2 (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR2 Set value in SCBRR2 Wait 1-bit interval elapsed? Yes Set RTRG1-0, TTRG1-0, and MCE bits in SCFCR2 Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR2 to 1, and set RIE, TIE, and REIE bits No 2. Set the transmit/receive format in SCSMR2. 3. Write a value corresponding to the bit rate into SCBRR2. (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR2 to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the TxD2 and RxD2 pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. End Figure 16.6 Sample SCIF Initialization Flowchart Rev. 6.0, 07/02, page 689 of 986 Serial Data Transmission: Figure 16.7 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission 1. SCIF status check and transmit data write: Read SCFSR2 and check that the TDFE flag is set to 1, then write transmit data to SCFTDR2, read 1 from the TDFE and TEND flags, then clear these flags to 0. The number of transmit data bytes that can be written is 16 - (transmit trigger set number). 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR2, and then clear the TDFE flag to 0. 3. Break output at the end of serial transmission: No To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR2, then clear the TE bit in SCSCR2 to 0. In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR2 indicated by the upper 8 bits of SCFDR2. Read TDFE flag in SCFSR2 No TDFE = 1? Yes Write transmit data (16 - transmit trigger set number) to SCFTDR2, read 1 from TDFE flag and TEND flag in SCFSR2, then clear to 0 All data transmitted? Yes Read TEND flag in SCFSR2 No TEND = 1? Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 Clear TE bit in SCSCR2 to 0 No End of transmission Figure 16.7 Sample Serial Transmission Flowchart Rev. 6.0, 07/02, page 690 of 986 In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR2, the SCIF transfers the data from SCFTDR2 to SCTSR2 and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR2) is set to 1 before writing transmit data to SCFTDR2. The number of data bytes that can be written is at least 16 - transmit trigger setting. 2. When data is transferred from SCFTDR2 to SCTSR2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR2. When the number of transmit data bytes in SCFTDR2 falls to or below the transmit trigger number set in the FIFO control register (SCFCR2), the TDFE flag is set. If the TIE bit in SCSCR2 is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD2 pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR2 transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR2 to SCTSR2, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. Figure 16.8 shows an example of the operation for transmission in asynchronous mode. Rev. 6.0, 07/02, page 691 of 986 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR2 and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 16.8 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the &765 input value. When &765 is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When &765 is set to 0, the next transmit data is output starting from the start bit. Figure 16.9 shows an example of the operation when modem control is used. Start bit Serial data TxD2 0 D0 D1 Parity Stop bit bit D7 0/1 1 Start bit 0 D0 D1 D7 0/1 CTS2 Drive high before stop bit Figure 16.9 Example of Operation Using Modem Control (&765 &765) &765 Rev. 6.0, 07/02, page 692 of 986 Serial Data Reception: Figure 16.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, BRK flags in SCFSR2 and ORER flag in SCLSR2 ER or DR or BRK or ORER = 1? No Read RDF flag in SCFSR2 No Yes 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR2, and the ORER flag in SCLSR2, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD2 pin. 2. SCIF status check and receive data read : Read SCFSR2 and check that RDF = 1, then read the receive data in SCFRDR2, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR2, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR2 can be ascertained by reading the lower bits of SCFDR2. Error handling RDF = 1? Yes Read receive data in SCFRDR2, and clear RDF flag in SCFSR2 to 0 No All data received? Yes Clear RE bit in SCSCR2 to 0 End of reception Figure 16.10 Sample Serial Reception Flowchart (1) Rev. 6.0, 07/02, page 693 of 986 Error handling No 1. Whether a framing error or parity error has occurred that is to be read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2. 2. When a break signal is received, receive data is not transferred to SCFRDR2 while the BRK flag is set. However, note that the last data in SCFRDR2 is H'00 (the break data in which a framing error occurred is stored). ORER = 1? Yes Overrun error handling No ER = 1? Yes Receive error handling No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR2 Clear DR, ER, BRK flags in SCFSR2, and ORER flag in SCLSR2, to 0 End Figure 16.10 Sample Serial Reception Flowchart (2) Rev. 6.0, 07/02, page 694 of 986 In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR2) to SCFRDR2. c. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred. d. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If b, c, and d checks are passed, the receive data is stored in SCFRDR2. Note: Reception continues when parity error, framing error occurs. 4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 16.11 shows an example of the operation for reception in asynchronous mode. Rev. 6.0, 07/02, page 695 of 986 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 0/1 RDF FER RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the 5765 signal is output when SCFRDR2 is empty. When 5765 is 0, reception is possible. SH7750: When 5765 is 1, this indicates that SCFRDR2 contains 15 or more bytes of data. SH7750S, SH7750R: When 5765 is 1, this indicates that SCFRDR2 contains a number of data bytes equal to or greater than the 5765 output active trigger set number. The 5765 output active trigger value is specified by bits 10 to 8 in the FIFO control register (SCFCR2), described in section 16.2.9, FIFO control register (SCFCR2). 5765 also becomes 1 when bit 4 (RE) in SCSCR2 is 0. Figure 16.12 shows an example of the operation when modem control is used. Start bit Serial data RxD2 0 D0 D1 D2 Parity Stop bit bit D7 0/1 1 Start bit 0 Figure 16.12 Example of Operation Using Modem Control (5765 5765) 5765 Rev. 6.0, 07/02, page 696 of 986 16.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receiveerror interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 16.6 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR2. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When transmission/reception is carried out using the DMAC, output of interrupt requests to the interrupt controller can be inhibited by clearing the RIE bit in SCSCR2 to 0. By setting the REIE bit to 1 while the RIE bit is cleared to 0, it is possible to output ERI and BRI interrupt requests, but not RXI interrupt requests. When the TDFE flag in the serial status register (SCFSR2) is set to 1, a transmit-FIFO-data-empty request is generated separately from the interrupt request. A transmit-FIFO-data-empty request can activate the DMAC to perform data transfer. When the RDF flag or DR flag in SCFSR2 is set to 1, a receive-FIFO-data-full request is generated separately from the interrupt request. A receive-FIFO-data-full request can activate the DMAC to perform data transfer. When using the DMAC for transmission/reception, set and enable the DMAC before making the SCIF settings. See section 14, Direct Memory Access Controller (DMAC), for details of the DMAC setting procedure. When the BRK flag in SCFSR2 or the ORER flag in the line status register (SCLSR2) is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR2. Table 16.6 SCIF Interrupt Sources Interrupt Source ERI RXI BRI TXI Description Interrupt initiated by receive error flag (ER) Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready flag (DR) DMAC Activation Not possible Possible Priority on Reset Release High Interrupt initiated by break flag (BRK) or overrun Not possible error flag (ORER) Interrupt initiated by transmit FIFO data empty flag (TDFE) Possible Low Rev. 6.0, 07/02, page 697 of 986 See section 5, Exceptions, for priorities and the relationship with non-SCIF interrupts. 16.5 Usage Notes Note the following when using the SCIF. SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register (SCFSR2) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR2) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR2 can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR2 is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR2 contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the FIFO data count register (SCFDR2). SCFRDR2 Reading and the RDF Flag: The RDF flag in the serial status register (SCFSR2) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR2) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR2, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR2 is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read. The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count register (SCFDR2). Break Detection and Processing: Break signals can be detected by reading the RxD2 pin directly when a framing error (FER) is detected. In the break state the input from the RxD2 pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR2 after receiving a break, the receive operation continues. Sending a Break Signal: The input/output condition and level of the TxD2 pin are determined by bits SPB2IO and SPB2DT in the serial port register (SCSPTR2). This feature can be used to send a break signal. Rev. 6.0, 07/02, page 698 of 986 After the serial transmitter is initialized, the TxD2 pin function is not selected and the value of the SPB2DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized, regardless of its current state, and 0 is output from the TxD2 pin. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.13. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock -7.5 clocks +7.5 clocks Receive data (RxD2) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 - 1 | D - 0.5 | ) - (L - 0.5) F - (1 + F) x 100% ....................... (1) 2N N M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency Rev. 6.0, 07/02, page 699 of 986 From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 - 1 / (2 x 16) ) x 100% = 46.875% ............................................... (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. SCK2/05(6(7 As the manual reset pin is multiplexed with the SCK2 pin, a manual reset must 05(6(7: 05(6(7 not be executed while the SCIF is operating in external clock mode. When Using the DMAC: When using the DMAC for transmission/reception, inhibit output of RXI and TXI interrupt requests to the interrupt controller. If interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler. Serial Ports: Note that, when the SCIF pin value is read using a serial port, the value read will be the value two peripheral clock cycles earlier. Overrun Error Flag (SH7750): SCIF overrun error flag is not set in the case that overrun error and flaming error occurred simultaneously in receiving data, that means 17th byte data which overrun was accompanying with flaming error. In such case, only SCFSR2. ER flag which shows occurrence of flaming error is set. Receive FIFO stores data received before the overrun and does not store (i. e. lose) overrun data. SCIF has no bit which corresponds to SCFSR2. FER for the lost data. In addition to the overrun error handling software routine, exception handler should check cooccurrence of overrun error when a flaming error is occurred and when a co-occurrence is found, it should handle also overrun error (When (i) a overrun error solely occurred without accompanying with other receive error and (ii) when a parity error is accompanied with overrun error, usual overrun error handling can be used. Overrun error handling should rather be done primarily). Rev. 6.0, 07/02, page 700 of 986 Framing error occurrence Flow chart: When flaming error (SCFSR.ER=1) is occurred, bit7 to Bits 7 to 0 in SCFDR2 = H'10? Yes No bit0 should be read out from SCFDR2. If bit7 to bit0 equals H'10, contents of the receive FIFO should be read. When the data received last is not accompanied with flaming error (SCFSR2.FER=0) both overrun error Normal error handling handling and flaming error handling shoud be PER or FER bit in SCFSR2 set to 1? Yes conducted. No Error handling Read receive FIFO No Last data? Yes Overrun error handling + framing error handling Figure 16.14 Overrun Error Flag Rev. 6.0, 07/02, page 701 of 986 Rev. 6.0, 07/02, page 702 of 986 Section 17 Smart Card Interface 17.1 Overview The subset of the IC card (smart card) interface conforming to ISO/IEC7816-3 (Identification Card) is supported as a serial communication interface (SCI) extension function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 17.1.1 Features Features of the smart card interface are listed below. * Asynchronous mode Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * On-chip baud rate generator allows any bit rate to be selected * Three interrupt sources There are three interrupt sources--transmit-data-empty, receive-data-full, and transmit/receive error--that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute data transfer. Rev. 6.0, 07/02, page 703 of 986 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the smart card interface. Bus interface Module data bus Internal data bus SCRDR1 RxD SCRSR1 SCTDR1 SCTSR1 SCSCMR1 SCSSR1 SCSCR1 SCSMR1 SCSPTR1 Transmission/ reception control SCBRR1 P Baud rate generator P/4 P/16 P/64 TxD Parity generation Parity check SCK Clock External clock TXI RXI ERI SCI SCSCMR1: SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 17.1 Block Diagram of Smart Card Interface Rev. 6.0, 07/02, page 704 of 986 17.1.3 Pin Configuration Table 17.1 shows the smart card interface pin configuration. Table 17.1 Smart Card Interface Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation MD0/SCK RxD MD7/TxD I/O I/O Input Output Function Clock input/output Receive data input Transmit data output 17.1.4 Register Configuration The smart card interface has the internal registers shown in table 17.2. Details of the SCBRR1, SCTDR1, SCRDR1, and SCSPTR1 registers are the same as for the normal SCI function: see the register descriptions in section 15, Serial Communication Interface (SCI). With the exception of the serial port register, the smart card interface registers are initialized in standby mode and in the module standby state as well as by a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Table 17.2 Smart Card Interface Registers Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial port register Abbreviation SCSMR1 SCBRR1 SCSCR1 SCTDR1 SCSSR1 SCRDR1 SCSCMR1 SCSPTR1 R/W R/W R/W R/W R/W R/(W)* R R/W R/W 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00 2 H'00* P4 Address H'FFE00000 H'FFE00004 H'FFE00008 H'FFE0000C H'FFE00010 H'FFE00014 H'FFE00018 H'FFE0001C Area 7 Address H'1FE00000 H'1FE00004 H'1FE00008 H'1FE0000C H'1FE00010 H'1FE00014 H'1FE00018 H'1FE0001C Access Size 8 8 8 8 8 8 8 8 Notes: *1 Only 0 can be written, to clear flags. *2 The value of bits 2 and 0 is undefined. Rev. 6.0, 07/02, page 705 of 986 17.2 Register Descriptions Only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 Smart Card Mode Register (SCSCMR1) SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function. SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit: 7 -- Initial value: R/W: -- -- 6 -- -- -- 5 -- -- -- 4 -- -- -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- -- -- 0 SMIF 0 R/W Bits 7 to 4 and 1--Reserved: These bits are always read as 0, and should only be written with 0. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3: SDIR 0 1 Description SCTDR1 contents are transmitted LSB-first Receive data is stored in SCRDR1 LSB-first SCTDR1 contents are transmitted MSB-first Receive data is stored in SCRDR1 MSB-first (Initial value) Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the bit 3 function for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 17.3.4, Register Settings. Bit 2: SINV 0 1 Description SCTDR1 contents are transmitted as they are Receive data is stored in SCRDR1 as it is SCTDR1 contents are inverted before being transmitted Receive data is stored in SCRDR1 in inverted form (Initial value) Rev. 6.0, 07/02, page 706 of 986 Bit 0--Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0: SMIF 0 1 Description Smart card interface function is disabled Smart card interface function is enabled (Initial value) 17.2.2 Serial Mode Register (SCSMR1) Bit 7 of SCSMR1 has a different function in smart card interface mode. Bit: 7 GM(C/$) Initial value: R/W: 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/( 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7--GSM Mode (GM): Sets the smart card interface function to GSM mode. With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the TEND flag that indicates completion of transmission, and the type of clock output used. The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register (SCSCR1). In GSM mode, the pulse width is guaranteed when SCK start/stop specifications are made by CKE1 and CKE0. Bit 7: GM 0 Description Normal smart card interface mode operation * * 1 Clock output on/off control only (Initial value) The TEND flag is set 12.5 etu after the beginning of the start bit GSM mode smart card interface mode operation * * The TEND flag is set 11.0 etu after the beginning of the start bit Clock output on/off and fixed-high/fixed-low control (set in SCSCR1) Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. With the smart card interface, the following settings should be used: CHR = 0, PE = 1, STOP = 1, MP = 0. Rev. 6.0, 07/02, page 707 of 986 17.2.3 Serial Control Register (SCSCR1) Bits 1 and 0 of SCSCR1 have a different function in smart card interface mode. Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Bits 7 to 4: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bits 3 and 2--Reserved: Not used with the smart card interface. Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits specify the function of the SCK pin. In smart card interface mode, an internal clock is always used as the clock source. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. GM 0 CKE1 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 SCK Pin Function Port I/O pin Clock output as SCK output pin Invalid setting: must not be used Invalid setting: must not be used Output pin with output fixed low Clock output as output pin Output pin with output fixed high Clock output as output pin Rev. 6.0, 07/02, page 708 of 986 17.2.4 Serial Status Register (SCSSR1) Bit 4 of SCSSR1 has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2 (TEND) are also different. Bit: 7 TDRE Initial value: R/W: 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER/ ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 -- 0 R 0 -- 0 R/W Note: * Only 0 can be written, to clear the flag. Bits 7 to 5: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bit 4--Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4: ERS 0 Description Normal reception, no error signal [Clearing conditions] * * 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to ERS after reading ERS = 1 (Initial value) An error signal has been sent from the receiving side indicating detection of a parity error [Setting condition] * When the low level of the error signal is detected Note: Clearing the TE bit in SCSCR1 to 0 does not affect the ERS flag, which retains its previous state. Bit 3--Parity Error (PER): Operates in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Rev. 6.0, 07/02, page 709 of 986 Bit 2--Transmit End (TEND): The setting conditions for the TEND flag are as follows. Bit 2: TEND 0 Description Transmission in progress [Clearing condition] * 1 When 0 is written to TDRE after reading TDRE = 1 (Initial value) Transmission has been ended [Setting conditions] * * * Power-on reset, manual reset, standby mode, or module standby When the TE bit in SCSCR1 is 0 and the FER/ERS bit is also 0 When the GM bit in SCSMR1 is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character When the GM bit in SCSMR1 is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character * etu: Elementary Time Unit (time for transfer for 1 bit) Bits 1 and 0--Reserved: Not used with the smart card interface. 17.3 17.3.1 Operation Overview The main functions of the smart card interface are as follows. * One frame consists of 8-bit data plus a parity bit. * In transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for a 1-etu period 10.5 etu after the start bit. * If an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. * Only asynchronous communication is supported; there is no synchronous communication function. Rev. 6.0, 07/02, page 710 of 986 17.3.2 Pin Connections Figure 17.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected outside the chip. The data transmission line should be pulled up on the VCC power supply side with a resistor. When the clock generated on the smart card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. Chip port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Note: If an IC card is not connected, and both TE and RE are set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. VCC TxD Data line RxD SCK SH7750 Series Px (port) Clock line Reset line IO CLK RST IC card Connected equipment Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections Rev. 6.0, 07/02, page 711 of 986 17.3.3 Data Format Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data. If an error signal is detected during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Ds: D0-D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 17.3 Smart Card Interface Data Format The operation sequence is as follows. 1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. 2. The transmitting station starts transmission of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). 3. With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. 4. The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. Rev. 6.0, 07/02, page 712 of 986 If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. 5. If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it receives an error signal, however, it returns to step 2 and retransmits the erroneous data. 17.3.4 Register Settings Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 17.3 Smart Card Interface Register Settings Bit Register SCSMR1 SCBRR1 SCSCR1 SCTDR1 SCSSR1 SCRDR1 Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- -- Bit 4 O/( BRR4 RE TDR4 Bit 3 1 BRR3 0 TDR3 Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1 TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF SPB0DT FER/ERS PER RDR4 -- -- RDR3 SDIR SPB1IO SCSCMR1 -- SCSPTR1 EIO SPB1DT SPB0IO Note: A dash indicates an unused bit. Serial Mode Register (SCSMR1) Settings: The GM bit is used to select the timing of TEND flag setting, and, together with the CKE1 and CKE0 bits in the serial control register (SCSCR1), to select the clock output state. The O/( bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 17.3.5, Clock. Rev. 6.0, 07/02, page 713 of 986 I/O data Ds Da Db Dc Dd De Df Dg Dh Dp DE Guard time TXI (TEND interrupt) 12.5 etu GM = 0 11.0 etu GM = 1 etu: Elementary Time Unit (time for transfer for 1 bit) Figure 17.4 TEND Generation Timing Bit Rate Register (SCBRR1) Setting: SCBRR1 is used to set the bit rate. See section 17.3.5, Clock, for the method of calculating the value to be set. Serial Control Register (SCSCR1) Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. The CKE1 and CKE0 bits specify the clock output state. See section 17.3.5, Clock, for details. Smart Card Mode Register (SCSCMR1) Settings: The SDIR bit and SINV bit are both cleared to 0 if the IC card is of the direct convention type, and both set to 1 if of the inverse convention type. The SMIF bit is set to 1 when the smart card interface is used. Figure 17.5 shows examples of register settings and the waveform of the start character for the two types of IC card (direct convention and inverse convention). With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data in this case is H'3B. The parity bit is 1 since even parity is stipulated for the smart card. With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data in this case is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card. Inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/( bit in SCSMR1 is set to odd parity mode. (This applies to both transmission and reception). Rev. 6.0, 07/02, page 714 of 986 (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State (a) Direct convention (SDIR = SINV = O/ = 0) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State (b) Inverse convention (SDIR = SINV = O/ = 1) Figure 17.5 Sample Start Character Waveforms 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (SCBRR1) and the CKS1 and CKS0 bits in the serial mode register (SCSMR1). The equation for calculating the bit rate is shown below. Table 17.5 shows some sample bit rates. If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= P x 106 1488 x 22n-1 x (N + 1) Where: N = Value set in SCBRR1 (0 N 255) B = Bit rate (bits/s) P = Peripheral module operating frequency (MHz) n = 0 to 3 (See table 17.4) Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Rev. 6.0, 07/02, page 715 of 986 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) P (MHz) N 0 1 2 7.1424 9600.0 4800.0 3200.0 10.00 13440.9 6720.4 4480.3 10.7136 14400.0 7200.0 4800.0 14.2848 19200.0 9600.0 6400.0 25.0 33602.2 16801.1 11200.7 33.0 44354.8 22177.4 14784.9 50.0 67204.3 33602.2 22401.4 Note: Bit rates are rounded to one decimal place. The method of calculating the value to be set in the bit rate register (SCBRR1) from the peripheral module operating frequency and bit rate is shown below. Here, N is an integer in the range 0 N 255, and the smaller error is specified. N= P x 106 - 1 1488 x 22n-1 x B Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) P (MHz) 7.1424 Bits/s 9600 N 0 Error 0.00 N 1 10.00 Error 30.00 10.7136 N 1 Error 25.00 14.2848 N 1 Error 8.99 N 3 25.00 Error 14.27 N 4 33.00 Error 8.22 N 6 50.00 Error 0.01 Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) P (MHz) 7.1424 10.00 10.7136 16.00 20.00 25.0 30.0 33.0 50.0 Maximum Bit Rate (bits/s) 19200 26882 28800 43010 53763 67204 80645 88710 67204 N 0 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 0 Rev. 6.0, 07/02, page 716 of 986 The bit rate error is given by the following equation: P Error (%) = 1488 x 22n-1 x B x (N + 1) x 106 - 1 x 100 Table 17.8 shows the relationship between the smart card interface transmit/receive clock register settings and the output state. Table 17.8 Register Settings and SCK Pin State Register Values Setting 1* 1 SCK Pin CKE0 0 1 0 1 0 1 High output Low output Output Port State Determined by setting of SPB1IO and SPB1DT bits in SCSPTR1 SCK (serial clock) output state Low-level output state SCK (serial clock) output state High-level output state SCK (serial clock) output state SMIF 1 1 GM 0 0 1 1 1 1 CKE1 0 0 0 0 1 1 2 2* 1 1 3* 2 1 1 Notes: *1 The SCK output state changes as soon as the CKE0 bit setting is changed. Clear the CKE1 bit to 0. *2 Stopping and starting the clock by changing the CKE0 bit setting does not affect the clock duty cycle. Port value Width is undefined Width is undefined Port value SCK (a) When GM = 0 Specified width Specified width CKE1 value CKE1 value SCK (b) When GM = 1 Figure 17.6 Difference in Clock Output According to GM Bit Setting Rev. 6.0, 07/02, page 717 of 986 17.3.6 Data Transmit/Receive Operations Initialization: Before transmitting and receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. Figure 17.7 shows a sample initialization processing flowchart. 1. Clear the TE and RE bits in the serial control register (SCSCR1) to 0. 2. Clear error flags FER/ERS, PER, and ORER in the serial status register (SCSSR1) to 0. 3. Set the GM bit, parity bit (O/(), and baud rate generator select bits (CKS1 and CKS0) in the serial mode register (SCSMR1). Clear the CHR and MP bits to 0, and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR1). When the SMIF bit is set to 1, the TxD pin and RxD pin both go to the high-impedance state. 5. Set the value corresponding to the bit rate in the bit rate register (SCBRR1). 6. Set the clock source select bits (CKE1 and CKE0) in SCSCR1. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCSCR1. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev. 6.0, 07/02, page 718 of 986 Initialization Clear TE and RE bits in SCSCR1 to 0 Clear FER/ERS, PER, and ORER flags in SCSCR1 to 0 In SCSMR1, set parity in O/ bit, clock in CKS1 and CKS0 bits, and set GM Set SMIF, SDIR, and SINV bits in SCSCMR1 Set value in SCBRR1 In SCSCR1, set clock in CKE1 and CKE0 bits, and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. Wait 1-bit interval elapsed? Yes Set TIE, RIE, TE, and RE bits in SCSCR1 1 2 3 4 5 6 No 7 End Figure 17.7 Sample Initialization Flowchart Rev. 6.0, 07/02, page 719 of 986 Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.8 shows a sample transmission processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the FER/ERS error flag in SCSSR1 is cleared to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag in SCSSR1 is set to 1. 4. Write the transmit data to SCTDR1, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. 5. To continue transmitting data, go back to step 2. 6. To end transmission, clear the TE bit to 0. With the above processing, interrupt handling is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation in section 17.3.6 below for details. Rev. 6.0, 07/02, page 720 of 986 Start Initialization Start of transmission 2 FER/ERS = 0? Yes Error handling No TEND = 1? Yes Write transmit data to SCTDR1, and clear TDRE flag in SCSSR1 to 0 No All data transmitted? Yes FER/ERS = 0? Yes Error handling No TEND = 1? Yes Clear TE bit in SCSCR1 to 0 6 No 4 3 1 No 5 End of transmission Figure 17.8 Sample Transmission Processing Flowchart Rev. 6.0, 07/02, page 721 of 986 Serial Data Reception: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 17.9 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag in SCSSR1 are cleared to 0. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1. 4. Read the receive data from SCRDR1. 5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2. 6. To end reception, clear the RE bit to 0. With the above processing, interrupt handling is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation in section 17.3.6 below for details. If a parity error occurs during reception and the PER flag is set to 1, the received data is still transferred to SCRDR1, and therefore this data can be read. Rev. 6.0, 07/02, page 722 of 986 Start Initialization Start of reception 2 ORER = 0 and PER = 0? Yes Error handling No RDRF = 1? Yes Read receive data from SCRDR1 and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 6 4 3 No 1 5 End of reception Figure 17.9 Sample Reception Processing Flowchart Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. Rev. 6.0, 07/02, page 723 of 986 Interrupt Operation: There are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used in this mode. When the TEND flag in SCSSR1 is set to 1, a TXI interrupt request is generated. When the RDRF flag in SCSSR1 is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and FER/ERS in SCSSR1 is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 17.9. Table 17.9 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit mode Normal operation Error Receive mode Normal operation Error Flag TEND FER/ERS RDRF PER, ORER Mask Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI Data Transfer Operation by DMAC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC. In a transmit operation, when the TEND flag in SCSSR1 is set to 1, a TXI interrupt is requested. If the TXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TEND flag is automatically cleared to 0 when data transfer is performed by the DMAC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically, including retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and therefore the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SCSSR1 is set to 1. If the RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC. If an error occurs, an error flag is set but the RDRF flag is not. The DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. The error flag must therefore be cleared. When performing data transfer using the DMAC, it is essential to set and enable the DMAC before carrying out SCI settings. For details of the DMAC setting procedures, see section 14, Direct Memory Access Controller (DMAC). Rev. 6.0, 07/02, page 724 of 986 17.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. (1) Receive Data Sampling Timing and Receive Margin In asynchronous mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing is shown in figure 17.10. 372 clocks 186 clocks 0 Base clock 185 371 0 185 371 0 Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 17.10 Receive Data Sampling Timing in Smart Card Mode The receive margin in smart card mode can therefore be expressed as shown in the following equation. M = (0.5 - 1 | D - 0.5 | ) - (L - 0.5) F - (1 + F) x 100% 2N N M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 372) Clock duty cycle (D = 0 to 1.0) Frame length (L =10) Absolute deviation of clock frequency Rev. 6.0, 07/02, page 725 of 986 From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the following equation. When D = 0.5 and F = 0: M = (0.5 - 1/2 x 372) x 100% = 49.866% (2) Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. Retransfer Operation when SCI is in Receive Mode: Figure 17.11 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The PER bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred. 3. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is not set to 1. 4. If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an RXI interrupt request is generated. 5. When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer frame n+1 Ds D0 D1 D2 D3 D4 5 RDRF 2 PER 1 3 4 Figure 17.11 Retransfer Operation in SCI Receive Mode Rev. 6.0, 07/02, page 726 of 986 Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving side after transmission of one frame is completed, the FER/ERS bit in SCSSR1 is set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The FER/ERS bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The TEND bit in SCSSR1 is not set for a frame for which an error signal indicating an error is received. 3. If an error signal is not sent back from the receiving side, the FER/ERS bit in SCSSR1 is not set. 4. If an error signal is not sent back from the receiving side, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SCSSR1 is set to 1. If the TIE bit in SCSCR1 is enabled at this time, a TXI interrupt request is generated. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer frame n+1 Ds D0 D1 D2 D3 D4 TDRE Transfer from SCTDR1 to SCTSR1 TEND 2 FER/ERS 1 Transfer from SCTDR1 to SCTSR1 4 3 Transfer from SCTDR1 to SCTSR1 Figure 17.12 Retransfer Operation in SCI Transmit Mode Rev. 6.0, 07/02, page 727 of 986 (3) Standby Mode and Clock When switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. Switching from Smart Card Interface Mode to Standby Mode: 1. Set the SBP1IO and SBP1DT bits in SCSPTR1 to the values for the fixed output state in standby mode. 2. Write 0 to the TE and RE bits in the serial control register (SCSCR1) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in standby mode. 3. Write 0 to the CKE0 bit in SCSCR1 to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. Write H'00 to the serial mode register (SCSMR1) and smart card mode register (SCSMR1). 6. Make the transition to the standby state. Returning from Standby Mode to Smart Card Interface Mode: 7. Clear the standby state. 8. Set the CKE1 bit in SCSCR1 to the value for the fixed output state at the start of standby (the current SCK pin state). 9. Set smart card interface mode and output the clock. Clock signal generation is started with the normal duty cycle. Standby mode Normal operation Normal operation 123 4 56 7 89 Figure 17.13 Procedure for Stopping and Restarting the Clock Rev. 6.0, 07/02, page 728 of 986 (4) Power-On and Clock The following procedure should be used to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in the serial control register (SCSCR1). 3. Set the serial mode register (SCSMR1) and smart card mode register (SCSCMR1), and switch to smart card mode operation. 4. Set the CKE0 bit in SCSCR1 to 1 to start clock output. Rev. 6.0, 07/02, page 729 of 986 Rev. 6.0, 07/02, page 730 of 986 Section 18 I/O Ports 18.1 Overview The SH7750 Series has a 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port. 18.1.1 Features The features of the general-purpose I/O port are as follows: * 20-bit I/O port with input/output direction independently specifiable for each bit * Pull-up can be specified independently for each bit. * Interrupt input is possible for 16 of the 20 I/O port bits. * Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2 (BCR2). The features of the SCI I/O port are as follows: * Data can be output when the I/O port is designated for output and SCI enabling has not been set. This allows break function transmission. * The RxD pin value can be read at all times, allowing break state detection. * SCK pin control is possible when the I/O port is designated for output and SCI enabling has not been set. * The SCK pin value can be read at all times. The features of the SCIF I/O port are as follows: * Data can be output when the I/O port is designated for output and SCIF enabling has not been set. This allows break function transmission. * The RxD2 pin value can be read at all times, allowing break state detection. * &765 and 5765 pin control is possible when the I/O port is designated for output and SCIF enabling has not been set. * The &765 and 5765 pin values can be read at all times. Rev. 6.0, 07/02, page 731 of 986 18.1.2 Block Diagrams Figure 18.1 shows a block diagram of the 16-bit general-purpose I/O port. PBnPUP PORTEN Pull-up resistor Internal bus PDTRW DQ C BCK 1 1 PBnIO 0 Data input strobe C D BCK MPX 1 Q Interrupt controller PTIRENn Dn input data PORTEN PBnPuP DnDIR PBnIO PTIRENn 0: Port not available 0: Pull-up 0: Input 0: Input 0: Interrupt input disabled 1: Port available 1: Pull-up off 1: Output 1: Output 1: Interrupt input enabled Figure 18.1 16-Bit Port Rev. 6.0, 07/02, page 732 of 986 MPX DnDIR 0 MPX Dn output data 0 Port 15 (input/ output)/D47 to Port 0 (input/ output)/D32 Figure 18.2 shows a block diagram of the 4-bit general-purpose I/O port. PBnPUP PORTEN Pull-up resistor Internal bus MPX Dn output data DQ C BCK 0 1 PDTRW Port 19 (input/ output)/D51 to Port 16 (input/ output)/D48 1 PBnIO 0 Data input strobe C QD BCK MPX 1 Dn input data PORTEN PBnPuP DnDIR PBnIO 0: Port not available 0: Pull-up 0: Input 0: Input 1: Port available 1: Pull-up off 1: Output 1: Output Figure 18.2 4-Bit Port MPX DnDIR 0 Rev. 6.0, 07/02, page 733 of 986 SCI I/O port block diagrams are shown in figures 18.3 to 18.5. Reset R Q D SPB1IO C Internal data bus SPTRW Reset MD0/SCK D SPB1DT C SPTRW Mode setting register Q R SCI Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal * SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/ bit in SCSMR1. Figure 18.3 MD0/SCK Pin Rev. 6.0, 07/02, page 734 of 986 Reset R Q D SPB0IO C SPTRW MD7/TxD Reset R Q D SPB0DT C SPTRW Mode setting register Serial transmit data SPTRW: Write to SPTR Internal data bus SCI Transmit enable signal Figure 18.4 MD7/TxD Pin RxD SCI Serial receive data Internal data bus SPTRR SPTRR: Read SPTR Figure 18.5 RxD Pin Rev. 6.0, 07/02, page 735 of 986 SCIF I/O port block diagrams are shown in figures 18.6 to 18.9. Reset R Q D SPB2IO C Internal data bus SPTRW MD1/TxD2 Reset R Q D SPB2DT C SCIF Transmit enable signal SPTRW Mode setting register SPTRW: Write to SPTR Serial transmit data Figure 18.6 MD1/TxD2 Pin MD2/RxD2 SCIF Mode setting register Serial receive data Internal data bus SPTRR SPTRR: Read SPTR Figure 18.7 MD2/RxD2 Pin Rev. 6.0, 07/02, page 736 of 986 Reset R Q D CTSIO C Internal data bus SPTRW Reset R Q D CTSDT C SCIF SPTRW signal Modem control enable signal* SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the pin function. Figure 18.8 &765 Pin Rev. 6.0, 07/02, page 737 of 986 Reset R Q D RTSIO C Internal data bus SPTRW MD8/ Reset R Q D RTSDT C SCIF Modem control enable signal* SPTRW Mode setting register signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the pin function. Figure 18.9 MD8/5765 Pin 5765 Rev. 6.0, 07/02, page 738 of 986 18.1.3 Pin Configuration Table 18.1 shows the 20-bit general-purpose I/O port pin configuration. Table 18.1 20-Bit General-Purpose I/O Port Pins Pin Name Port 19 pin Port 18 pin Port 17 pin Port 16 pin Port 15 pin Port 14 pin Port 13 pin Port 12 pin Port 11 pin Port 10 pin Port 9 pin Port 8 pin Port 7 pin Port 6 pin Port 5 pin Port 4 pin Port 3 pin Port 2 pin Port 1 pin Port 0 pin Signal PORT19/D51 PORT18/D50 PORT17/D49 PORT16/D48 PORT15/D47 PORT14/D46 PORT13/D45 PORT12/D44 PORT11/D43 PORT10/D42 PORT9/D41 PORT8/D40 PORT7/D39 PORT6/D38 PORT5/D37 PORT4/D36 PORT3/D35 PORT2/D34 PORT1/D33 PORT0/D32 I/O I/O I/O I/O I/O I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* Function I/O port I/O port I/O port I/O port I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt Note: * When port pins are used as GPIO interrupts, they must be set to input mode. The input setting can be made in the PCTRA register. Rev. 6.0, 07/02, page 739 of 986 Table 18.2 shows the SCI I/O port pin configuration. Table 18.2 SCI I/O Port Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation MD0/SCK RxD MD7/TxD I/O I/O Input Output Function Clock input/output Receive data input Transmit data output Note: Pins MD0/SCK and MD7/TxD function as mode input pins MD0 and MD7 after a power-on reset. They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/$ bit in SCSMR1. Break state transmission and detection can be performed by means of a setting in the SCI's SCSPTR1 register. Table 18.3 shows the SCIF I/O port pin configuration. Table 18.3 SCIF I/O Port Pins Pin Name Serial clock pin Receive data pin Transmit data pin Modem control pin Modem control pin Abbreviation 05(6(7/SCK2 MD2/RxD2 MD1/TxD2 &765 MD8/5765 I/O Input Input Output I/O I/O Function Clock input Receive data input Transmit data output Transmission enabled Transmission request Note: The MRESET/SCK2 pin functions as the 05(6(7 manual reset pin when a manual reset is executed. The MD1/TxD2, MD2/RxD2, and MD8/5765 pins function as the MD1, MD2, and MD8 mode input pins after a power-on reset. These pins are made to function as serial pins by performing SCIF operation settings with the TE and RE bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. Rev. 6.0, 07/02, page 740 of 986 18.1.4 Register Configuration The 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port have seven registers, as shown in table 18.4. Table 18.4 I/O Port Registers Name Port control register A Port data register A Port control register B Port data register B GPIO interrupt control register Serial port register Serial port register Abbreviation R/W PCTRA PDTRA PCTRB PDTRB GPIOIC SCSPTR1 SCSPTR2 R/W R/W R/W R/W R/W R/W R/W Initial Value* P4 Address H'00000000 Undefined H'00000000 Undefined H'00000000 Undefined Undefined Area 7 Address Access Size H'FF80002C H'1F80002C 32 H'FF800030 H'FF800040 H'FF800044 H'FF800048 H'1F800030 H'1F800040 H'1F800044 H'1F800048 16 32 16 16 H'FFE0001C H'1FE0001C 8 H'FFE80020 H'1FE80020 16 Note: * Initialized by a power-on reset. Rev. 6.0, 07/02, page 741 of 986 18.2 18.2.1 Register Descriptions Port Control Register A (PCTRA) Port control register A (PCTRA) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port (port 15 pin to port 0 pin). As the initial value of port data register A (PDTRA) is undefined, all the bits in the 16-bit port should be set to output with PCTRA after writing a value to the PDTRA register. PCTRA is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: 31 30 29 28 27 26 25 24 PB15PUP PB15IO PB14PUP PB14IO PB13PUP PB13IO PB12PUP PB12IO Initial value: R/W: Bit: 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 PB9PUP 0 R/W 18 PB9IO 0 R/W 17 PB8PUP 0 R/W 16 PB8IO PB11PUP PB11IO PB10PUP PB10IO Initial value: R/W: Bit: 0 R/W 15 PB7PUP 0 R/W 14 PB7IO 0 R/W 13 PB6PUP 0 R/W 12 PB6IO 0 R/W 11 PB5PUP 0 R/W 10 PB5IO 0 R/W 9 PB4PUP 0 R/W 8 PB4IO Initial value: R/W: Bit: 0 R/W 7 PB3PUP 0 R/W 6 PB3IO 0 R/W 5 PB2PUP 0 R/W 4 PB2IO 0 R/W 3 PB1PUP 0 R/W 2 PB1IO 0 R/W 1 PB0PUP 0 R/W 0 PB0IO Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 6.0, 07/02, page 742 of 986 Bit 2n + 1 (n = 0-15)--Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP 0 1 Description Bit m (m = 0-15) of 16-bit port is pulled up Bit m (m = 0-15) of 16-bit port is not pulled up (Initial value) Bit 2n (n = 0-15)--Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port is an input or an output. Bit 2n: PBnIO 0 1 Description Bit m (m = 0-15) of 16-bit port is an input Bit m (m = 0-15) of 16-bit port is an output (Initial value) 18.2.2 Port Data Register A (PDTRA) Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit in the 16-bit port. When a bit is set as an output, the value written to the PDTRA register is output from the external pin. When a value is read from the PDTRA register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRA register is read. PDTRA is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 14 13 12 11 10 9 8 PB8DT -- R/W 0 PB0DT -- R/W PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT PB9DT Initial value: R/W: Bit: -- R/W 7 PB7DT Initial value: R/W: -- R/W -- R/W 6 PB6DT -- R/W -- R/W 5 PB5DT -- R/W -- R/W 4 PB4DT -- R/W -- R/W 3 PB3DT -- R/W -- R/W 2 PB2DT -- R/W -- R/W 1 PB1DT -- R/W Rev. 6.0, 07/02, page 743 of 986 18.2.3 Port Control Register B (PCTRB) Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 4-bit port (port 19 pin to port 16 pin). As the initial value of port data register B (PDTRB) is undefined, each bit in the 4-bit port should be set to output with PCTRB after writing a value to the PDTRB register. PCTRB is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: 31 -- Initial value: R/W: Bit: 0 R 23 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: Bit: 0 R 7 30 -- 0 R 22 -- 0 R 14 -- 0 R 6 29 -- 0 R 21 -- 0 R 13 -- 0 R 5 28 -- 0 R 20 -- 0 R 12 -- 0 R 4 27 -- 0 R 19 -- 0 R 11 -- 0 R 3 26 -- 0 R 18 -- 0 R 10 -- 0 R 2 25 -- 0 R 17 -- 0 R 9 -- 0 R 1 24 -- 0 R 16 -- 0 R 8 -- 0 R 0 PB19PUP PB19IO PB18PUP PB18IO PB17PUP PB17IO PB16PUP PB16IO Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 2n + 1 (n = 0-3)--Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 4-bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP 0 1 Description Bit m (m = 16-19) of 4-bit port is pulled up Bit m (m = 16-19) of 4-bit port is not pulled up (Initial value) Rev. 6.0, 07/02, page 744 of 986 Bit 2n (n = 0-3)--Port I/O Control (PBnIO): Specifies whether each bit in the 4-bit port is an input or an output. Bit 2n: PBnIO 0 1 Description Bit m (m = 16-19) of 4-bit port is an input Bit m (m = 16-19) of 4-bit port is an output (Initial value) 18.2.4 Port Data Register B (PDTRB) Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit in the 4-bit port. When a bit is set as an output, the value written to the PDTRB register is output from the external pin. When a value is read from the PDTRB register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRB register is read. PDTRB is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 PB19DT PB18DT PB17DT PB16DT -- R/W -- R/W -- R/W -- R/W 18.2.5 GPIO Interrupt Control Register (GPIOIC) The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs 16-bit interrupt input control. GPIOIC is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. GPIO interrupts are active-low level interrupts. Bit-by-bit masking is possible, and the OR of all the bits set as GPIO interrupts is used for interrupt detection. Which bits interrupts are input to can be identified by reading the PDTRA register. Rev. 6.0, 07/02, page 745 of 986 Bit: 15 14 13 12 11 10 9 8 PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 PTIREN8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 PTIREN7 PTIREN6 PTIREN5 PTIREN4 PTIREN3 PTIREN2 PTIREN1 PTIREN0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit n (n = 0-15)--Port Interrupt Enable (PTIRENn): Specifies whether interrupt input is performed for each bit. Bit n: PTIRENn 0 1 Description Port m (m = 0-15) of 16-bit port is used as a normal I/O port (Initial value) Port m (m = 0-15) of 16-bit port is used as a GPIO interrupt* Note: * When using an interrupt, set the corresponding port to input in the PCTRA register before making the PTIRENn setting. 18.2.6 Serial Port Register (SCSPTR1) Bit: 7 EIO Initial value: R/W: 0 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 2 1 0 SPB1IO SPB1DT SPB0IO SPB0DT 0 R/W -- R/W 0 R/W -- R/W The serial port register (SCSPTR1) is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to H'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7--Error Interrupt Only (EIO): See section 15.2.8, Serial Port Register (SCSPTR1). Bits 6 to 4--Reserved: These bits are always read as 0, and should only be written with 0. Rev. 6.0, 07/02, page 746 of 986 Bit 3--Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO 0 1 Description SPB1DT bit value is not output to the SCK pin SPB1DT bit value is output to the SCK pin (Initial value) Bit 2--Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 2: SPB1DT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 1--Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO 0 1 Description SPB0DT bit value is not output to the TxD pin SPB0DT bit value is output to the TxD pin (Initial value) Bit 0--Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB0DT 0 1 Description Input/output data is low-level Input/output data is high-level Rev. 6.0, 07/02, page 747 of 986 18.2.7 Serial Port Register (SCSPTR2) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 RTSIO Initial value: R/W: 0 R/W 14 -- 0 R 6 RTSDT -- R/W 13 -- 0 R 5 CTSIO 0 R/W 12 -- 0 R 4 CTSDT -- R/W 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 8 -- 0 R 0 SPB2IO SPB2DT 0 R/W -- R/W The serial port register (SCSPTR2) is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. &765 pin data reading and output data writing can be performed by means of bits 5 and 4, and 5765 pin data reading and output data writing by means of bits 7 and 6. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8--Reserved: These bits are always read as 0, and should only be written with 0. Bit 7--Serial Port RTS Port I/O (RTSIO): Specifies serial port 5765 pin input/output. When the 5765 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO 0 1 Description RTSDT bit value is not output to the 5765 pin RTSDT bit value is output to the 5765 pin (Initial value) Rev. 6.0, 07/02, page 748 of 986 Bit 6--Serial Port RTS Port Data (RTSDT): Specifies the serial port 5765 pin input/output data. Input or output is specified by the RTSIO pin (see the description of bit 7, RTSIO, for details). When the 5765 pin is designated as an output, the value of the RTSDT bit is output to the 5765 pin. The 5765 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 5--Serial Port CTS Port I/O (CTSIO): Specifies serial port &765 pin input/output. When the &765 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO 0 1 Description CTSDT bit value is not output to the &765 pin CTSDT bit value is output to the &765 pin (Initial value) Bit 4--Serial Port CTS Port Data (CTSDT): Specifies the serial port &765 pin input/output data. Input or output is specified by the CTSIO pin (see the description of bit 5, CTSIO, for details). When the &765 pin is designated as an output, the value of the CTSDT bit is output to the &765 pin. The &765 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT 0 1 Description Input/output data is low-level Input/output data is high-level Bits 3 and 2--Reserved: These bits are always read as 0, and should only be written with 0. Bit 1--Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO 0 1 Description SPB2DT bit value is not output to the TxD2 pin SPB2DT bit value is output to the TxD2 pin (Initial value) Rev. 6.0, 07/02, page 749 of 986 Bit 0--Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT 0 1 Description Input/output data is low-level Input/output data is high-level Rev. 6.0, 07/02, page 750 of 986 Section 19 Interrupt Controller (INTC) 19.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority. 19.1.1 Features The INTC has the following features. * Fifteen interrupt priority levels can be set By setting the three interrupt priority registers, the priorities of on-chip peripheral module interrupts can be selected from 15 levels for different request sources. * NMI noise canceler function The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading this bit in the interrupt exception service routine, enabling it to be used as a noise canceler. * NMI request masking when SR.BL bit is set to 1 It is possible to select whether or not NMI requests are to be masked when the SR.BL bit is set to 1. 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the INTC. Rev. 6.0, 07/02, page 751 of 986 NMI - 4 TMU RTC SCI SCIF WDT REF DMAC H-UDI GPIO (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Priority identifier Comparator Interrupt request SR I3 I2 I1 I0 CPU Input control 4 IPR ICR IPRA-IPRD*1 INTPRI00*2 Internal bus Bus interface INTC TMU: Timer unit RTC: Realtime clock unit SCI: Serial communication interface SCIF: Serial communication interface with FIFO WDT: Watchdog timer REF: Memory refresh controller section of the bus state controller DMAC: Direct memory access controller H-UDI: Hitachi user debug interface GPIO: I/O port ICR: Interrupt control register IPRA-IPRD: Interrupt priority registers A-D*1 INTPRI00: Interrupt priority level setting register 00*2 SR: Status register Notes: *1 IPRD is provided only in the SH7750S and SH7750R. *2 INTPRI00 is provided only in the SH7750R. Figure 19.1 Block Diagram of INTC Rev. 6.0, 07/02, page 752 of 986 19.1.3 Pin Configuration Table 19.1 shows the INTC pin configuration. Table 19.1 INTC Pins Pin Name Nonmaskable interrupt input pin Interrupt input pins Abbreviation NMI ,5/6-,5/3 I/O Input Input Function Input of nonmaskable interrupt request signal Input of interrupt request signals (maskable by I3-I0 in SR) 19.1.4 Register Configuration The INTC has the registers shown in table 19.2. Table 19.2 INTC Registers 1 Initial Value* Name Interrupt control register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority 3 register D* Interrupt priority level setting 4 register 00* Interrupt source 4 register 00* Interrupt mask 4 register 00* Abbreviation ICR IPRA IPRB IPRC IPRD INTPRI00 R/W R/W R/W R/W R/W R/W R/W *2 H'0000 H'0000 H'0000 H'DA74 H'00000000 P4 Address H'FFD00000 H'FFD00004 H'FFD00008 H'FFD0000C H'FFD00010 H'FE080000 Area 7 Address H'1FD00000 H'1FD00004 H'1FD00008 H'1FD0000C H'1FD00010 H'1E080000 Access Size 16 16 16 16 16 32 INTREQ00 INTMSK00 R R/W H'00000000 H'00000300 -- H'FE080020 H'FE080040 H'FE080060 H'1E080020 H'1E080040 H'1E080060 32 32 32 Interrupt mask INTMSKCLR00 R 4 clear register 00* Notes: *1 *2 *3 *4 Initialized by a power-on reset or manual reset. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low. SH7750S and SH7750R only SH7750R only Rev. 6.0, 07/02, page 753 of 986 19.2 Interrupt Sources There are three types of interrupt sources: NMI, RL, and on-chip peripheral modules. Each interrupt has a priority level (16-0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 19.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in the status register in the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if the BL bit is set to 1. A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in the interrupt control register (ICR) is used to select either rising or falling edge. When the NMIE bit in the ICR register is modified, the NMI interrupt is not detected for a maximum of 6 bus clock cycles after the modification. NMI interrupt exception handling does not affect the interrupt mask level bits (I3-I0) in the status register (SR). Rev. 6.0, 07/02, page 754 of 986 19.2.2 IRL Interrupts IRL interrupts are input by level at pins ,5/6-,5/3. The priority level is the level indicated by pins ,5/6-,5/3. An ,5/6-,5/3 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). SH7750 Series Interrupt requests Priority encoder 4 to to Figure 19.2 Example of IRL Interrupt Connection Rev. 6.0, 07/02, page 755 of 986 Table 19.3 ,5/6 ,5/3 Pins and Interrupt Levels ,5/6-,5/3 ,5/6 0 ,5/5 0 ,5/4 0 ,5/3 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Interrupt Priority Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request Level 7 interrupt request Level 6 interrupt request Level 5 interrupt request Level 4 interrupt request Level 3 interrupt request Level 2 interrupt request Level 1 interrupt request No interrupt request A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no transient level on the ,5/ pin change is detected. In standby mode, as the bus clock is stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead. When the RTC is not used, therefore, interruption by means of IRL interrupts cannot be performed in standby mode. The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts. However, the priority level can be changed to a higher one. The interrupt mask bits (I3-I0) in the status register (SR) are not affected by IRL interrupt handling. Pins ,5/3-,5/6 can be used for four independent interrupt requests by setting the IRLM bit to 1 in the ICR register. When independent interrupt requests are used in the SH7750, the interrupt priority levels are fixed (table 19.4). When independent interrupt requests are used in the SH7750S or SH7750R, the interrupt priority levels can be set in interrupt priority register D (IPRD). Rev. 6.0, 07/02, page 756 of 986 Table 19.4 SH7750 ,5/6-,5/3 Pins and Interrupt Levels (When IRLM = 1) ,5/6 ,5/3 ,5/6 1/0 1/0 1/0 0 ,5/5 1/0 1/0 0 1 ,5/4 1/0 0 1 1 ,5/3 0 1 1 1 Interrupt Priority Level 13 10 7 4 Interrupt Request IRL0 IRL1 IRL2 IRL3 19.2.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following nine modules: * Hitachi user debug interface (H-UDI) * Direct memory access controller (DMAC) * Timer unit (TMU) * Realtime clock (RTC) * Serial communication interface (SCI) * Serial communication interface with FIFO (SCIF) * Bus state controller (BSC) * Watchdog timer (WDT) * I/O port (GPIO) Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register value as a branch offset in the exception handling routine. A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A to D (IPRA-IPRD), 00 (INTPRI00). The interrupt mask bits (I3-I0) in the status register (SR) are not affected by on-chip peripheral module interrupt handling. On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the BL bit to 0. In the case of interrupts on channel 3 or 4 of the TMU, also read from the interrupt source register 00 (INTREQ00). This will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read. Rev. 6.0, 07/02, page 757 of 986 If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT register value is 0. In this case, interrupt handling is initiated due to the timing relationship between the flag update and interrupt request recognition within the chip. Processing can be continued without any problem by executing an RTE instruction. 19.2.4 Interrupt Exception Handling and Priority Table 19.5 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned a unique INTEVT code. The start address of the interrupt handler is common to each interrupt source. This is why, for instance, the value of INTEVT is used as an offset at the start of the interrupt handler and branched to in order to identify the interrupt source. The order of priority of the on-chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority registers A to D (IPRA-IPRD). The order of priority of the on-chip peripheral modules is set to 0 by a reset. When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 19.5. Updating of interrupt priority registers A to D, 00 should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt priority registers, then clear the BL bit to 0. This will secure the necessary timing internally. Rev. 6.0, 07/02, page 758 of 986 Table 19.5 Interrupt Exception Handling Sources and Priority Order Interrupt Source NMI IRL INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) H'1C0 ,5/6-,5/3 = 0 H'200 ,5/6-,5/3 = 1 H'220 ,5/6-,5/3 = 2 H'240 ,5/6-,5/3 = 3 H'260 ,5/6-,5/3 = 4 H'280 ,5/6-,5/3 = 5 H'2A0 ,5/6-,5/3 = 6 H'2C0 ,5/6-,5/3 = 7 H'2E0 ,5/6-,5/3 = 8 H'300 ,5/6-,5/3 = 9 H'320 ,5/6-,5/3 = A H'340 ,5/6-,5/3 = B H'360 ,5/6-,5/3 = C H'380 ,5/6-,5/3 = D H'3A0 ,5/6-,5/3 = E H'3C0 IRL0 IRL1 IRL2 IRL3 H-UDI GPIO DMAC H-UDI GPIOI DMTE0 DMTE1 DMTE2 DMTE3 DMTE4* 2 2 DMTE5* 2 DMTE6* 2 DMTE7* Priority within IPR Setting Unit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 Default Priority High Low 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15-0 (13)* 15-0 (10)* 15-0 (7)* 15-0 (4)* 15-0 (0) 15-0 (0) 15-0 (0) 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H'240 H'2A0 H'300 H'360 H'600 H'620 H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 IPRD (15-12)* -- IPRD (11-8)* IPRD (7-4)* IPRD (3-0)* IPRC (3-0) 1 1 -- -- -- -- IPRC (15-12) -- IPRC (11-8) High Low DMAE Rev. 6.0, 07/02, page 759 of 986 Table 19.5 Interrupt Exception Handling Sources and Priority Order (cont) Interrupt Source TMU3 TMU4 TMU0 TMU1 TMU2 TUNI3* TUNI4* TUNI0 TUNI1 TUNI2 TICPI2 RTC ATI PRI CUI SCI1 ERI RXI TXI TEI SCIF ERI RXI BRI TXI WDT REF ITI RCMI ROVI 2 INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) H'B00 H'B80 H'400 H'420 H'440 H'460 H'480 H'4A0 H'4C0 H'4E0 H'500 H'520 H'540 H'700 H'720 H'740 H'760 H'560 H'580 H'5A0 15-0 (0) 15-0 (0) IPRB (15-12) IPRB (11-8) 15-0 (0) IPRC (7-4) 15-0 (0) IPRB (7-4) 15-0 (0) IPRA (3-0) 15-0 (0) 15-0 (0) 15-0 (0) 15-0 (0) 15-0 (0) INTPRI00 (11-8) INTPRI00 (15-12) IPRA (15-12) IPRA (11-8) IPRA (7-4) Priority within IPR Setting Unit -- -- -- -- High Low High Low High Low High Low -- High Low Default Priority High Low 2 Notes: TUNI0-TUNI4: Underflow interrupts TICPI2: Input capture interrupt ATI: Alarm interrupt PRI: Periodic interrupt CUI: Carry-up interrupt ERI: Receive-error interrupt RXI: Receive-data-full interrupt TXI: Transmit-data-empty interrupt TEI: Transmit-end interrupt BRI: Break interrupt request ITI: Interval timer interrupt RCMI: Compare-match interrupt ROVI: Refresh counter overflow interrupt Rev. 6.0, 07/02, page 760 of 986 H-UDI: Hitachi use debug interface GPIOI: I/O port interrupt DMTE0-DMTE7: DMAC transfer end interrupts DMAE: DMAC address error interrupt *1 Interrupt priority levels can only be changed in the SH7750S or SH7750R. In the SH7750, the initial values cannot be changed. *2 SH7750R only 19.3 19.3.1 Register Descriptions Interrupt Priority Registers A to D (IPRA-IPRD) Interrupt priority registers A to D (IPRA-IPRD) are 16-bit readable/writable registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode. IPRA to IPRC Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W IPRD (SH7750S and SH7750R only) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 1 R/W 7 0 R/W 14 1 R/W 6 1 R/W 13 0 R/W 5 1 R/W 12 1 R/W 4 1 R/W 11 1 R/W 3 0 R/W 10 0 R/W 2 1 R/W 9 1 R/W 1 0 R/W 8 0 R/W 0 0 R/W Rev. 6.0, 07/02, page 761 of 986 Table 19.6 shows the relationship between the interrupt request sources and the IPRA-IPRD register bits. Table 19.6 Interrupt Request Sources and IPRA-IPRD Registers Bits Register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D* 3 15-12 TMU0 WDT GPIO IRL0 11-8 TMU1 REF* IRL1 1 7-4 TMU2 SCI1 SCIF IRL2 3-0 RTC 2 Reserved* DMAC H-UDI IRL3 Notes: *1 REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus State Controller (BSC), for details. *2 Reserved bits: These bits are always read as 0 and should always be written with 0. *3 SH7750S and SH7750R only As shown in table 19.6, four on-chip peripheral modules are assigned to each register. Interrupt priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the fourbit groups: 15-12, 11-8, 7-4, and 3-0. Setting H'F designates priority level 15 (the highest level), and setting H'0 designates priority level 0 (requests are masked). 19.3.2 Interrupt Control Register (ICR) The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register is initialized by a power-on reset or manual reset. It is not initialized in standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 NMIL 0/1* R 7 IRLM 0 R/W 14 MAI 0 R/W 6 -- 0 -- 13 -- 0 -- 5 -- 0 -- 12 -- 0 -- 4 -- 0 -- 11 -- 0 -- 3 -- 0 -- 10 -- 0 -- 2 -- 0 -- 9 NMIB 0 R/W 1 -- 0 -- 8 NMIE 0 R/W 0 -- 0 -- Note: * 1 when NMI pin input is high, 0 when low. Rev. 6.0, 07/02, page 762 of 986 Bit 15--NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. It cannot be modified. Bit 15: NMIL 0 1 Description NMI pin input level is low NMI pin input level is high Bit 14--NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked while the NMI pin input level is low, irrespective of the CPU's SR.BL bit. Bit 14: MAI 0 1 Description Interrupts enabled even while NMI pin is low Interrupts disabled while NMI pin is low* (Initial value) Note: * NMI interrupts are accepted in normal operation and in sleep mode. In standby mode, all interrupts are masked, and standby is not cleared, while the NMI pin is low. Bit 9--NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or detected immediately while the SR.BL bit is set to 1. Bit 9: NMIB 0 1 Description NMI interrupt requests held pending while SR.BL bit is set to 1 (Initial value) NMI interrupt requests detected while SR.BL bit is set to 1 Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information will be lost, and so must be saved beforehand. 2. This bit is cleared automatically by NMI acceptance. Bit 8--NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt request signal to the NMI pin is detected. Bit 8: NMIE 0 1 Description Interrupt request detected on falling edge of NMI input Interrupt request detected on rising edge of NMI input (Initial value) Rev. 6.0, 07/02, page 763 of 986 Bit 7--IRL Pin Mode (IRLM): Specifies whether pins ,5/6-,5/3 are to be used as levelencoded interrupt requests or as four independent interrupt requests. Bit 7: IRLM 0 1 Description ,5/ pins used as level-encoded interrupt requests (Initial value) ,5/ pins used as four independent interrupt requests (level-sense IRQ mode) Bits 13 to 10 and 6 to 0--Reserved: These bits are always read as 0, and should only be written with 0. 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only) The interrupt-priority-level setting register 00 (INTPRI00) sets the priority levels (levels 15-0) for the on-chip peripheral module interrupts. INTPRI00 is a 32-bit readable/writable register. It is initialized to H'00000000 by a reset, but is not initialized when the device enters standby mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R R/W: R/W R/W R/W R/W R/W R/W R/W R/W Table 19.7 shows the correspondence between interrupt request sources and the bits in INTPRI00. Rev. 6.0, 07/02, page 764 of 986 Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register Bit Register 31 to 28 27 to 24 Reserved 23 to 20 Reserved 19 to 16 Reserved 15 to 12 11 to 8 7 to 4 3 to 0 Reserved Reserved Interruptpriority-level setting register 00 TMU ch4 TMU ch3 Reserved Note: As shown in the table above, levels for all eight on-chip peripheral modules are assigned in a single register. The interrupt priority level for the interrupt source that corresponds to each set of four bits is set as a value from H'F (1111) to H'0 (0000). The setting H'F selects interrupt priority level 15, which is the highest, and H'0 selects level 0, which means that interrupt requests from that source are masked. Reserved bits are always read as 0. When writing, only 0s should be written to these bits. 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only) The interrupt source register 00 (INTREQ00) indicates the origin of the interrupt request that has been sent to the INTC. The states of the bits in this register is not affected by masking of the corresponding interrupts by the settings in the INTPRI00 or INTMSK00 register. INTREQ00 is a 32-bit read-only register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 0--Interrupt Request: Each of the non-reserved bits in this register indicates that there is an interrupt request relevant to that bit. For the correspondence between the bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 0 1 Description There is no interrupt request that corresponds to this bit There is an interrupt request that corresponds to this bit. Rev. 6.0, 07/02, page 765 of 986 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) The interrupt mask register 00 (INTMSK00) sets the masking of individual interrupt requests. INTMSK00 is a 32-bit register. It is initialized to H'000003FF by a reset, and retains this value in standby mode. To cancel masking of an interrupt, write a 1 to the corresponding bit in the INTMSKCLR00 register. Note that writing a 0 to a bit in INTMSK00 does not change its value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 31 to 0--Interrupt Mask: Sets the masking of the interrupt request that corresponds to the given bit. For the correspondence between bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 0 1 Description Interrupt requests from the source that corresponds to this bit are accepted Interrupt requests from the source that corresponds to this bit are masked (Initial value) Rev. 6.0, 07/02, page 766 of 986 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) The interrupt mask clear register 00 (INTMSKCLR00) clears the masking of individual interrupt requests. INTMSKCLR00 is a 32-bit write-only register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W Bit 31 to 0Interrupt Mask Clear: Each bit selects whether or not to clear the masking of the interrupt source that corresponds to that bit. For the correspondence between the bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 0 1 Description Masking of interrupt requests from the source that corresponds to the bit is not changed Masking of interrupt requests from the source that corresponds to the bit is cleared 19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only) The relationship between the bits in these registers and interrupt sources is as shown below. Table 19.8 Bit Assignments Bit number 31 to 10, 7 to 0 9 8 Module Reserved TMU TMU Interrupt Reserved TUNI4 TUNI3 Rev. 6.0, 07/02, page 767 of 986 19.4 19.4.1 INTC Operation Interrupt Operation Sequence The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, according to the priority levels set in interrupt priority registers A to C (IPRA-IPRC). Lowerpriority interrupts are held pending. If two of these interrupts have the same priority level, or if multiple interrupts occur within a single module, the interrupt with the highest priority according to table 19.5, Interrupt Exception Handling Sources and Priority Order, is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3-I0) in the status register (SR) of the CPU. If the request priority level is higher that the level in bits I3-I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU accepts an interrupt at a break between instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. The R15 contents at this time are saved in SGR. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). The interrupt handler may branch with the INTEVT register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the particular interrupt source. Notes: 1. The interrupt mask bits (I3-I0) in the status register (SR) are not changed by acceptance of an interrupt in the SH7750 Series. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 19.7 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction. 3. For some interrupt sources, their interrupt masks (INTMSK00) must e cleared using the INTMSKCLR00 register. Rev. 6.0, 07/02, page 768 of 986 Program execution state Interrupt generated? Yes (BL bit in SR = 0) or (sleep or standby mode)? Yes NMI? Yes No No NMIB in ICR = 1 and NMI? No Yes No Level 15 interrupt? Yes Yes I3-I0* = level 14 or lower? No Set interrupt source in INTEVT Save SR to SSR; save PC to SPC Set BL, MD, RB bits in SR to 1 Branch to exception handler Yes No Level 14 interrupt? Yes I3-I0 = level 13 or lower? No Yes No Level 1 interrupt? Yes I3-I0 = level 0? No No Note: * I3-I0: Interrupt mask bits in status register (SR) Figure 19.3 Interrupt Operation Flowchart Rev. 6.0, 07/02, page 769 of 986 19.4.2 Multiple Interrupts When handling multiple interrupts, interrupt handling should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The code in INTEVT can be used as a branch-offset for branching to the specific handler. 2. Clear the interrupt source in the corresponding interrupt handler. 3. Save SPC and SSR to the stack. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Set the BL bit in SR to 1. 7. Restore SSR and SPC from memory. 8. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. This enables the interrupt response time to be shortened for urgent processing. 19.4.3 Interrupt Masking with MAI Bit By setting the MAI bit to 1 in the ICR register, it is possible to mask interrupts while the NMI pin is low, irrespective of the BL and IMASK bits in the SR register. * In normal operation and sleep mode All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is generated by a transition at the NMI pin. * In standby mode All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a transition at the NMI pin. Therefore, standby cannot be cleared by an NMI interrupt while the MAI bit is set to 1. Rev. 6.0, 07/02, page 770 of 986 19.5 Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception service routine is started (the interrupt response time) is shown in table 19.9. Table 19.9 Interrupt Response Time Number of States Item Time for priority decision and SR mask bit comparison* Wait time until end of sequence being executed by CPU Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handler is started Response time Total Minimum case Maximum case NMI 1Icyc + 4Bcyc S - 1 ( 0) x Icyc 4 x Icyc RL 1Icyc + 7Bcyc S - 1 ( 0) x Icyc 4 x Icyc Peripheral Modules 1Icyc + 2Bcyc S - 1 ( 0) x Icyc 4 x Icyc Notes 5Icyc + 4Bcyc + (S - 1)Icyc 13Icyc 36 + S Icyc 5Icyc + 7Bcyc + (S - 1)Icyc 19Icyc 60 + S Icyc 5Icyc + 2Bcyc + (S - 1)Icyc 9Icyc 20 + S Icyc When Icyc: Bcyc = 2:1 When Icyc: Bcyc = 8:1 Icyc: One cycle of internal clock supplied to CPU, etc. Bcyc: One CKIO cycle S: Latency of instruction Note: * In the SH7750 and SH7750S including the case where the mask bit (IMASK) in SR is changed, and a new interrupt is generated. Rev. 6.0, 07/02, page 771 of 986 Rev. 6.0, 07/02, page 772 of 986 Section 20 User Break Controller (UBC) 20.1 Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU. This function makes it easy to design an effective selfmonitoring debugger, enabling programs to be debugged with the chip alone, without using an incircuit emulator. 20.1.1 Features The UBC has the following features. * Two break channels (A and B) User break interrupts can be generated on independent conditions for channels A and B, or on sequential conditions (sequential break setting: channel A channel B). * The following can be set as break compare conditions: Address (selection of 32-bit virtual address and ASID for comparison): Address: All bits compared/lower 10 bits masked/lower 12 bits masked/lower 16 bits masked/lower 20 bits masked/all bits masked ASID: All bits compared/all bits masked Data (channel B only, 32-bit mask capability) Bus cycle: Instruction access/operand access Read/write Operand size: Byte/word/longword/quadword * An instruction access cycle break can be effected before or after the instruction is executed. Rev. 6.0, 07/02, page 773 of 986 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the UBC. Access control Address bus Channel A Access comparator BBRA Data bus BARA Address comparator BASRA BAMRA Channel B Access comparator BBRB BARB Address comparator BASRB BAMRB Data comparator BBRA: BARA: BASRA: BAMRA: BBRB: BARB: BASRB: BAMRB: BDRB: BDMRB: BRCR: Break bus cycle register A Break address register A Break ASID register A Break address mask register A Break bus cycle register B Break address register B Break ASID register B Break address mask register B Break data register B Break data mask register B Break control register BDRB BDMRB Control BRCR User break trap request Figure 20.1 Block Diagram of User Break Controller Rev. 6.0, 07/02, page 774 of 986 Table 20.1 shows the UBC registers. Table 20.1 UBC Registers Name Break address register A Break address mask register A Break bus cycle register A Break ASID register A Break address register B Break address mask register B Break bus cycle register B Break ASID register B Break data register B Break data mask register B Break control register Abbreviation BARA BAMRA R/W R/W R/W Initial Value Undefined Undefined P4 Address H'FF200000 H'FF200004 Area 7 Address H'1F200000 H'1F200004 Access Size 32 8 BBRA BASRA BARB BAMRB R/W R/W R/W R/W H'0000 Undefined Undefined Undefined H'FF200008 H'FF000014 H'FF20000C H'FF200010 H'1F200008 H'1F000014 H'1F20000C H'1F200010 16 8 32 8 BBRB BASRB BDRB BDMRB BRCR R/W R/W R/W R/W R/W H'0000 Undefined Undefined Undefined H'0000* H'FF200014 H'FF000018 H'FF200018 H'FF20001C H'FF200020 H'1F200014 H'1F000018 H'1F200018 H'1F20001C H'1F200020 16 8 32 32 16 Note: * Some bits are not initialized. See section 20.2.12, Break Control Register (BRCR), for details. Rev. 6.0, 07/02, page 775 of 986 20.2 20.2.1 Register Descriptions Access to UBC Control Registers The access size must be the same as the control register size. If the sizes are different, a write will not be effected in a UBC register write operation, and a read operation will return an undefined value. UBC control register contents cannot be transferred to a floating-point register using a floating-point memory load instruction. When a UBC control register is updated, use either of the following methods to make the updated value valid: 1. Execute an RTE instruction after the memory store instruction that updated the register. The updated value will be valid from the RTE instruction jump destination onward. 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the SH7750 Series executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward. Rev. 6.0, 07/02, page 776 of 986 20.2.2 Break Address Register A (BARA) Bit: 31 BAA31 Initial value: R/W: Bit: * R/W 23 BAA23 Initial value: R/W: Bit: * R/W 15 BAA15 Initial value: R/W: Bit: * R/W 7 BAA7 Initial value: R/W: * R/W 30 BAA30 * R/W 22 BAA22 * R/W 14 BAA14 * R/W 6 BAA6 * R/W 29 BAA29 * R/W 21 BAA21 * R/W 13 BAA13 * R/W 5 BAA5 * R/W 28 BAA28 * R/W 20 BAA20 * R/W 12 BAA12 * R/W 4 BAA4 * R/W 27 BAA27 * R/W 19 BAA19 * R/W 11 BAA11 * R/W 3 BAA3 * R/W 26 BAA26 * R/W 18 BAA18 * R/W 10 BAA10 * R/W 2 BAA2 * R/W 25 BAA25 * R/W 17 BAA17 * R/W 9 BAA9 * R/W 1 BAA1 * R/W 24 BAA24 * R/W 16 BAA16 * R/W 8 BAA8 * R/W 0 BAA0 * R/W Note: *: Undefined Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual address used in the channel A break conditions. BARA is not initialized by a power-on reset or manual reset. Bits 31 to 0--Break Address A31 to A0 (BAA31-BAA0): These bits hold the virtual address (bits 31-0) used in the channel A break conditions. Rev. 6.0, 07/02, page 777 of 986 20.2.3 Break ASID Register A (BASRA) Bit: 7 BASA7 Initial value: R/W: * R/W 6 BASA6 * R/W 5 BASA5 * R/W 4 BASA4 * R/W 3 BASA3 * R/W 2 BASA2 * R/W 1 BASA1 * R/W 0 BASA0 * R/W Note: *: Undefined Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID used in the channel A break conditions. BASRA is not initialized by a power-on reset or manual reset. Bits 7 to 0--Break ASID A7 to A0 (BASA7-BASA0): These bits hold the ASID (bits 7-0) used in the channel A break conditions. 20.2.4 Break Address Mask Register A (BAMRA) Bit: 7 -- Initial value: R/W: Note: *: Undefined 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 2 1 0 BAMA0 * R/W BAMA2 BASMA BAMA1 * R/W * R/W * R/W Break address mask register A (BAMRA) is an 8-bit readable/writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA. BAMRA is not initialized by a power-on reset or manual reset. Bits 7 to 4--Reserved: These bits are always read as 0, and should only be written with 0. Bit 2--Break ASID Mask A (BASMA): Specifies whether all bits of the channel A break ASID7 to ASID0 (BASA7-BASA0) are to be masked. Bit 2: BASMA 0 1 Description All BASRA bits are included in break conditions No BASRA bits are included in break conditions Rev. 6.0, 07/02, page 778 of 986 Bits 3, 1, and 0--Break Address Mask A2 to A0 (BAMA2-BAMA0): These bits specify which bits of the channel A break address 31 to 0 (BAA31-BAA0) set in BARA are to be masked. Bit 3: BAMA2 0 Bit 1: BAMA1 0 Bit 0: BAMA0 0 1 1 0 1 1 0 0 1 1 Note: *: Don't care * Description All BARA bits are included in break conditions Lower 10 bits of BARA are masked, and not included in break conditions Lower 12 bits of BARA are masked, and not included in break conditions All BARA bits are masked, and not included in break conditions Lower 16 bits of BARA are masked, and not included in break conditions Lower 20 bits of BARA are masked, and not included in break conditions Reserved (cannot be set) 20.2.5 Break Bus Cycle Register A (BBRA) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 SZA2 0 R/W 13 -- 0 R 5 IDA1 0 R/W 12 -- 0 R 4 IDA0 0 R/W 11 -- 0 R 3 RWA1 0 R/W 10 -- 0 R 2 RWA0 0 R/W 9 -- 0 R 1 SZA1 0 R/W 8 -- 0 R 0 SZA0 0 R/W Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets three conditions--(1) instruction access/operand access, (2) read/write, and (3) operand size--from among the channel A break conditions. BBRA is initialized to H'0000 by a power-on reset. It retains its value in standby mode. Bits 15 to 7--Reserved: These bits are always read as 0, and should only be written with 0. Rev. 6.0, 07/02, page 779 of 986 Bits 5 and 4--Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions. Bit 5: IDA1 0 Bit 4: IDA0 0 1 1 0 1 Description Condition comparison is not performed (Initial value) Instruction access cycle is used as break condition Operand access cycle is used as break condition Instruction access cycle or operand access cycle is used as break condition Bits 3 and 2--Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel A break conditions. Bit 3: RWA1 0 Bit 2: RWA0 0 1 1 0 1 Description Condition comparison is not performed Read cycle is used as break condition Write cycle is used as break condition Read cycle or write cycle is used as break condition (Initial value) Bits 6, 1, and 0--Operand Size Select A (SZA2-SZA0): These bits select the operand size of the bus cycle used as a channel A break condition. Bit 6: SZA2 0 Bit 1: SZA1 0 Bit 0: SZA0 0 1 1 0 1 1 0 0 1 1 Note: *: Don't care * Description Operand size is not included in break conditions (Initial value) Byte access is used as break condition Word access is used as break condition Longword access is used as break condition Quadword access is used as break condition Reserved (cannot be set) Reserved (cannot be set) Rev. 6.0, 07/02, page 780 of 986 20.2.6 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 20.2.7 Break ASID Register B (BASRB) BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA. 20.2.8 Break Address Mask Register B (BAMRB) BAMRB is the channel B break address mask register. The bit configuration is the same as for BAMRA. 20.2.9 Break Data Register B (BDRB) Bit: 31 BDB31 Initial value: R/W: Bit: * R/W 23 BDB23 Initial value: R/W: Bit: * R/W 15 BDB15 Initial value: R/W: Bit: * R/W 7 BDB7 Initial value: R/W: Note: *: Undefined * R/W 30 BDB30 * R/W 22 BDB22 * R/W 14 BDB14 * R/W 6 BDB6 * R/W 29 BDB29 * R/W 21 BDB21 * R/W 13 BDB13 * R/W 5 BDB5 * R/W 28 BDB28 * R/W 20 BDB20 * R/W 12 BDB12 * R/W 4 BDB4 * R/W 27 BDB27 * R/W 19 BDB19 * R/W 11 BDB11 * R/W 3 BDB3 * R/W 26 BDB26 * R/W 18 BDB18 * R/W 10 BDB10 * R/W 2 BDB2 * R/W 25 BDB25 * R/W 17 BDB17 * R/W 9 BDB9 * R/W 1 BDB1 * R/W 24 BDB24 * R/W 16 BDB16 * R/W 8 BDB8 * R/W 0 BDB0 * R/W Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31- 0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or manual reset. Rev. 6.0, 07/02, page 781 of 986 Bits 31 to 0--Break Data B31 to B0 (BDB31-BDB0): These bits hold the data (bits 31-0) to be used in the channel B break conditions. 20.2.10 Break Data Mask Register B (BDMRB) Bit: 31 30 29 28 27 26 25 24 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit: * R/W 23 * R/W 22 * R/W 21 * R/W 20 * R/W 19 * R/W 18 * R/W 17 * R/W 16 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value: R/W: Bit: * R/W 15 * R/W 14 * R/W 13 * R/W 12 * R/W 11 * R/W 10 * R/W 9 * R/W 8 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 Initial value: R/W: Bit: * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Initial value: R/W: Note: *: Undefined * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on reset or manual reset. Rev. 6.0, 07/02, page 782 of 986 Bits 31 to 0--Break Data Mask B31 to B0 (BDMB31-BDMB0): These bits specify whether the corresponding bit of the channel B break data B31 to B0 (BDB31-BDB0) set in BDRB is to be masked. Bit 31-0: BDMBn 0 1 Description Channel B break data bit BDBn is included in break conditions Channel B break data bit BDBn is masked, and not included in break conditions n = 31 to 0 Note: When the data bus value is included in the break conditions, the operand size should be specified. When byte size is specified, set the same data in bits 15-8 and 7-0 of BDRB and BDMRB. 20.2.11 Break Bus Cycle Register B (BBRB) BBRB is the channel B bus break register. The bit configuration is the same as for BBRA. 20.2.12 Break Control Register (BRCR) Bit: 15 CMFA Initial value: R/W: Bit: 0 R/W 7 DBEB Initial value: R/W: Note: *: Undefined * R/W 14 CMFB 0 R/W 6 PCBB * R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 SEQ * R/W 10 PCBA * R/W 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 UBDE 0 R/W The break control register (BRCR) is a 16-bit readable/writable register that specifies (1) whether channels A and B are to be used as two independent channels or in a sequential condition, (2) whether the break is to be effected before or after instruction execution, (3) whether the BDRB register is to be included in the channel B break conditions, and (4) whether the user break debug function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual reset, so these bits should be initialized by software as necessary. Rev. 6.0, 07/02, page 783 of 986 Bit 15--Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) Bit 15: CMFA 0 1 Description Channel A break condition is not matched Channel A break condition match has occurred (Initial value) Bit 14--Condition Match Flag B (CMFB): Set to 1 when a break condition set for channel B is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) Bit 14: CMFB 0 1 Description Channel B break condition is not matched Channel B break condition match has occurred (Initial value) Bits 13 to 11--Reserved: These bits are always read as 0, and should only be written with 0. Bit 10--Instruction Access Break Select A (PCBA): Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 10: PCBA 0 1 Description Channel A PC break is effected before instruction execution Channel A PC break is effected after instruction execution Bits 9 and 8--Reserved: These bits are always read as 0, and should only be written with 0. Bit 7--Data Break Enable B (DBEB): Specifies whether the data bus condition is to be included in the channel B break conditions. This bit is not initialized by a power-on reset or manual reset. Bit 7: DBEB 0 1 Description Data bus condition is not included in channel B conditions Data bus condition is included in channel B conditions Note: When the data bus is included in the break conditions, bits IDB1-0 in break bus cycle register B (BBRB) should be set to 10 or 11. Rev. 6.0, 07/02, page 784 of 986 Bit 6--PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 6: PCBB 0 1 Description Channel B PC break is effected before instruction execution Channel B PC break is effected after instruction execution Bits 5 and 4--Reserved: These bits are always read as 0, and should only be written with 0. Bit 3--Sequence Condition Select (SEQ): Specifies whether the conditions for channels A and B are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset. Bit 3: SEQ 0 1 Description Channel A and B comparisons are performed as independent conditions Channel A and B comparisons are performed as sequential conditions (channel A channel B) Bits 2 and 1--Reserved: These bits are always read as 0, and should only be written with 0. Bit 0--User Break Debug Enable (UBDE): Specifies whether the user break debug function (see section 20.4, User Break Debug Support Function) is to be used. Bit 0: UBDE 0 1 Description User break debug function is not used User break debug function is used (Initial value) 20.3 20.3.1 Operation Explanation of Terms Relating to Accesses An instruction access is an access that obtains an instruction. An operand access is any memory access for the purpose of instruction execution. For example, the access to address PC+dispx2+4 in the instruction MOV.W @(disp,PC), Rn (an access very close to the program counter) is an operand access. The fetching of an instruction from the branch destination when a branch instruction is executed is also an instruction access. As the term "data" is used to distinguish data from an address, the term "operand access" is used in this section. Rev. 6.0, 07/02, page 785 of 986 In the SH7750 Series, all operand accesses are treated as either read accesses or write accesses. The following instructions require special attention: * PREF, OCBP, and OCBWB instructions: Treated as read accesses. * MOVCA.L and OCBI instructions: Treated as write accesses. * TAS.B instruction: Treated as one read access and one write access. The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no access data. The SH7750 Series handles all operand accesses as having a data size. The data size can be byte, word, longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA.L, and OCBI instructions is treated as longword. 20.3.2 Explanation of Terms Relating to Instruction Intervals In this section, "1 (2, 3, ...) instruction(s) after...", as a measure of the distance between two instructions, is defined as follows. A branch is counted as an interval of two instructions. * Example of sequence of instructions with no branch: 100 Instruction A (0 instructions after instruction A) 102 104 106 Instruction B (1 instruction after instruction A) Instruction C (2 instructions after instruction A) Instruction D (3 instructions after instruction A) * Example of sequence of instructions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 Instruction A: BT/S L200 (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B) L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B) 202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B) Rev. 6.0, 07/02, page 786 of 986 20.3.3 User Break Operation Sequence The sequence of operations from setting of break conditions to user break exception handling is described below. 1. Specify pre- or post-execution breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel A and B break conditions, in the break control register (BRCR). Set the break addresses in the break address registers for each channel (BARA, BARB), the ASIDs corresponding to the break space in the break ASID registers (BASRA, BASRB), and the address and ASID masking methods in the break address mask registers (BAMRA, BAMRB). If the data bus value is to be included in the break conditions, also set the break data in the break data register (BDRB) and the data mask in the break data mask register (BDMRB). 2. Set the break bus conditions in the break bus cycle registers (BBRA, BBRB). If even one of the BBRA/BBRB instruction access/operand access select (ID bit) and read/write select groups (RW bit) is set to 00, a user break interrupt will not be generated on the corresponding channel. Make the BBRA and BBRB settings after all other break-related register settings have been completed. If breaks are enabled with BBRA/BBRB while the break address, data, or mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently. 3. The operation when a break condition is satisfied depends on the BL bit (in the CPU's SR register). When the BL bit is 0, exception handling is started and the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is 1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition but exception handling is not started. The condition match flags (CMFA, CMFB) are set by a branch condition match, but are not automatically cleared. Therefore, a memory store instruction should be used on the BRCR register to clear the flags to 0. See section 20.3.6, Condition Match Flag Setting, for the exact setting conditions for the condition match flags. 4. When sequential condition mode has been selected, and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched. See section 20.3.8, Contiguous A and B Settings for Sequential Conditions, for the operation when the channel A condition match and channel B condition match occur close together. With sequential conditions, only the channel B condition match flag is set. When sequential condition mode has been selected, if it is wished to clear the channel A match when the channel A condition has been matched but the channel B condition has not yet been matched, this can be done by writing 0 to the SEQ bit in the BRCR register. Rev. 6.0, 07/02, page 787 of 986 20.3.4 Instruction Access Cycle Break 1. When an instruction access/read/word setting is made in the break bus cycle register (BBRA/BBRB), an instruction access cycle can be used as a break condition. In this case, breaking before or after execution of the relevant instruction can be selected with the PCBA/PCBB bit in the break control register (BRCR). When an instruction access cycle is used as a break condition, clear the LSB of the break address registers (BARA, BARB) to 0. A break will not be generated if this bit is set to 1. 2. When a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. Therefore, an overrun-fetched instruction (an instruction that is fetched but not executed when a branch or exception occurs) cannot be used in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of the fetch of an instruction subject to a break, the break exception handling is carried out first. The instruction TLB exception handling is performed when the instruction is re-executed (see section 5.4, Exception Types and Priorities). Also, since a delayed branch instruction and the delay slot instruction are executed as a single instruction, if a pre-execution break is specified for a delay slot instruction, the break will be effected before execution of the delayed branch instruction. However, a pre-execution break cannot be specified for the delay slot instruction for an RTE instruction. 3. With a pre-execution break, the instruction set as a break condition is executed, then a break interrupt is generated before the next instruction is executed. When a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). 4. When an instruction access cycle is set for channel B, break data register B (BDRB) is ignored in judging whether there is an instruction access match. Therefore, a break condition specified by the DBEB bit in BRCR is not executed. Rev. 6.0, 07/02, page 788 of 986 20.3.5 Operand Access Cycle Break 1. In the case of an operand access cycle break, the bits included in address bus comparison vary as shown below according to the data size specification in the break bus cycle register (BBRA/BBRB). Data Size Quadword (100) Longword (011) Word (010) Byte (001) Not included in condition (000) Address Bits Compared Address bits A31-A3 Address bits A31-A2 Address bits A31-A1 Address bits A31-A0 In quadword access, address bits A31-A3 In longword access, address bits A31-A2 In word access, address bits A31-A1 In byte access, address bits A31-A0 2. When data value is included in break conditions in channel B When a data value is included in the break conditions, set the DBEB bit in the break control register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register B (BDMRB) settings are necessary in addition to the address condition. A user break interrupt is generated when all three conditions--address, ASID, and data--are matched. When a quadword access occurs, the 64-bit access data is divided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. A break is generated if either of the 32-bit data units satisfies the data match condition. Set the IDB1-0 bits in break bus cycle register B (BBRB) to 10 or 11. When byte data is specified, the same data should be set in the two bytes comprising bits 15-8 and bits 7-0 in break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31-16 of BDRB and BDMRB are ignored. 3. When the DBEB bit in the break control register (BRCR) is set to 1, a break is not generated by an operand access with no access data (an operand access in a PREF, OCBP, OCBWB, or OCBI instruction). Rev. 6.0, 07/02, page 789 of 986 20.3.6 Condition Match Flag Setting 1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed. Example 1: 100 BT L200 (branch performed) 102 Instruction (operand access break on channel A) flag not set Example 2: 110 FADD (FPU exception) 112 Instruction (operand access break on channel A) flag not set 2. Instruction access with pre-execution condition The flag is set when the break match condition is detected. Example 1: 110 Instruction (pre-execution break on channel A) flag set 112 Instruction (pre-execution break on channel B) flag not set Example 2: 110 Instruction (pre-execution break on channel B, instruction access TLB miss) flag set 20.3.7 Program Counter (PC) Value Saved 1. When instruction access (pre-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred. In this case, a user break interrupt is generated and the fetched instruction is not executed. 2. When instruction access (post-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. In this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction. 3. When an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). In this case, the PC value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made). Rev. 6.0, 07/02, page 790 of 986 4. When operand access (address only) is set as a break condition, the address of the instruction to be executed after the instruction at which the condition match occurred is saved to SPC. The instruction at which the condition match occurred is executed, and a user break interrupt occurs before the following instruction is executed. 5. When operand access (address + data) is set as a break condition, execution of the instruction at which the condition match occurred is completed. A user break interrupt is generated before execution of instructions from one instruction later to four instructions later. It is not possible to specify at which instruction, from one later to four later, the interrupt will be generated. The start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to SPC. If an instruction between one instruction later and four instructions later causes another exception, control is performed as follows. Designating the exception caused by the break as exception 1, and the exception caused by an instruction between one instruction later and four instructions later as exception 2, the fact that memory updating and register updating that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1. The program counter value saved is the address of the first instruction for which execution is suppressed. Whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT) is not guaranteed. However, if exception 2 is from a source not synchronized with an instruction (external interrupt or peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT). 20.3.8 Contiguous A and B Settings for Sequential Conditions When channel A match and channel B match timings are close together, a sequential break may not be guaranteed. Rules relating to the guaranteed range are given below. 1. Instruction access matches on both channel A and channel B Instruction B is 0 instructions after instruction A Instruction B is 1 instruction after instruction A Instruction B is 2 or more instructions after instruction A Equivalent to setting the same address. Do not use this setting. Sequential operation is not guaranteed. Sequential operation is guaranteed. 2. Instruction access match on channel A, operand access match on channel B Instruction B is 0 or 1 instruction after instruction A Instruction B is 2 or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed. Rev. 6.0, 07/02, page 791 of 986 3. Operand access match on channel A, instruction access match on channel B Instruction B is 0 to 3 instructions after instruction A Instruction B is 4 or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed. 4. Operand access matches on both channel A and channel B Do not make a setting such that a single operand access will match the break conditions of both channel A and channel B. There are no other restrictions. For example, sequential operation is guaranteed even if two accesses within a single instruction match channel A and channel B conditions in turn. 20.3.9 Usage Notes 1. Do not execute a post-execution instruction access break for the SLEEP instruction. 2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction. 3. The value of the BL bit referenced in a user break exception depends on the break setting, as follows. a. Pre-execution instruction access break: The BL bit value before the executed instruction is referenced. b. Post-execution instruction access break: The OR of the BL bit values before and after the executed instruction is referenced. c. Operand access break (address/data): The BL bit value after the executed instruction is referenced. d. In the case of an instruction that modifies the BL bit PreExecution Instruction Access A M A M PostExecution Instruction Access A M M M PreExecution Instruction Access A M A M PostExecution Instruction Access A M M M SL.BL 00 10 01 11 A: Accepted M: Masked Operand Access (Address/Data) A A M M Rev. 6.0, 07/02, page 792 of 986 e. In the case of an RTE delay slot The BL bit value before execution of a delay slot instruction is the same as the BL bit value before execution of an RTE instruction. The BL bit value after execution of a delay slot instruction is the same as the first BL bit value for the first instruction executed on returning by means of an RTE instruction (the same as the value of the BL bit in SSR before execution of the RTE instruction). f. If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit before execution of the first instruction of the exception handling routine is 1. 4. If channels A and B both match independently at virtually the same time, and, as a result, the SPC value is the same for both user break interrupts, only one user break interrupt is generated, but both the CMFA bit and the CMFB bit are set. For example: 110 Instruction (post-execution instruction break on channel A) SPC = 112, CMFA = 1 112 Instruction (pre-execution instruction break on channel B) SPC = 112, CMFB = 1 5. The PCBA or PCBB bit in BRCR is invalid for an instruction access break setting. 6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel B condition match. For example: A A B (user break generated) B (no break generated) 7. In the event of contention between a re-execution type exception and a post-execution break in a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit may or may not be set to 1 when the break condition occurs. 8. A post-execution break is classified as a completion type exception. Consequently, in the event of contention between a completion type exception and a post-execution break, the postexecution break is suppressed in accordance with the priorities of the two events. For example, in the case of contention between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition. 20.4 User Break Debug Support Function The user break debug support function enables the processing used in the event of a user break exception to be changed. When a user break exception occurs, if the UBDE bit is set to 1 in the BRCR register, the DBR register value will be used as the branch destination address instead of [VBR + offset]. The value of R15 is saved in the SGR register regardless of the value of the UBDE bit in the BRCR register or the kind of exception event. A flowchart of the user break debug support function is shown in figure 20.2. Rev. 6.0, 07/02, page 793 of 986 Exception/interrupt generation Hardware operation SPC PC SSR SR SR.BL B'1 SR.MD B'1 SR.RB B'1 Exception Exception/ interrupt/trap? Interrupt Trap EXPEVT exception code INTEVT interrupt code EXPEVT H'160 TRA TRAPA (imm) SGR R15 No Reset exception? Yes Yes (BRCR.UBDE == 1) && (user break exception)? No PC DBR PC VBR + vector offset PC H'A0000000 Debug program R15 SGR (STC instruction) Exception service routine Execute RTE instruction PC SPC SR SSR End of exception operations Figure 20.2 User Break Debug Support Function Flowchart Rev. 6.0, 07/02, page 794 of 986 20.5 Examples of Use Instruction Access Cycle Break Condition Settings * Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400 Conditions set: Independent channel A/channel B mode Channel A: ASID: H'80 / address: H'00000404 / address mask: H'00 Bus cycle: instruction access (post-instruction-execution), read (operand size not included in conditions) Channel B: ASID: H'70 / address: H'00008010 / address mask: H'01 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break is generated after execution of the instruction at address H'00000404 with ASID = H'80, or before execution of an instruction at addresses H'00008000-H'000083FE with ASID = H'70. * Register settings: BASRA = H'80 / BARA = H'00037226 / BAMRA = H'00 / BBRA = H'0016 / BASRB = H'70 / BARB = H'0003722E / BAMRB = H'00 / BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008 Conditions set: Channel A channel B sequential mode Channel A: ASID: H'80 / address: H'00037226 / address mask: H'00 Bus cycle: instruction access (pre-instruction-execution), read, word Channel B: ASID: H'70 / address: H'0003722E / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read, word The instruction at address H'00037266 with ASID = H'80 is executed, then a user break is generated before execution of the instruction at address H'0003722E with ASID = H'70. * Register settings: BASRA = H'80 / BARA = H'00027128 / BAMRA = H'00 / BBRA = H'001A / BASRB = H'70 / BARB = H'00031415 / BAMRB = H'00 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0000 Conditions set: Independent channel A/channel B mode Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00 Bus cycle: CPU, instruction access (pre-instruction-execution), write, word Rev. 6.0, 07/02, page 795 of 986 Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break interrupt is not generated on channel A since the instruction access is not a write cycle. A user break interrupt is not generated on channel B since instruction access is performed on an even address. Operand Access Cycle Break Condition Settings * Register settings: BASRA = H'80 / BARA = H'00123456 / BAMRA = H'00 / BBRA = H'0024 / BASRB = H'70/ BARB = H'000ABCDE / BAMRB = H'02 / BBRB = H'002A / BDRB = H'0000A512 / BDMRB = H'00000000 / BRCR = H'0080 Conditions set: Independent channel A/channel B mode Channel A: ASID: H'80 / address: H'00123456 / address mask: H'00 Bus cycle: operand access, read (operand size not included in conditions) Channel B: ASID: H'70 / address: H'000ABCDE / address mask: H'02 Data: H'0000A512 / data mask: H'00000000 Bus cycle: operand access, write, word Data break enabled On channel A, a user break interrupt is generated in the event of a longword read at address H'00123454, a word read at address H'00123456, or a byte read at address H'00123456, with ASID = H'80. On channel B, a user break interrupt is generated when H'A512 is written by word access to any address from H'000AB000 to H'000ABFFE with ASID = H'70. Rev. 6.0, 07/02, page 796 of 986 20.6 User Break Controller Stop Function In the SH7750S, this function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. Note that, if you use this function, you cannot use the user break controller. This function is not provided in the SH7750. 20.6.1 Transition to User Break Controller Stopped State Setting the MSTP5 bit of the STBCR2 (inside the CPG) to 1 stops the clock supply and causes the user break controller to enter the stopped state. Follow steps (1) to (5) below to set the MSTP5 bit to 1 and enter the stopped state. (1) Initialize BBRA and BBRB to 0; (2) Initialize BRCR to 0; (3) Make a dummy read of BRCR; (4) Read STBCR2, then set the MSTP5 bit in the read data to 1 and write back. (5) Make two dummy reads of STBCR2. Make sure that, if an exception or interrupt occurs while performing steps (1) to (5), you do not change the values of these registers in the exception handling routine. Do not read or write the following registers while the user break controller clock is stopped: BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB, BDMRB, and BRCR. If these registers are read or written, the value cannot be guaranteed. 20.6.2 Cancelling the User Break Controller Stopped State The clock supply can be restarted by setting the MSTP5 bit of STBCR2 (inside the CPG) to 0. The user break controller can then be operated again. Follow steps (6) and (7) below to clear the MSTP5 bit to 0 to cancel the stopped state. (6) Read STBCR2, then clear the MSTP5 bit in the read data to 0 and write the modified data back; (7) Make two dummy reads of STBGR2. As with the transition to the stopped state, if an exception or interrupt occurs while processing steps (6) and (7), make sure that the values in these registers are not changed in the exception handling routine. Rev. 6.0, 07/02, page 797 of 986 20.6.3 Examples of Stopping and Restarting the User Break Controller The following are example programs: ; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0. mov mov.l mov.w mov.l mov.w #0, R0 #BBRA, R1 R0, @R1 #BBRB, R1 R0, @R1 ; (2) Initialize BRCR to 0. mov.l mov.w #BRCR, R1 R0, @R1 ; (3) Dummy read BRCR. mov.w @R1, R0 ; (4) Read STBCR2, then set MSTP5 bit in the read data to 1 and write it back mov.l mov.b #STBCR2, R1 @R1, R0 or #H'1, R0 mov.b R0, @R1 ; (5) Twice dummy read STBCR2. mov.b mov.b @R1, R0 @R1, R0 ; Canceling user break controller stopped state ; (6) Read STBCR2, then clear MSTP5 bit in the read data to 0 and write it back mov.l mov.b and mov.b #STBCR2, R1 @R1, R0 #H'FE, R0 R0, @R1 ; (7) Twice dummy read STBCR2. mov.b mov.b @R1, R0 @R1, R0 Rev. 6.0, 07/02, page 798 of 986 Section 21 Hitachi User Debug Interface (H-UDI) 21.1 21.1.1 Overview Features The Hitachi user debug interface (H-UDI) is a serial input/output interface conforming to JTAG, IEEE 1149.1, and IEEE Standard Test Access Port and Boundary-Scan Architecture. The SH7750R's H-UDI supports boundary-scan, but is used for emulator connection as well. The functions of this interface should not be used when using an emulator. Refer to the emulator manual for the method of connecting the emulator. The H-UDI uses six pins (TCK, TMS, TDI, TDO, 7567, and $6(%5./BRKACK). The pin functions and serial transfer protocol conform to the JTAG specifications. 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the H-UDI. The TAP (test access port) controller and control registers are reset independently of the chip reset pin by driving the 7567 pin low or setting TMS to 1 and applying TCK for at least five clock cycles. The other circuits are reset and initialized in an ordinary reset. The H-UDI circuit has four internal registers: SDBPR, SDIR, SDDRH, and SDDRL (these last two together designated SDDR). The SDBPR register supports the JTAG bypass mode, SDIR is the command register, and SDDR is the data register. SDIR can be accessed directly from the TDI and TDO pins. Rev. 6.0, 07/02, page 799 of 986 /BRKACK TCK TMS Break control Interrupt/reset etc. TAP controller Decoder SDIR Shift register * SDBPR SDBSR * SDINT SDDRH SDDRL TDO MUX Note: * Provided only in the SH7750R. Figure 21.1 Block Diagram of H-UDI Circuit Rev. 6.0, 07/02, page 800 of 986 Peripheral module bus TDI 21.1.3 Pin Configuration Table 21.1 shows the H-UDI pin configuration. Table 21.1 H-UDI Pins Pin Name Clock pin Abbreviation TCK I/O Input Function When Not Used 1 Same as the JTAG serial clock input Open* pin. Data is transferred from data input pin TDI to the H-UDI circuit, and data is read from data output pin TDO, in synchronization with this signal. The mode select input pin. Changing Open* this signal in synchronization with TCK determines the meaning of the data input from TDI. The protocol conforms to the JTAG (IEEE Std 1149.1) specification. 2 3 The input pin that resets the H-UDI. * * This signal is received asynchronously with respect to TCK, and effects a reset of the JTAG interface circuit when low. 7567 must be driven low for a certain period when powering on, regardless of whether or not JTAG is used. This differs from the IEEE specification. Mode pin TMS Input 1 Reset pin 7567 Input Data input pin Data output pin Emulator pin TDI Input The data input pin. Data is sent to the Open* H-UDI circuit by changing this signal in synchronization with TCK. The data output pin. Data is sent to the H-UDI circuit by reading this signal in synchronization with TCK. Dedicated emulator pin Open 1 TDO Output $6(%5./ BRKACK Input/ output 1 Open* Notes: *1 Pulled up inside the chip. When designing a board that allows use of an emulator, or when using interrupts and resets via the H-UDI, there is no problem in connecting a pullup resistance externally. *2 When designing a board that enables the use of an emulator, or when using interrupts and resets via the H-UDI, drive 7567 low for a period overlapping 5(6(7 at power-on, and also provide for control by 7567 alone. *3 Fixed to the ground or connected to the same signal line as 5(6(7/#or to a signal line that behaves in the same way. However, there is a problem when this pin is fixed to the ground. 7567 is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. The size of this current is determined by Rev. 6.0, 07/02, page 801 of 986 the rating of the pull-up resistor on port-pin f. Although this current has no effect on the chip's operation, unnecessary current will be dissipated. The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or SH7750 Series CPG setting so that the TCK frequency is lower than that of the SH7750 Series' on-chip peripheral module clock. 21.1.4 Register Configuration Table 21.2 shows the H-UDI registers. Except for SDBPR, these registers are mapped in the control register space and can be referenced by the CPU. Table 21.2 H-UDI Registers CPU Side Name Instruction register Data register H Data register L Bypass register Interrupt source 4 register* Abbreviation SDIR P4 R/W Address R Area 7 Address Access Initial 1 Size Value* 16 H'FFFF R/W R/W H-UDI Side Access Initial 1 Size Value* 32 H'FFFFFFFD (Fixed 2 value* ) -- -- -- H'00000000 H'FFF00000 H'1FF00000 SDDR/ R/W H'FFF00008 H'1FF00008 SDDRH 32/16 Undefined Undefined Undefined H'0000 -- -- R/W W* 3 -- -- 1 32 SDDRL R/W H'FFF0000A H'1FF0000A 16 SDBPR -- SDINT -- -- -- 16 R/W H'FFF00014 H'1FF00014 Boundary SDBSR -- 4 scan register* -- -- -- Undefined R/W -- Undefined Notes: *1 Initialized when the 7567 pin goes low or when the TAP is in the Test-Logic-Reset state. *2 The value read from H-UDI is fixed (H'FFFFFFFD). *3 Using the H-UDI interrupt command, a 1 can be written to the least significant bit. *4 SH7750R only Rev. 6.0, 07/02, page 802 of 986 21.2 21.2.1 Register Descriptions Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is initialized by the 7567 pin or in the TAP Test-Logic-Reset state. When this register is written to from the H-UDI, writing is possible regardless of the CPU mode. However, if a read is performed by the CPU while writing is in progress, it may not be possible to read the correct value. In this case, SDIR should be read twice, and then read again if the read values do not match. Operation is undefined if a reserved command is set in this register. SH7750, SH7750S: Bit: 15 TI3 Initial value: R/W: Bit: 1 R 7 -- Initial value: R/W: 1 R 14 TI2 1 R 6 -- 1 R 13 TI1 1 R 5 -- 1 R 12 TI0 1 R 4 -- 1 R 11 -- 1 R 3 -- 1 R 10 -- 1 R 2 -- 1 R 9 -- 1 R 1 -- 1 R 8 -- 1 R 0 -- 1 R Bits 15 to 12--Test Instruction Bits (TI3-TI0) Bit 15: TI3 0 Bit 14: TI2 0 1 Bit 13: TI1 -- 0 1 Bit 12: TI0 -- -- 0 1 1 0 0 1 1 0 1 -- -- -- 0 1 Description Reserved Reserved H-UDI reset negate H-UDI reset assert Reserved H-UDI interrupt Reserved Reserved Bypass mode (Initial value) Bits 11 to 0--Reserved: These bits are always read as 1, and should only be written with 1. Rev. 6.0, 07/02, page 803 of 986 SH7750R: Bit: 15 TI7 Initial value: R/W: Bit: 1 R 7 -- Initial value: R/W: 1 R 14 TI6 1 R 6 -- 1 R 13 TI5 1 R 5 -- 1 R 12 TI4 1 R 4 -- 1 R 11 TI3 1 R 3 -- 1 R 10 TI2 1 R 2 -- 1 R 9 TI1 1 R 1 -- 1 R 8 TI0 1 R 0 -- 1 R Bits 15 to 8--Test Instruction Bits (TI7-TI0) Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: TI7 TI6 TI5 TI4 TI3 TI2 TI1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 0 0 1 -- 1 0 0 -- -- -- 1 0 1 -- -- -- 1 0 0 -- -- -- 1 Bit 8: TI0 0 0 -- -- -- 1 Description EXTEST SAMPLE/PRELOAD H-UDI reset negate H-UDI reset assert H-UDI interrupt Bypass mode (Initial value) Reserved Other than above Bits 7 to 0--Reserved: These bits are always read as 1, and should only be written with 1. Rev. 6.0, 07/02, page 804 of 986 21.2.2 Data Register (SDDR) The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and SDDRL, that can be read and written to by the CPU. The value in this register is not initialized by a 7567 or CPU reset. Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: * R/W 23 * R/W 22 * R/W 21 * R/W 20 * R/W 19 * R/W 18 * R/W 17 * R/W 16 Initial value: R/W: Bit: * R/W 15 * R/W 14 * R/W 13 * R/W 12 * R/W 11 * R/W 10 * R/W 9 * R/W 8 Initial value: R/W: Bit: * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 Initial value: R/W: Note: *: Undefined * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Bits 31 to 0--DR Data: These bits store the SDDR value. 21.2.3 Bypass Register (SDBPR) The bypass register (SDBPR) is a one-bit register that cannot be accessed by the CPU. When bypass mode is set in SDIR, SDBPR is connected between the TDI pin and TDO pin of the H-UDI. Rev. 6.0, 07/02, page 805 of 986 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only) The interrupt source register (SDINT) is a 16-bit register that can be read from and written to by the CPU. From the H-UDI pins, the INTREQ bit is set to 1 when a H-UDI interrupt command is set in the SDIR register (Update-IR). While SDIR is holding a H-UDI interrupt command, the SDINT register is connected between the TDI and TDO pins of the H-UDI, allowing it to be read as a 32bit register. In this case, the upper 16 bits will all be 0, and the lower 16 bits will represent SDINT. From the CPU, only writing a 0 to the INTREQ bit is possible. While this bit holds a 1, the interrupt requests continue to be issued, so this bit should always be cleared in the interrupt handler. This register is initialized in the Test-Logic-Reset state of 7567 or TAP. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 INTREQ 0 R/W Bits 15 to 1--Reserved: These bits are always read as 0. When writing, only 0s should be written here. Bit 0Interrupt Request (INTREQ): Indicates whether or not an interrupt request has been issued by an H-UDI interrupt command. From the CPU, the interrupt request can be cleared by writing a 0 to this bit. If a 1 is written to this bit, it retains the value it had before the write operation. 21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) The boundary scan register (SDBSR) is a shift register that is placed on the pads to control the chip's I/O pins. This register can perform a boundary scan test that conforms to the JTAG standard (IEEE Std 1149.1) using EXTEST, SAMPLE, and PRELOAD commands. Table 21.3 shows the relationship between the SH7750R's pins and the boundary scan register. Rev. 6.0, 07/02, page 806 of 986 Table 21.3 Configuration of the Boundary Scan Register (1) No. Pin Name Type No. 309 IN IN CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 Pin Name A19 A18 A18 SCK2/05(6(7 SCK2/05(6(7 SCK2/05(6(7 MD7/TXD MD7/TXD MD7/TXD MD8/RTS2 MD8/RTS2 MD8/RTS2 TCLK TCLK TCLK CTS2 CTS2 CTS2 NMI ,5/6 ,5/5 ,5/4 ,5/3 MD2/RXD2 MD1/TXD2 MD1/TXD2 MD1/TXD2 MD0/SCK MD0/SCK MD0/SCK RD/:55 RD/:55 D63 D63 D63 D48 D48 Type OUT CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN IN IN IN IN IN IN CTL OUT IN CTL OUT CTL OUT IN CTL OUT IN CTL No. 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 Pin Name D48 D62 D62 D62 D49 D49 D49 D61 D61 D61 D50 D50 D50 D60 D60 D60 D51 D51 D51 D59 D59 D59 D52 D52 D52 D58 D58 D58 D53 D53 D53 D57 D57 D57 D54 D54 D54 Type OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT from TDI 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 &.,25(1% MD6/,2,649 STATUS1 STATUS1 STATUS0 STATUS0 A1 A1 A0 A0 DACK1 DACK1 DACK0 DACK0 MD5/5$65 MD5/5$65 MD5/5$65 MD4/&(5% MD4/&(5% MD4/&(5% MD3/&(5$ MD3/&(5$ MD3/&(5$ A25 A25 A24 A24 A23 A23 A22 A22 A21 A21 A20 A20 A19 Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 6.0, 07/02, page 807 of 986 Table 21.3 Configuration of the Boundary Scan Register (2) No. 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 Pin Name D56 D56 D56 D55 D55 D55 D31 D31 D31 D16 D16 D16 D30 D30 D30 D17 D17 D17 D29 D29 D29 D18 D18 D18 D28 D28 D28 D19 D19 D19 D27 D27 D27 D20 D20 D20 D26 D26 D26 Type IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT No. 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 Pin Name D21 D21 D21 D25 D25 D25 '5(44 '5(43 RXD D22 D22 D22 D24 D24 D24 D23 D23 D23 :(:/&$6:/DQM7/5(* :(:/&$6:/DQM7/5(* :(9/&$69/DQM6 :(9/&$69/DQM6 Type IN CTL OUT IN CTL OUT IN IN IN IN CTL OUT IN CTL OUT IN CTL OUT CTL OUT CTL OUT No. 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 Pin Name DRAK1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 A8 A8 A9 A9 A10 A10 A11 A11 A12 A12 A13 A13 A14 A14 A15 A15 A16 A16 A17 A17 :(3/&$63/DQM0 :(3/&$63/DQM0 :(4/&$64/DQM1 :(4/&$64/DQM1 :(7/&$67/DQM4 :(7/&$67/DQM4 Type OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT :(6/&$66/DQM3/,&,2:5 CTL :(6/&$66/DQM3/,&,2:5 OUT :(5/&$65/DQM2/,&,25' CTL :(5/&$65/DQM2/,&,25' OUT RD/:5 RD/:5 5'/&$66/)5$0( 5'/&$66/)5$0( 5$6 5$6 &65 &65 &66 &66 DRAK0 DRAK0 DRAK1 CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 6.0, 07/02, page 808 of 986 Table 21.3 Configuration of the Boundary Scan Register (3) No. 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 Pin Name :(8/&$68/DQM5 :(8/&$68/DQM5 CKE CKE D7 D7 D7 D8 D8 D8 %5(4/%6$&. %$&./%65(4 %$&./%65(4 D6 D6 D6 D9 D9 D9 D5 D5 D5 D10 D10 D10 D4 D4 D4 D11 D11 D11 D3 D3 D3 D12 D12 D12 D2 D2 D2 Type CTL OUT CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT No. 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 Pin Name D13 D13 D13 D1 D1 D1 D14 D14 D14 D0 D0 D0 D15 D15 D15 D39 D39 D39 D40 D40 D40 D38 D38 D38 D41 D41 D41 D37 D37 D37 D42 D42 D42 D36 D36 D36 D43 D43 D43 D35 Type IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN No. 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Pin Name D35 D35 D44 D44 D44 D34 D34 D34 D45 D45 D45 D33 D33 D33 D46 D46 D46 D32 D32 D32 D47 D47 D47 5'5 5'5 %6 %6 CS6 CS6 CS5 CS5 CS4 CS4 CS1 CS1 CS0 CS0 5'< Type CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT IN to TDO Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 6.0, 07/02, page 809 of 986 21.3 21.3.1 Operation TAP Control Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state transitions specified by JTAG. * The transition condition is the TMS value at the rising edge of TCK. * The TDI value is sampled at the rising edge of TCK, and shifted at the falling edge. * The TDO value changes at the falling edge of TCK. When not in the Shift-DR or Shift-IR state, TDO is in the high-impedance state. * In a transition to 7567 = 0, a transition is made to the Test-Logic-Reset state asynchronously with respect to TCK. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR-Scan 1 Select-IR-Scan 1 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 Figure 21.2 TAP Control State Transition Diagram Rev. 6.0, 07/02, page 810 of 986 21.3.2 H-UDI Reset A power-on reset is effected by an SDIR command. A reset is effected by sending an H-UDI reset assert command, and then sending an H-UDI reset negate command, from the H-UDI pin (see figure 21.3). The interval required between the H-UDI reset assert command and the H-UDI reset negate command is the same as the length of time the reset pin is held low in order to effect a power-on reset. H-UDI pin H-UDI reset assert H-UDI reset negate Chip internal reset CPU state Normal Reset Reset processing Figure 21.3 H-UDI Reset 21.3.3 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command value in SDIR from the H-UDI. The H-UDI interrupt is of general exception/interrupt operation type, with a branch to an address based on VBR and return effected by means of an RTE instruction. The exception code stored in control register INTEVT in this case is H'600. The priority of the H-UDI interrupt can be controlled with bits 3 to 0 of control register IPRC. In the SH7750 or SH7750S, the H-UDI interrupt request signal is asserted for about eight cycles of the LSI's on-chip peripheral clock after the command is set. The number of cycles for assertion is determined by the ratio of TCK to the frequency of the on-chip peripheral clock. Since the period of assertion is limited, the CPU may miss a request. In the SH7750R, the H-UDI interrupt request signal is asserted when the INTREQ bit in the SDINT register is set to 1 after the command is set (Update-IR). The interrupt request signal will not be negated unless a 0 is written to the INTREQ bit by software; therefore, the CPU will not miss a request. As long as the H-UDI interrupt command is set in SDIR, the SDINT register is connected between the TDI and TDO pins. Note that, in the SH7750 or SH7750S, the H-UDI interrupt command automatically becomes a bypass command immediately after it has been set. In the SH7750R, the command is not changed except by the following operations: update in the Update-IR state, initialization in the Test-LogicReset state, and initialization by assertion of#7567. Rev. 6.0, 07/02, page 811 of 986 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only) In the SH7750R, setting a command from the H-UDI in SDIR can place the H-UDI pins in the boundary scan mode that conforms to the JTAG standard. However, the following limitations apply. 1. Boundary scan does not cover clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, and CKIO). 2. Boundary scan does not cover reset-related signals (5(6(7, CA) 3. Boundary scan does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, 7567). 4. With EXTEST, assert the 5(6(7 pin (low), and assert the CA pin (high). With SAMPLE/PRELOAD, assert the CA pin (high). 5. To perform boundary scan, supply a clock to the EXTAL pin, and wait for the power-on oscillation settling time to elapse before starting boundary scan. The frequency range of the input clock is from 1 to 33.3 MHz. Note that after the power-on oscillation settling time has elapsed, a clock does not need to be supplied to the EXTAL pin any longer. For details on the power-on oscillation settling time, see section 22, Electrical Characteristics. 6. In BYPASS mode of the SH7750 or SH7750S, the bypass register (SPDBPR) is not initialized in the Capture-DR state. 21.4 Usage Notes 1. SDIR Command Once an SDIR command has been set, it remains unchanged until initialization by asserting 7567 or placing the TAP in the Test-Logic-Reset state, or until another command (other than an H-UDI interrupt command) is written from the H-UDI. 2. SDIR Commands in Sleep Mode Sleep mode is cleared by an H-UDI interrupt or H-UDI reset, and these exception requests are accepted in this mode. In standby mode, neither an H-UDI interrupt nor an H-UDI reset is accepted. 3. In standby mode, the H-UDI function cannot be used. Furthermore, TCK must be retained at a high level when entering the standby mode in order to retain the TAP state before and after standby mode. 4. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when an emulator is used. 5. The H-UDI pins of the SH7750 and SH7750S must not be connected to a boundary-scan signal loop on the board. Rev. 6.0, 07/02, page 812 of 986 Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 Absolute Maximum Ratings Item I/O, PLL, RTC, CPG power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-RTC VDD-CPG VDD Vin Topr Tstg Value -0.3 to 4.2, -0.3 to 4.2* 2 Unit V Internal power supply voltage Input voltage Operating temperature Storage temperature -0.3 to 2.5, -0.3 to 2.1* -0.3 to VDDQ + 0.3 -20 to 75, -40 to 85* -55 to 125 1 2 V V C C Notes: Permanent damage to the chip may result if the maximum ratings are exceeded. Permanent damage to the chip may result if all VSS pins are not connected to GND. For information on the power-on and power-off procedures, refer to appendix H, Power-On and Power-Off Procedures. *1 HD6417750F167I, HD6417750SF167I only *2 HD6417750R only Rev. 6.0, 07/02, page 813 of 986 22.2 DC Characteristics Table 22.2 DC Characteristics (HD6417750RBP240) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA 1.4 1.5 1.6 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 230 -- -- -- 170 35 -- -- 15 3 580 120 400 800 215 40 440 880 25 5 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 1 1 A mA Ta = 25C* Ta > 50C* 1 1 Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- I = 240 MHz, B = 120 MHz 1 A A V Ta = 25C* Ta > 50C* RTC on* RTC off 2 1 RTC current Standby dissipation mode Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Input leakage All input current pins Three-state leakage current I/O, all output pins (off state) IDD-RTC VIH -- VDDQ x 0.9 2.0 -- -- -- -- -- -- VIL -0.3 -0.3 |Iin| |Isti| -- -- A A VIN = 0.5 to VDDQ -0.5 V VIN = 0.5 to VDDQ -0.5 V Rev. 6.0, 07/02, page 814 of 986 Item Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins Symbol VOH VOL Rpull CL Min 2.4 -- 20 -- Typ -- -- 60 -- Max -- 0.55 180 10 Unit V Test Conditions k pF Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and connect VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the total current value for the 3.3 V versions of VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG. *1 RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) *2 RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. Rev. 6.0, 07/02, page 815 of 986 Table 22.3 DC Characteristics (HD6417750RF240) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 240 MHz 1.4 1.5 1.6 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 230 -- -- -- 140 35 -- -- 15 3 580 120 400 800 180 40 440 880 25 5 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 1 1 A mA 1 Ta = 25C* 1 Ta > 50C* Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- I = 240 MHz, B = 80 MHz Ta = 25C* Ta > 50C* 2 1 A A V 1 RTC current Standby dissipation mode Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Input leakage All input current pins Three-state leakage current I/O, all output pins (off state) IDD-RTC VIH -- VDDQ x 0.9 2.0 RTC on* RTC off -- -- -- -- -- -- VIL -0.3 -0.3 |Iin| |Isti| -- -- A A VIN = 0.5 to VDDQ -0.5 V VIN = 0.5 to VDDQ -0.5 V Rev. 6.0, 07/02, page 816 of 986 Item Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins Symbol VOH VOL Rpull CL Min 2.4 -- 20 -- Typ -- -- 60 -- Max -- 0.55 180 10 Unit V Test Conditions k pF Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the total current value for the 3.3 V versions of VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG. *1 RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) *2 RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. Rev. 6.0, 07/02, page 817 of 986 Table 22.4 DC Characteristics (HD6417750RBP200) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 200 MHz 1.35 1.5 1.6 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 190 -- -- -- 140 30 -- -- 15 3 480 100 400 800 180 35 440 880 25 5 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 1 1 A mA 1 Ta = 25C* 1 Ta > 50C* Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- I = 200 MHz, B = 100 MHz Ta = 25C* Ta > 50C* 2 1 A A V 1 RTC current Standby dissipation mode Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Input leakage All input current pins Three-state leakage current I/O, all output pins (off state) IDD-RTC VIH -- VDDQ x 0.9 2.0 RTC on* RTC off -- -- -- -- -- -- VIL -0.3 -0.3 |Iin| |Isti| -- -- A A VIN = 0.5 to VDDQ -0.5 V VIN = 0.5 to VDDQ -0.5 V Rev. 6.0, 07/02, page 818 of 986 Item Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins Symbol VOH VOL Rpull CL Min 2.4 -- 20 -- Typ -- -- 60 -- Max -- 0.55 180 10 Unit V Test Conditions k pF Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and connect VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG 3.3 V system currents. *1 RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) *2 RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. Rev. 6.0, 07/02, page 819 of 986 Table 22.5 DC Characteristics (HD6417750RF200) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 200 MHz 1.35 1.5 1.6 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 190 -- -- -- 140 30 -- -- 15 3 480 100 400 800 180 35 440 880 25 5 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 1 1 A mA 1 Ta = 25C* 1 Ta > 50C* Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- I = 200 MHz, B = 67 MHz Ta = 25C* Ta > 50C* 2 1 A A V 1 RTC current Standby dissipation mode Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Input leakage All input current pins Three-state leakage current I/O, all output pins (off state) IDD-RTC VIH -- VDDQ x 0.9 2.0 RTC on* RTC off -- -- -- -- -- -- VIL -0.3 -0.3 |Iin| |Isti| -- -- A A VIN = 0.5 to VDDQ -0.5 V VIN = 0.5 to VDDQ -0.5 V Rev. 6.0, 07/02, page 820 of 986 Item Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins Symbol VOH VOL Rpull CL Min 2.4 -- 20 -- Typ -- -- 60 -- Max -- 0.55 180 10 Unit V Test Conditions k pF Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. *1 RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) *2 RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. Rev. 6.0, 07/02, page 821 of 986 Table 22.6 DC Characteristics (HD6417750SBP200) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 200 MHz 1.8 1.95 2.07 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 410 165 -- -- 140 40 -- -- 15 780 210 2000 5000 180 50 2200 5500 25 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 200 MHz, B = 100 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- -- A A Ta = 25C (RTC on*) Ta > 50C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC RTC current During RTC IDD-RTC dissipation operation Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ x 0.9 2.0 -- -- -- -- -- -- 60 -- VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 V VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 822 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 823 of 986 Table 22.7 DC Characteristics (HD6417750SF200) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 200 MHz 1.8 1.95 2.07 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 410 165 -- -- 140 40 -- -- 15 780 210 2000 5000 180 50 2200 5500 25 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 200 MHz, B = 67 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- -- A A Ta = 25C (RTC on*) Ta > 50C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC RTC current During RTC IDD-RTC dissipation operation Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ x 0.9 2.0 -- -- -- -- -- -- 60 -- VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 V VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 824 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 825 of 986 Table 22.8 DC Characteristics (HD6417750BP200M) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 200 MHz 1.8 1.95 2.07 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 1000 165 -- -- 160 40 -- -- -- -- -- -- -- -- 60 -- 1200 -- 2000 5000 200 -- 2200 5500 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 200 MHz, B = 100 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- VDDQ x 0.9 2.0 A V Ta = 25C (RTC on*) Ta > 50C (RTC on*) Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 826 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 827 of 986 Table 22.9 DC Characteristics (HD6417750SF167) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 167 MHz 1.6 1.8 2.0 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 320 120 50 100 140 40 110 220 15 650 150 400 800 180 50 440 880 45 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 167 MHz, B = 84 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- -- A A Ta = 25C (RTC on*) Ta > 50C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC RTC current During RTC IDD-RTC dissipation operation Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ x 0.9 2.0 -- -- -- -- -- -- 60 -- VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 V VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 828 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 829 of 986 Table 22.10 DC Characteristics (HD6417750SF167I) Ta = -40 to +85C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 167 MHz 1.6 1.8 2.0 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 320 140 50 100 180 50 110 220 15 650 175 400 880 220 65 440 960 45 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 167 MHz, B = 84 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- -- A A Ta = 25C (RTC on*) Ta > 50C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC RTC current During RTC IDD-RTC dissipation operation Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ x 0.9 2.0 -- -- -- -- -- -- 60 -- VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 V VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 830 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 831 of 986 Table 22.11 DC Characteristics (HD6417750F167) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 167 MHz 1.6 1.8 2.0 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 630 120 -- -- 160 40 -- -- -- -- -- -- -- -- 60 -- 700 -- 400 800 200 -- 440 880 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 167 MHz, B = 84 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- VDDQ x 0.9 2.0 A V Ta = 25C (RTC on*) Ta > 50C (RTC on*) Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 832 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 833 of 986 Table 22.12 DC Characteristics (HD6417750F167I) Ta = -40 to +85C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 167 MHz 1.6 1.8 2.0 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 720 140 50 100 180 50 110 220 -- -- -- -- -- -- 60 -- 800 -- 400 880 220 -- 440 960 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 167 MHz, B = 83 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- VDDQ x 0.9 2.0 A V Ta = 25C (RTC on*) Ta > 50C (RTC on*) Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 834 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 835 of 986 Table 22.13 DC Characteristics (HD6417750SVF133) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 133 MHz, B = 66 MHz 1.4 1.5 1.7 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 210 50 -- -- 80 35 -- -- 15 520 60 100 200 160 40 110 220 25 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 133 MHz, B = 67 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- -- A A Ta = 25C (RTC on*) Ta > 50C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC RTC current During RTC IDD-RTC dissipation operation Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ x 0.9 2.0 -- -- -- -- -- -- 60 -- VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 V VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 836 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 837 of 986 Table 22.14 DC Characteristics (HD6417750SVBT133) Ta = -30 to +70C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 133 MHz, B = 66 MHz 1.4 1.5 1.7 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- 210 50 -- -- 80 35 -- -- 15 520 60 100 200 160 40 110 220 45 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 133 MHz, B = 67 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- -- A A Ta = 25C (RTC on*) Ta > 50C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC RTC current During RTC IDD-RTC dissipation operation Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ x 0.9 2.0 -- -- -- -- -- -- 60 -- VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 V VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 838 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev. 6.0, 07/02, page 839 of 986 Table 22.15 DC Characteristics (HD6417750VF128) Ta = -20 to +75C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA I = 128 MHz, B = 64 MHz 1.4 1.5 1.7 Current dissipation Normal operation Sleep mode Standby mode IDD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60 -- 520 60 100 200 160 40 110 220 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.1 VDDQ x 0.2 -- 0.55 180 10 A mA Ta = 25C (RTC on*) Ta > 50C (RTC on*) I = 128 MHz, B = 64 MHz Current dissipation Normal operation Sleep mode Standby mode IDDQ -- -- -- -- VDDQ x 0.9 2.0 A V Ta = 25C (RTC on*) Ta > 50C (RTC on*) Input voltage 5(6(7, NMI, 7567 Other input pins 5(6(7, NMI, 7567 Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VIL -0.3 -0.3 VOH VOL Rpull CL 2.4 -- 20 -- V k pF Rev. 6.0, 07/02, page 840 of 986 Notes: 1. Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ - 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Table 22.16 Permissible Output Currents Ta = -20 to +75C Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Symbol IOL IOL -IOH (-IOH) Min -- -- -- -- Typ -- -- -- -- Max 2 120 2 40 Unit mA Note: To protect chip reliability, do not exceed the output current values in table 22.16. Rev. 6.0, 07/02, page 841 of 986 22.3 AC Characteristics In principle, SH7750 Series input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 22.17 Clock Timing (HD6417750RBP240) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ -- -- -- Max 240 120 60 Unit MHz Table 22.18 Clock Timing (HD6417750RF240) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ -- -- -- Max 240 84 60 Unit MHz Table 22.19 Clock Timing (HD6417750BP200M, HD6417750SBP200, HD6417750RBP200) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ -- -- -- Max 200 100 50 Unit MHz Table 22.20 Clock Timing (HD6417750RF200) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ -- -- -- Max 200 84 50 Unit MHz Table 22.21 Clock Timing (HD6417750SF200) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ -- -- -- Max 200 67 50 Unit MHz Rev. 6.0, 07/02, page 842 of 986 Table 22.22 Clock Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ -- -- -- Max 167 84 42 Unit MHz Table 22.23 Clock Timing (HD6417750SVF133, HD6417750SVBT133) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ -- -- -- Max 134 67 34 Unit MHz Table 22.24 Item Operating frequency Clock Timing (HD6417750VF128) Symbol CPU, FPU, cache, TLB External bus Peripheral modules f Min 1 1 1 Typ -- -- -- Max 128 64 32 Unit MHz Rev. 6.0, 07/02, page 843 of 986 22.3.1 Clock and Control Signal Timing Table 22.25 Clock and Control Signal Timing (HD6417750RBP240) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = -20 to +75C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation PLL1 12-times/PLL2 operation PLL1/PLL2 not operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operating PLL1/PLL2 not operating Symbol fEX fEX fEX tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL tOSC2 tOSC3 Min 16 14 1 30 3.5 3.5 -- -- 25 1 8.3 1 1 -- -- 3 3 10 10 20 20 3 20 20 200 3 3 Max 34 20 34 1000 -- -- 4 4 120 34 1000 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc s ms ms 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.7 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time 5(6(7 assert time PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Rev. 6.0, 07/02, page 844 of 986 Item Standby return oscillation settling time 3 Symbol tOSC4 Min 3 2 2 2 -- 0 Max -- -- -- -- 200 -- Unit ms ms ms ms s ns Figure 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 845 of 986 Table 22.26 Clock and Control Signal Timing (HD6417750RF240) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = -20 to +75C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation PLL1 12-times/PLL2 operation PLL1/PLL2 not operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operating PLL1/PLL2 not operating Symbol fEX fEX fEX tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL tOSC2 tOSC3 tOSC4 Min 16 14 1 30 3.5 3.5 -- -- 25 1 11.9 1 1 -- -- 3 3 10 10 20 20 3 20 20 200 3 3 3 Max 34 20 34 1000 -- -- 4 4 84 34 1000 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc s ms ms ms 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.7 22.8 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time 5(6(7 assert time PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Rev. 6.0, 07/02, page 846 of 986 Item Symbol Min 2 2 2 -- 0 Max -- -- -- 200 -- Unit ms ms ms s ns Figure Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 847 of 986 Table 22.27 Clock and Control Signal Timing (HD6417750RBP200) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = -20 to +75C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation PLL1 12-times/PLL2 operation PLL1/PLL2 not operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operating PLL1/PLL2 not operating Symbol fEX fEX fEX tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL tOSC2 tOSC3 tOSC4 Min 16 14 1 30 3.5 3.5 -- -- 25 1 10 1 1 -- -- 3 3 10 10 20 20 3 20 20 200 5 5 5 Max 34 17 34 1000 -- -- 4 4 100 100 1000 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc s ms ms ms 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.7 22.8 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time 5(6(7 assert time PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Rev. 6.0, 07/02, page 848 of 986 Item Symbol Min 2 2 2 -- 0 Max -- -- -- 200 -- Unit ms ms ms s ns Figure Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 849 of 986 Table 22.28 Clock and Control Signal Timing (HD6417750RF200) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = -20 to +75C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation PLL1 12-times/PLL2 operation PLL1/PLL2 not operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operating PLL1/PLL2 not operating Symbol fEX fEX fEX tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL tOSC2 tOSC3 tOSC4 Min 16 14 1 30 3.5 3.5 -- -- 25 1 11.9 1 1 -- -- 3 3 10 10 20 20 3 20 20 200 5 5 5 Max 34 17 34 1000 -- -- 4 4 84 34 1000 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc s ms ms ms 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.7 22.8 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time 5(6(7 assert time PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Rev. 6.0, 07/02, page 850 of 986 Item Symbol Min 2 2 2 -- 0 Max -- -- -- 200 -- Unit ms ms ms s ns Figure Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 851 of 986 Table 22.29 Clock and Control Signal Timing (HD6417750BP200M, HD6417750SBP200) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = -20 to +75C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 15 3.5 3.5 -- -- 25 1 10 1 1 -- -- 3 3 10 10 20 20 3 20 20 200 Max 67 34 67 34 1000 -- -- 4 4 100 100 1000 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc s 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time 5(6(7 assert time PLL synchronization settling time Rev. 6.0, 07/02, page 852 of 986 Item Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tOSC2 tOSC3 tOSC4 Min 10 5 5 2 2 2 -- 0 Max -- -- -- -- -- -- 200 -- Unit ms ms ms ms ms ms s ns Figure 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 853 of 986 Table 22.30 Clock and Control Signal Timing (HD6417750SF200) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = -20 to +75C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 15 3.5 3.5 -- -- 25 1 10 1 1 -- -- 3 3 10 10 20 20 3 20 20 200 Max 67 34 67 34 1000 -- -- 4 4 67 67 1000 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc s 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time 5(6(7 assert time PLL synchronization settling time Rev. 6.0, 07/02, page 854 of 986 Item Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tOSC2 tOSC3 tOSC4 Min 10 5 5 2 2 2 -- 0 Max -- -- -- -- -- -- 200 -- Unit ms ms ms ms ms ms s ns Figure 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 855 of 986 Table 22.31 Clock and Control Signal Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I) HD6417750SF167, HD6417750F167: VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = -20 to +75C, CL = 30 pF HD6417750SF167I, HD6417750F167I: VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = -40 to +85C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 18 3.5 3.5 -- -- 25 1 12 1 1 -- -- 3 3 10 10 20 20 3 20 Max 56 28 56 28 1000 -- -- 4 4 84 84 1000 -- -- 3 3 -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time Rev. 6.0, 07/02, page 856 of 986 Item 5(6(7 assert time PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tRESW tPLL tOSC2 tOSC3 tOSC4 Min 20 200 10 5 5 2 2 2 -- 0 Max -- -- -- -- -- -- -- -- 200 -- Unit tcyc s ms ms ms ms ms ms s ns Figure 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 28 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 857 of 986 Table 22.32 Clock and Control Signal Timing (HD6417750SVF133, HD6417750SVBT133) HD6417750SVBT133: VDDQ = 3.0 to 3.6 V, VDD = 1.5 V typ, Ta = -30 to +70C, CL = 30 pF HD6417750SVF133: VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = -20 to +75C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 22 3.5 3.5 -- -- 25 1 14 1 1 -- -- 3 3 10 10 20 20 3 20 20 200 Max 45 23 45 23 1000 -- -- 4 4 67 67 1000 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc s 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time 5(6(7 assert time PLL synchronization settling time Rev. 6.0, 07/02, page 858 of 986 Item Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tOSC2 tOSC3 tOSC4 Min 10 5 5 2 2 2 -- 0 Max -- -- -- -- -- -- 200 -- Unit ms ms ms ms ms ms s ns Figure 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 23 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 859 of 986 Table 22.33 Clock and Control Signal Timing (HD6417750VF128) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = -20 to +75C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 23 3.5 3.5 -- -- 25 1 15 1 1 -- -- 3 3 10 10 20 20 3 20 20 200 Max 43 22 43 22 1000 -- -- 4 4 64 64 1000 -- -- 3 3 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc s 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time 5(6(7 assert time PLL synchronization settling time Rev. 6.0, 07/02, page 860 of 986 Item Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tOSC2 tOSC3 tOSC4 Min 10 5 5 2 2 2 -- 0 Max -- -- -- -- -- -- 200 -- Unit ms ms ms ms ms ms s ns Figure 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) 7567 reset hold time tIRLSTB tTRSTRH 22.10 22.3, 22.5 Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 22 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev. 6.0, 07/02, page 861 of 986 tEXcyc tEXH tEXL VIH 1/2VDDQ VIH VIL tEXf VIL VIH 1/2VDDQ tEXr Note: When the clock is input from the EXTAL pin Figure 22.1 EXTAL Clock Input Timing tcyc tCKOH1 tCKOL1 VOH 1/2VDDQ VOH VOL tCKOf VOL VOH 1/2VDDQ tCKOr Figure 22.2(1) CKIO Clock Output Timing tCKOH2 tCKOL2 1.5 V 1.5 V 1.5 V Figure 22.2(2) CKIO Clock Output Timing Rev. 6.0, 07/02, page 862 of 986 Stable oscillation CKIO, internal clock VDD VDD min tRESW tOSC1 tSCK2RH SCK2 tOSCMD MD8, MD7, MD2-MD0 tTRSTRH tMDRH Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 not operating Figure 22.3 Power-On Oscillation Settling Time Standby CKIO, internal clock tRESW tOSC2 Stable oscillation Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 not operating Figure 22.4 Standby Return Oscillation Settling Time (Return by 5(6(7 5(6(7) Rev. 6.0, 07/02, page 863 of 986 Stable oscillation Internal clock VDD VDD min tRESW tOSC1 tSCK2RH SCK2 tOSCMD MD8, MD7, MD2-MD0 tTRSTRH tMDRH CKIO Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 operating Figure 22.5 Power-On Oscillation Settling Time Standby Internal clock tRESW tOSC2 Stable oscillation CKIO Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 operating Figure 22.6 Standby Return Oscillation Settling Time (Return by 5(6(7 5(6(7) Rev. 6.0, 07/02, page 864 of 986 Standby CKIO, internal clock tOSC3 Stable oscillation NMI Note: Oscillation settling time when on-chip resonator is used Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI) Standby CKIO, internal clock tOSC4 Stable oscillation - Note: Oscillation settling time when on-chip resonator is used Figure 22.8 Standby Return Oscillation Settling Time (Return by ,5/6 ,5/3 ,5/6-,5/3 ,5/3) Rev. 6.0, 07/02, page 865 of 986 Reset or NMI interrupt request Stable input clock EXTAL input PLL synchronization PLL output, CKIO output tPLL x 2 PLL synchronization Stable input clock Internal clock STATUS1- STATUS0 Normal Standby Normal Note: When external clock from EXTAL is input Figure 22.9 PLL Synchronization Settling Time in Case of 5(6(7 or NMI Interrupt - interrupt request Stable input clock Stable input clock EXTAL input PLL synchronization PLL output, CKIO output tIRLSTB tPLL x 2 PLL synchronization Internal clock STATUS1- STATUS0 Normal Standby Normal Note: When external clock from EXTAL is input Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt Rev. 6.0, 07/02, page 866 of 986 CKIO tRESW tSCK2RS tSCK2RH SCK2 Figure 22.11 Manual Reset Input Timing tMDRS tMDRH MD6-MD3 Figure 22.12 Mode Input Timing Rev. 6.0, 07/02, page 867 of 986 22.3.2 Control Signal Timing Table 22.34 Control Signal Timing (1) HD6417750 RBP240 * Item %5(4 setup time %5(4 hold time %$&. delay time Bus tri-state delay time Bus tri-state delay time to standby mode Bus buffer on time Bus buffer on time from standby STATUS0/1 delay time STATUS0/1 delay time to standby Symbol Min tBREQS tBREQH tBACKD tBOFF1 tBOFF2 2 1.5 -- -- -- Max -- -- 5.3 12 2 Min 2.5 1.5 -- -- -- HD6417750 RBP200 * Max -- -- 6 12 2 Min 3.5 1.5 -- -- -- HD6417750 RF240 * Max -- -- 6 12 2 Min 3.5 1.5 -- -- -- HD6417750 RF200 * Max -- -- 6 12 2 Unit Figure ns ns ns ns tcyc 22.13 22.13 22.13 22.13 22.14 Notes tBON1 tBON2 -- -- 12 1 -- -- 12 1 -- -- 12 1 -- -- 12 1 ns tcyc 22.13 22.14 tSTD1 tSTD2 -- -- 5 2 -- -- 6 2 -- -- 6 2 -- -- 6 2 ns tcyc 22.14 22.14 Note: * VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on Rev. 6.0, 07/02, page 868 of 986 Table 22.34 Control Signal Timing (2) HD6417750 F167 HD6417750 F167I HD6417750 SF167 HD6417750 SF167I HD6417750 SF200 *2 Min 3.5 1.5 -- -- -- Max -- -- 8 12 2 HD6417750 VF128 *1 Item %5(4 setup time %5(4 hold time %$&. delay time Bus tri-state delay time Bus tri-state delay time to standby mode Bus buffer on time Bus buffer on time from standby STATUS0/1 delay time STATUS0/1 delay time to standby Symbol Min tBREQS tBREQH tBACKD tBOFF1 tBOFF2 3.5 1.5 -- -- -- Max -- -- 10 15 2 HD6417750 SVF133 HD6417750 SVBT133 *1 Min 3.5 1.5 -- -- -- Max -- -- 10 15 2 HD6417750 BP200M HD6417750 SBP200 *3 Min 3 1.5 -- -- -- Max -- -- 6 10 2 Unit Figure ns ns ns ns tcyc 22.13 22.13 22.13 22.13 22.14 Notes tBON1 tBON2 -- -- 15 1 -- -- 15 1 -- -- 12 1 -- -- 10 1 ns tcyc 22.13 22.14 tSTD1 tSTD2 -- -- 11 2 -- -- 11 2 -- -- 9 2 -- -- 7 2 ns tcyc 22.14 22.14 Notes: *1 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on *2 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on (HD6417750F167, HD6417750SF167, HD6417750SF200) VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -40 to +85C, CL = 30 pF, PLL2 on (HD6417750F167I, HD6417750SF167I) *3 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on Rev. 6.0, 07/02, page 869 of 986 CKIO tBREQH tBREQS tBREQH tBREQS tBACKD tBACKD A[25-0], , RD/ , RD/ , , , , , , , tBOFF1 tBON1 Figure 22.13 Control Signal Timing Normal operation Standby mode Normal operation CKIO STATUS 0, STATUS 1 Normal tSTD2 , , , RD/ A25-A0, D63-D0 DACKn, DRAKn, SCK, , * TXD, TXD2, , RD/ , , , , , Standby tSTD1 Normal , tBOFF2 tBON2 Note: * When the PHZ bit in STBCR is set to 1, these pins go to the high-impedance state (except for pins being used as port pins, which retain their port state). Figure 22.14 Pin Drive Timing for Standby Mode Rev. 6.0, 07/02, page 870 of 986 22.3.3 Bus Timing Table 22.35 Bus Timing (1) HD6417750 RBP240 * Item Address delay time %6 delay time &6 delay time 5: delay time 5' delay time Read data setup time Read data hold time :( delay time (falling edge) Symbol tAD tBSD tCSD tRWD tRSD tRDS tRDH tWEDF Min 1.5 1.5 1.5 1.5 1.5 2 1.5 -- Max 5.3 5.3 5.3 5.3 5.3 -- -- 5.3 Min 1.5 1.5 1.5 1.5 1.5 2.5 1.5 -- HD6417750 RBP200 * Max 6 6 6 6 6 -- -- 6 Min 1.5 1.5 1.5 1.5 1.5 3.5 1.5 -- HD6417750 RF240 * Max 6 6 6 6 6 -- -- 6 Min 1.5 1.5 1.5 1.5 1.5 3.5 1.5 -- HD6417750 RF200 * Max 6 6 6 6 6 -- -- 6 Unit ns ns ns ns ns ns ns ns Relative to CKIO falling edge Notes :( delay time Write data delay time 5'< setup time 5'< hold time 5$6 delay time &$6 delay time 1 &$6 delay time 2 CKE delay time DQM delay time )5$0( delay time ,2,649 setup time ,2,649 hold time ,&,2:5 delay time (falling edge) ,&,25' delay time DACK delay time DACK delay time (falling edge) tWED1 tWDD tRDYS tRDYH tRASD tCASD1 tCASD2 tCKED tDQMD tFMD tIO16S tIO16H tICWSDF tICRSD tDACD tDACDF 1.5 1.5 2 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2 1.5 1.5 1.5 1.5 1.5 5.3 5.3 -- -- 5.3 5.3 5.3 5.3 5.3 5.3 -- -- 5.3 5.3 5.3 5.3 1.5 1.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 1.5 1.5 1.5 1.5 6 6 -- -- 6 6 6 6 6 6 -- -- 6 6 6 6 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 6 6 -- -- 6 6 6 6 6 6 -- -- 6 6 6 6 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 6 6 -- -- 6 6 6 6 6 6 -- -- 6 6 6 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Relative to CKIO falling edge DRAM SDRAM SDRAM SDRAM MPX PCMCIA PCMCIA PCMCIA PCMCIA Rev. 6.0, 07/02, page 871 of 986 HD6417750 RBP240 * Item DTR setup time DTR hold time '%5(4 setup time '%5(4 hold time 75 setup time 75 hold time %$9/ delay time 7'$&. delay time ID1, ID0 delay time Symbol tDTRS tDTRH tDBQS tDBQH tTRS tTRH tBAVD tTDAD tIDD Min 2.0 1.5 2.0 1.5 2.0 1.5 1.5 1.5 1.5 Max -- -- -- -- -- -- 5.3 5.3 5.3 HD6417750 RBP200 * Min 2.5 1.5 2.5 1.5 2.5 1.5 1.5 1.5 1.5 Max -- -- -- -- -- -- 6 6 6 HD6417750 RF240 * Min 3.5 1.5 3.5 1.5 3.5 1.5 1.5 1.5 1.5 Max -- -- -- -- -- -- 6 6 6 HD6417750 RF200 * Min 3.5 1.5 3.5 1.5 3.5 1.5 1.5 1.5 1.5 Max -- -- -- -- -- -- 6 6 6 Unit ns ns ns ns ns ns ns ns ns Notes Note: * VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on Rev. 6.0, 07/02, page 872 of 986 Table 22.35 Bus Timing (2) HD6417750 SF167 HD6417750 SVF133 HD6417750 SVBT133 *1 Item Address delay time %6 delay time &6 delay time 5: delay time 5' delay time Read data setup time Read data hold time :( delay time (falling edge) :( delay time Write data delay time 5'< setup time 5'< hold time 5$6 delay time &$6 delay time 1 &$6 delay time 2 CKE delay time DQM delay time )5$0( delay time ,2,649 setup time ,2,649 hold time ,&,2:5 delay time (falling edge) ,&,25' delay time DACK delay time DACK delay time (falling edge) Symbol tAD tBSD tCSD tRWD tRSD tRDS tRDH tWEDF tWED1 tWDD tRDYS tRDYH tRASD tCASD1 tCASD2 tCKED tDQMD tFMD tIO16S tIO16H tICWSDF tICRSD tDACD tDACDF Min 1.5 1.5 1.5 1.5 1.5 3.5 1.5 -- 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 Max 10 10 10 10 10 -- -- 10 10 10 -- -- 10 10 10 10 10 10 -- -- 10 10 10 10 Min 1.5 1.5 1.5 1.5 1.5 3.5 1.5 -- 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 HD6417750 SF167I HD6417750 SF200 *2 Max 8 8 8 8 8 -- -- 8 8 8 -- -- 8 8 8 8 8 8 -- -- 8 8 8 8 Min 1.5 1.5 1.5 1.5 1.5 3 1.5 -- 1.5 1.5 3 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3 1.5 1.5 1.5 1.5 1.5 HD6417750 SBP200 *3 Max 6 6 6 6 6 -- -- 6 6 6 -- -- 6 6 6 6 6 6 -- -- 6 6 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Relative to CKIO falling edge DRAM SDRAM SDRAM SDRAM MPX PCMCIA PCMCIA PCMCIA PCMCIA Relative to CKIO falling edge Notes Rev. 6.0, 07/02, page 873 of 986 HD6417750 SF167 HD6417750 SVF133 HD6417750 SVBT133 *1 Item DTR setup time DTR hold time '%5(4 setup time '%5(4 hold time 75 setup time 75 hold time %$9/ delay time 7'$&. delay time ID1, ID0 delay time Symbol tDTRS tDTRH tDBQS tDBQH tTRS tTRH tBAVD tTDAD tIDD Min 3.5 1.5 3.5 1.5 3.5 1.5 1.5 1.5 1.5 Max -- -- -- -- -- -- 10 10 10 Min 3.5 1.5 3.5 1.5 3.5 1.5 1.5 1.5 1.5 HD6417750 SF167I HD6417750 SF200 *2 Max -- -- -- -- -- -- 8 8 8 Min 3 1.5 3 1.5 3 1.5 1.5 1.5 1.5 HD6417750 SBP200 *3 Max -- -- -- -- -- -- 6 6 6 Unit ns ns ns ns ns ns ns ns ns Notes Notes: *1 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on *2 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on (HD6417750SF167, HD6417750SF200) VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -40 to +85C, CL = 30 pF, PLL2 on (HD6417750SF167I) *3 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on Rev. 6.0, 07/02, page 874 of 986 Table 22.35 Bus Timing (3) HD6417750 F167 HD6417750 VF128 *1 Item Address delay time %6 delay time &6 delay time 5: delay time 5' delay time Read data setup time Read data hold time :( delay time (falling edge) :( delay time Write data delay time 5'< setup time 5'< hold time 5$6 delay time &$6 delay time 1 &$6 delay time 2 CKE delay time DQM delay time )5$0( delay time ,2,649 setup time ,2,649 hold time ,&,2:5 delay time (falling edge) ,&,25' delay time DACK delay time DACK delay time (falling edge) Symbol tAD tBSD tCSD tRWD tRSD tRDS tRDH tWEDF tWED1 tWDD tRDYS tRDYH tRASD tCASD1 tCASD2 tCKED tDQMD tFMD tIO16S tIO16H tICWSDF tICRSD tDACD tDACDF Min 1.3 1.3 1.3 1.3 1.3 3.5 1.5 -- 1.3 1.3 3.5 1.5 1.3 1.3 1.3 0.5 1.3 1.3 3.5 1.5 1.3 1.3 1.3 1.3 Max 10 10 10 10 10 -- -- 10 10 10 -- -- 10 10 10 10 10 10 -- -- 10 10 10 10 Min 1.3 1.3 1.3 1.3 1.3 3.5 1.5 -- 1.3 1.3 3.5 1.5 1.3 1.3 1.3 0.5 1.3 1.3 3.5 1.5 1.3 1.3 1.3 1.3 HD6417750 F167I *2 Max 8 8 8 8 8 -- -- 8 8 8 -- -- 8 8 8 8 8 8 -- -- 8 8 8 8 Min 1.2 1.2 1.2 1.2 1.2 3 1.5 -- 1.2 1.2 3 1.5 1.2 1.2 1.2 0.5 1.2 1.2 3 1.5 1.2 1.2 1.2 1.2 HD6417750 BP200M *3 Max 6 6 6 6 6 -- -- 6 6 6 -- -- 6 6 6 6 6 6 -- -- 6 6 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Relative to CKIO falling edge DRAM SDRAM SDRAM SDRAM MPX PCMCIA PCMCIA PCMCIA PCMCIA Relative to CKIO falling edge Notes Rev. 6.0, 07/02, page 875 of 986 HD6417750 F167 HD6417750 VF128 *1 Item DTR setup time DTR hold time '%5(4 setup time '%5(4 hold time 75 setup time 75 hold time %$9/ delay time 7'$&. delay time ID1, ID0 delay time Symbol tDTRS tDTRH tDBQS tDBQH tTRS tTRH tBAVD tTDAD tIDD Min 3.5 1.5 3.5 1.5 3.5 1.5 1.3 1.3 1.3 Max -- -- -- -- -- -- 10 10 10 Min 3.5 1.5 3.5 1.5 3.5 1.5 1.3 1.3 1.3 HD6417750 F167I *2 Max -- -- -- -- -- -- 8 8 8 Min 3 1.5 3 1.5 3 1.5 1.2 1.2 1.2 HD6417750 BP200M *3 Max -- -- -- -- -- -- 6 6 6 Unit ns ns ns ns ns ns ns ns ns Notes Notes: *1 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on *2 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on (HD6417750F167) VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -40 to +85C, CL = 30 pF, PLL2 on (HD6417750F167I) *3 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on Rev. 6.0, 07/02, page 876 of 986 T1 CKIO T2 tAD A25-A0 tAD tCSD tCSD tRWD RD/ tRWD tRSD tRSD tRSD D63-D0 (read) tRDS tWED1 tRDH tWEDF tWEDF tWDD D63-D0 (write) tWDD tWDD tBSD tBSD tDACD DACKn (SA: IO memory) tDACD tDACD tDACDF DACKn (SA: IO memory) tDACDF tDACD DACKn (DA) tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait) Rev. 6.0, 07/02, page 877 of 986 T1 CKIO Tw T2 tAD A25-A0 tAD tCSD tCSD tRWD RD/ tRWD tRSD tRSD tRSD D63-D0 tRDS tWED1 tRDH (read) tWEDF tWEDF tWDD D63-D0 tWDD tWDD (write) tBSD tBSD tRDYS tRDYH tDACD DACKn (SA: IO memory) tDACD tDACD tDACDF DACKn (SA: IO memory) tDACDF tDACD DACKn (DA) tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) Rev. 6.0, 07/02, page 878 of 986 T1 CKIO Tw Twe T2 tAD A25-A0 tAD tCSD tCSD tRWD RD/ tRWD tRSD tRSD tRSD D63-D0 (read) tRDS tWED1 tRDH tWEDF tWEDF tWDD D63-D0 (write) tWDD tWDD tBSD tBSD tRDYS tRDYH tRDYS tRDYH tDACD tDACD DACKn (SA: IO memory) tDACD tDACDF DACKn (SA: IO memory) tDACDF tDACD DACKn (DA) tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) Rev. 6.0, 07/02, page 879 of 986 TS1 CKIO T1 T2 TH1 tAD A25-A0 tAD tCSD tCSD tRWD RD/ tRWD tRSD tRSD * tRSD D63-D0 (read) tRDS tWED1 tRDH tWEDF tWEDF tWDD D63-D0 (write) tWDD tWDD tBSD tBSD tDACD DACKn (SA: IO memory) tDACD tDACD tDACDF DACKn (SA: IO memory) tDACDF DACKn (DA) tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high * SH7750R only Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Rev. 6.0, 07/02, page 880 of 986 T1 CKIO TB2 TB1 TB2 TB1 TB2 TB1 T2 tAD A25-A5 tAD tAD A4-A0 tCSD tRWD RD/ tCSD tRWD tRSD tRDH tRDS tRSD tRDH tRSD D31-D0 (read) tRDS tBSD tBSD tDACD tDACD DACKn (SA: IO memory) DACKn (DA) tDACD tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.19 Burst ROM Bus Cycle (No Wait) Rev. 6.0, 07/02, page 881 of 986 T1 CKIO Tw Twe TB2 TB1 Twb TB2 TB1 Twb TB2 TB1 Twb T2 tAD A25-A5 tAD tAD A4-A0 Rev. 6.0, 07/02, page 882 of 986 tCSD tRWD RD/ tCSD tRWD tRSD tRSD tRDS tRDH tRDS tRDH D31-D0 (read) tBSD tRDYS tDACD tDACD tDACD tRDYS tRDYH tDACD tRDYH tRDYS tRDYH DACKn (SA: IO memory) DACKn (DA) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait) TS1 T1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 T2 TH1 CKIO tAD tAD tCSD tRWD tRSD tRDS tBSD tBSD tRDH tRDS tRDH tAD A25-A5 A4-A0 tCSD tRWD tRSD RD/ D31-D0 (read) DACKn (SA: IO memory) tDACD tDACD tDACD tDACD Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) DACKn (DA) tDACD Rev. 6.0, 07/02, page 883 of 986 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high T1 Twb Tw Twe TB2 TB1 Twb Twbe TB2 TB1 Twb Twbe TB2 TB1 Twbe T2 CKIO tAD tAD tCSD tRWD tRSD tRDS tBSD tBSD tRDH tBSD tBSD tRSD tRDS tAD A25-A5 A4-A0 Rev. 6.0, 07/02, page 884 of 986 tCSD tRWD tRSD tRDH tRDYS tRDYS tDACD tDACD tDACD tRDYH tRDYH tRDYS tRDYH tRDYS tRDYH tDACD tDACD RD/ D31-D0 (read) DACKn (SA: IO memory) Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) DACKn (DA) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc Tpc Tpc tAD BANK Row tAD tAD Precharge-sel Row H/L Address Row column tCSD tRWD RD/ tCSD tRWD tRASD tCASD2 tCASD2 tRASD tCASD2 tDQMD DQMn tDQMD tRDS tRDH d0 D63-D0 (read) tWDD tWDD tBSD tBSD D63-D0 (write) CKE tDACD DACKn (SA: IO memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) tDACD tDACD Rev. 6.0, 07/02, page 885 of 986 Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc Tpc Tpc tAD tAD tAD Precharge-sel Row H/L BANK Row Address Row c0 Rev. 6.0, 07/02, page 886 of 986 tCSD tRWD RD/ tCSD tRWD tRASD tCASD2 tCASD2 tRASD tCASD2 tDQMD DQMn tDQMD tRDH tRDS d0 d1 d2 d3 D63-D0 (read) tWDD D63-D0 (write) tWDD tBSD tBSD CKE Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) tDACD DACKn (SA: IO memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high tDACD tDACD Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 tAD BANK Row tAD tAD H/L tRWD Precharge-sel Row tRWD Address Row c0 tCSD tRWD RD/ tCSD tRWD tRASD tRASD tCASD2 tCASD2 tCASD2 tDQMD tDQMD DQMn D63-D0 (read) D63-D0 (write) tRDS d0 tRDH d1 d2 d3 tWDD tBSD tBSD tWDD tDACD DACKn (SA: IO memory) tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD[1:0] = 01, CAS Latency = 3) Rev. 6.0, 07/02, page 887 of 986 Tpr CKIO Tpc Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 tAD BANK tAD Row tAD tAD Precharge-sel Row H/L Address Row c0 tCSD tRWD RD/ tCSD tRWD tRASD tRASD tRASD tRASD tCASD2 tCASD2 tDQMD tCASD2 tDQMD DQMn D63-D0 (read) D63-D0 (write) tRDS d0 tRDH d1 d2 d3 tWDD tBSD tBSD tWDD DACKn (SA: IO memory) tDACD tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3) Rev. 6.0, 07/02, page 888 of 986 Tc1 CKIO Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 tAD BANK Row tAD Precharge-sel H/L Address c0 tCSD tCSD tRWD RD/ tRWD tRASD tRASD tCASD2 tCASD2 tDQMD DQMn tDQMD D63-D0 (read) tRDS d0 tRDH d1 d2 d3 D63-D0 (write) tWDD tWDD tBSD tBSD tDACD DACKn (SA: IO memory) tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency = 3) Rev. 6.0, 07/02, page 889 of 986 Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc tAD BANK Row tAD tAD Precharge-sel Row H/L Address Row Column tCSD tCSD tRWD RD/ tRWD tRASD tRASD tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD tWDD D63-D0 (write) tWDD c0 tWDD tBSD tBSD CKE DACKn (SA: IO memory) tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Rev. 6.0, 07/02, page 890 of 986 Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc tAD BANK Row tAD tAD Precharge-sel Row H/L Address Row c0 tCSD tRWD RD/ tCSD tRWD tRASD tRASD tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD tWDD tWDD D63-D0 (write) d0 tWDD d1 d2 d3 tBSD tBSD CKE DACKn (SA: IO memory) tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Rev. 6.0, 07/02, page 891 of 986 Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl tAD BANK Row tAD tAD Precharge-sel Row H/L Address Row c0 tCSD tRWD RD/ tCSD tRWD tRASD tRASD tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD tWDD D63-D0 (write) tWDD d0 tWDD d1 d2 d3 tBSD tBSD CKE tDACD DACKn tDACD (SA: IO memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010) Rev. 6.0, 07/02, page 892 of 986 Tpr CKIO Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl tAD BANK Row tAD Row tAD tAD Precharge-sel H/L Row H/L Address Row c0 tCSD tRWD RD/ tCSD tRWD tRASD tRASD tRASD tRWD tRWD tRASD tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD tWDD D63-D0 (write) tWDD d0 tWDD d1 d2 d3 tBSD tBSD CKE tDACD DACKn (SA: IO memory) tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Rev. 6.0, 07/02, page 893 of 986 Tnop CKIO (Tnop) Tc1 Tc2 Tc3 Tc4 Trwl Trwl tAD BANK Row tAD Precharge-sel H/L Address c0 tCSD tCSD tRWD RD/ tRWD tCASD2 tCASD2 tDQMD DQMn tDQMD tWDD tWDD D63-D0 (write) d0 tWDD d1 d2 d3 tBSD tBSD CKE tDACD DACKn (SA: IO memory) SA-DMA tDACD Normal write Notes: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line. IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL[2:0] = 010) Rev. 6.0, 07/02, page 894 of 986 Tpr CKIO Tpc tAD BANK Row tAD Precharge-sel H/L Address tCSD tCSD tRWD RD/ tRWD tRASD tRASD tCASD2 tCASD2 tDQMD DQMn tDQMD D63-D0 (write) tWDD tWDD tBSD CKE tDACD DACKn tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (TPC[2:0] = 001) Rev. 6.0, 07/02, page 895 of 986 TRr1 CKIO TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc tAD BANK tAD Precharge-sel Address tCSD tCSD tCSD tCSD tRWD RD/ tRWD tRASD tRASD tRASD tRASD tCASD2 tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD D63-D0 (write) tWDD tWDD tBSD CKE tDACD DACKn tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001) Rev. 6.0, 07/02, page 896 of 986 TRs1 CKIO TRs2 TRs3 TRs4 TRs5 Trc Trc Trc tAD BANK tAD Precharge-sel Address tCSD tCSD tCSD tCSD tRWD RD/ tRWD tRASD tRASD tRASD tRASD tCASD2 tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD tWDD D63-D0 (write) tWDD tBSD tCKED CKE tCKED tDACD tDACD DACKn Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001) Rev. 6.0, 07/02, page 897 of 986 TRp1 CKIO TRp2 TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 tAD BANK tAD tAD Precharge-sel Address tCSD tRWD RD/ tCSD tRWD tRASD tCSD tRWD tRASD tRASD tCASD2 tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD D63-D0 (write) tWDD tWDD tBSD CKE tDACD DACKn tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL) Rev. 6.0, 07/02, page 898 of 986 TRp1 CKIO TRp2 TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 tAD BANK tAD tAD Precharge-sel Address tCSD tRWD RD/ tCSD tRWD tRASD tCSD tRWD tRASD tRASD tCASD2 tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD D63-D0 (write) tWDD tWDD tBSD CKE tDACD DACKn tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET) Rev. 6.0, 07/02, page 899 of 986 Tr1 Tc1 Tc2 Tr2 Tpc Tr1 Tr2 Trw Tc1 Tcw Tc2 Tpc Tpc CKIO tAD tAD tAD tAD column tAD tAD tCSD tRWD tRASD tCASD1 tRASD column Row A25-A0 Row tCSD tRWD tRWD tRASD tRASD tRASD tRASD tRWD tCSD tCSD Rev. 6.0, 07/02, page 900 of 986 tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tRDS tWDD tWDD tWDD tWDD tWDD tWDD tRDH tRDS tRDH tBSD tBSD tBSD tBSD tDACD tDACD tDACD tDACD tDACD tDACD tDACD tDACD tDACD tDACD tDACD tDACD (1) (2) RD/ D63-D0 (read) D63-D0 (write) Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010 DACKn (SA: IO memory) DACKn (SA: IO memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high T1r CKIO Tr2 Tc1 Tc2 Tce Tpc tAD A25-A0 Row tAD Column tAD tCSD tCSD tRWD RD/ tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 D63-D0 (read) tRDS tRDH tWDD D63-D0 (write) tBSD tBSD DACKn (SA: IO memory) tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) Rev. 6.0, 07/02, page 901 of 986 T1r CKIO Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce Tpc tAD A25-A0 Row c0 c1 c2 c3 tAD tAD tAD tCSD tCSD tRWD RD/ Rev. 6.0, 07/02, page 902 of 986 tRWD tRASD tRASD tRASD tRWD tCASD1 tCASD1 tCASD1 tCASD1 D63-D0 (read) d0 tRDS tWDD tRDH d1 d2 tRDS d3 tRDH D63-D0 (write) Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) tBSD tBSD tBSD tBSD DACKn (SA: IO memory) tDACD tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tc1 Tr2 Trw Tc1 Tcw Tc2 Tc1 Tcw Tc2 Tc1 Tcw Tc2 Tcw Tc2 Tce Tpc CKIO tAD Row c0 c1 c2 c3 tAD tAD tCSD tRWD tRASD tCASD1 tCASD1 A25-A0 tCSD tRWD tRASD tRASD RD/ tCASD1 tCASD1 tCASD1 tCASD1 D63-D0 (read) d0 d1 tRDS tWDD tRDH d2 tRDS d3 tRDH D63-D0 (write) tBSD tBSD tDACD tDACD Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) tDACD DACKn (SA: IO memory) Rev. 6.0, 07/02, page 903 of 986 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tr2 Trw Tc1 Tcw Tc2 Tcnw Tc1 Tcw Tcw Tc2 Tcnw Tce Tc2 Tcnw Tc1 Tc2 Tcnw Tc1 Tcw Tpc CKIO tAD tAD Row c0 c1 c2 c3 tAD tCSD tRWD A25-A0 Rev. 6.0, 07/02, page 904 of 986 tCSD tRWD tRASD tRASD tCASD1 tRDS d0 d1 RD/ tRASD tCASD1 tRDH tCASD1 tRDS d2 d3 tCASD1 tCASD1 tRDH D63-D0 (read) D63-D0 (write) tWDD tBSD tDACD t DACD tDACD tBSD DACKn (SA: IO memory) Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tpc Tr2 Tc1 Tc2 Tc1 Tc2 Tr1 Tc1 Tc2 Tc1 Tc2 Tce CKIO tAD Row c0 c1 c2 c3 tAD tAD tAD tCSD A25-A0 tCSD tRWD tRWD RD/ tRASD tRASD tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 D63-D0 (read) d0 tRDS tWDD tBSD tRDH d1 d2 tRDS d3 tRDH D63-D0 (write) tBSD tBSD tBSD Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) tDACD tDACD tDACD DACKn (SA: IO memory) Rev. 6.0, 07/02, page 905 of 986 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 CKIO Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce tAD A25-A0 c0 c1 c2 c3 tAD tCSD tAD tCSD Rev. 6.0, 07/02, page 906 of 986 tRWD RD/ RAS-down mode ended tRWD tRASD tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 D63-D0 (read) d0 tRDS d1 tRDH d2 tRDS d3 tRDH tWDD D63-D0 (write) tBSD tBSD tBSD tBSD tDACD DACKn (SA: IO memory) Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 CKIO Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tpc tAD A25-A0 Row c0 c1 c2 c3 tAD tAD tCSD tCSD tRWD RD/ tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 D63-D0 (read) d0 d1 tRDS tWDD tWDD tWDD d0 d1 tRDH d2 tRDS d3 tRDH tWDD d2 d3 D63-D0 (write) tBSD tBSD tDACD DACKn (SA: IO memory) tDACD tDACD Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) tDACD DACKn (SA: IO memory) tDACD tDACD Rev. 6.0, 07/02, page 907 of 986 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tr2 Trw Tc1 Tcw Tc2 Tc1 Tcw Tc2 Tc2 Tc1 Tcw Tc1 Tcw Tpc Tc2 CKIO tAD tAD Row c0 c1 c2 c3 tAD tCSD tRWD A25-A0 tCSD tRWD tRASD tRASD tCASD1 tCASD1 tRDH d0 d1 d2 Rev. 6.0, 07/02, page 908 of 986 tRASD tCASD1 tRDS d3 RD/ tCASD1 tRDS tWDD tWDD d0 d1 tCASD1 tRDH tWDD D63-D0 (read) tWDD d2 d3 D63-D0 (write) tBSD tBSD tDACD tDACD tDACD tDACD tDACD tDACD DACKn (SA: IO memory) Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) DACKn (SA: IO memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tr2 Trw Tc1 Tcw Tc2 Tcnw Tc1 Tc1 Tcw Tc2 Tcw Tc2 Tcnw Tcw Tcnw Tc2 Tcnw Tc1 Tpc CKIO tAD Row c0 c1 c2 c3 tAD tAD tCSD tRWD A25-A0 tCSD tRWD tRASD tRASD tCASD1 tRDS tWDD tWDD tWDD d0 d1 d2 d3 d0 d1 RD/ tRASD tCASD1 tRDH d2 tCASD1 tCASD1 tRDS tCASD1 tRDH d3 D63-D0 (read) D63-D0 (write) tWDD tBSD tBSD tDACD tDACD tDACD tDACD tDACD tDACD DACKn (SA: IO memory) DACKn (SA: IO memory) Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) Rev. 6.0, 07/02, page 909 of 986 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tpc CKIO Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 tAD tAD Row c0 c1 c2 c3 tAD tAD tCSD tRWD A25-A0 tCSD tRWD RD/ tCSD tRWD tRASD tCASD1 tCASD1 tCASD1 Rev. 6.0, 07/02, page 910 of 986 tRASD tCASD1 tCASD1 D63-D0 (read) tRDS tWDD tWDD d0 d0 tRDH d1 d2 tRDS d3 tRDH tWDD d1 d2 d3 tWDD D63-D0 (write) tBSD tBSD tDACD DACKn (SA: IO memory) tDACD tDACD tDACD tDACD tDACD DACKn (SA: IO memory) Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tnop CKIO Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 tAD A25-A0 c0 c1 c2 c3 tAD tCSD tRWD tCSD tRWD tRASD RAS down mode ended tCSD tRWD RD/ tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tRDS tWDD tWDD d0 d0 tRDH d1 d2 tRDS d3 D63-D0 (read) tRDH tWDD d1 d2 d3 D63-D0 (write) tWDD tBSD tBSD tDACD DACKn (SA: IO memory) tDACD tDACD tDACD tDACD tDACD DACKn (SA: IO memory) Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Rev. 6.0, 07/02, page 911 of 986 TRr1 CKIO TRr2 TRr3 TRr4 TRr5 Trc Trc Trc tAD A25-A0 tCSD tRWD RD/ tRASD tCASD1 tRASD tRASD tCASD1 tCASD1 tWDD D63-D0 (write) DACKn (SA: IO memory) tDACD tDACD DACKn (SA: IO memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000, TRC[2:0] = 001) Rev. 6.0, 07/02, page 912 of 986 TRr1 CKIO TRr2 TRr3 TRr4 TRr4w TRr5 Trc Trc Trc tAD A25-A0 tCSD tRWD RD/ tRASD tCASD1 tRASD tRASD tCASD1 tCASD1 tWDD D63-D0 (write) DACKn (SA: IO memory) tDACD tDACD DACKn (SA: IO memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001) Rev. 6.0, 07/02, page 913 of 986 TRr1 CKIO TRr2 TRr3 TRr4 TRr5 Trc Trc Trc tAD A25-A0 tCSD tRWD RD/ tRASD tCASD1 tRASD tRASD tCASD1 tCASD1 tWDD D63-D0 (write) DACKn (SA: IO memory) tDACD tDACD DACKn (SA: IO memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) Rev. 6.0, 07/02, page 914 of 986 Tpcm1 Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO Tpcm2 tAD A25-A0 tAD tCSD tRWD tRWD tCSD tAD tAD tCSD tRWD tCSD ( ) tRWD RD/ tRSD tRSD tRSD tRDS tWED1 tWEDF tWDD tWDD tBSD tWDD tBSD tRDYS tDACD DACKn (DA) TED tRSD tRDH tWEDF tWDD tWED1 tRSD * tRDS tRDH tWEDF tRSD D15-D0 (read) tWEDF D15-D0 (write) tWDD tBSD tBSD tWDD tRDYH tDACD tRDYS tRDYH tDACD tDACD TEH Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait (1) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high *: SH7750S only Rev. 6.0, 07/02, page 915 of 986 (2) Tpci1 Tpci0 Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO Tpci2 tAD A25-A0 tAD tCSD tRWD tRWD tCSD tAD tAD tCSD tRWD tCSD ( ) tRWD RD/ Rev. 6.0, 07/02, page 916 of 986 tICRSD tICRSD tICRSD tICRSD tRDS tICWSDF tWDD tICWSDF tRDH ( D15-D0 (read) ) tICRSD tRDS tICWSDF tICWSDF ( ) tRDH tICWSDF tWDD tWDD tWDD tWDD tBSD D15-D0 (write) tBSD tBSD tBSD tRDYS tRDYH tRDYS tDACD tIO16S tRDYH tIO16H tDACD tIO16S tIO16H tDACD DACKn (DA) tDACD Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait (1) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high (2) Tpci0 Tpci2w Tpci2w CKIO Tpci1 Tpci1w Tpci2 Tpci0 Tpci1 Tpci1w Tpci2 tAD A25-A1 tAD tAD A0 tCSD ( ) tCSD tCSD tRWD tRWD RD/ tICRSD tICRSD tRDS tICWSDF tICWSDF ( ) tICRSD tRDH tICWSDF tWDD tWDD tICWSDF ( D15-D0 (read) ) tICWSDF D15-D0 (write) tWDD tBSD tRDYS tRDYH tBSD tWDD tWDD tRDYS tRDYH Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing) tIO16S tIO16H Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Rev. 6.0, 07/02, page 917 of 986 Tm1 Tm0 Tmd1w Tmd1w Tmd1 CKIO Tmd1w Tmd1 tFMD / tFMD tWDD tRDH A tFMD tRDS tWDD tWDD D0 tFMD tRDS D0 tWDD D63-D0 A tRDH tCSD tRWD RD/ tCSD tRWD tRWD tCSD tCSD tRWD Rev. 6.0, 07/02, page 918 of 986 tWED1 tRDYS tBSD tBSD tDACD tRDYH tBSD tWED1 tWED1 tRDYS tRDYH tRDYS tBSD tRDYH tWED1 tDACD DACKn (DA) tDACD tDACD Figure 22.55 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait) (1) 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high (2) 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address Tm1 CKIO Tmd1 Tm1 Tmd1w Tmd1 Tm1 Tmd1w Tmd1w Tmd1 tFMD / tFMD tWDD D0 A D0 A D0 tFMD tFMD tWDD tCSD tRWD tWED1 tRDYH tBSD tWED1 tRDYS tRDYH tRWD tCSD tWDD tWDD tFMD tWDD tCSD tRWD tWED1 tWED1 tRDYS tBSD tBSD tDACD tRWD tCSD tWDD tWDD tFMD tWDD D63-D0 A tWDD tCSD tRWD tWED1 tCSD tRWD RD/ tWED1 tRDYS tBSD tBSD tDACD tDACD tRDYH tRDYS tBSD tDACD tRDYH tDACD DACKn (DA) tDACD Figure 22.56 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) (1) 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high (2) 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address (3) Rev. 6.0, 07/02, page 919 of 986 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO tFMD tWDD tWDD tRDS D0 A D1 D2 D3 D0 D1 D2 tFMD tRDH tCSD tRWD tWED1 tRDYH tBSD tBSD tRDYS tRDYH tRDYS tRDYH tWED1 tRWD tCSD tWDD tWDD tRDS tRDH tFMD tFMD / D63-D0 A D3 tCSD tRWD tWED1 tRDYS tBSD tBSD tDACD tDACD tCSD tRWD tWED1 Rev. 6.0, 07/02, page 920 of 986 tDACD tDACD (1) 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address RD/ DACKn (DA) (2) 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address Figure 22.57 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait) (2) 1st Data (One Internal Wait), 2nd to 4th Data (One Internal Wait + One External Wait) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tm1 Tmd1 Tmd2 Tmd3 Tmd4 Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO tFMD tFMD tWDD tWDD D0 D1 D2 D3 D1 A D2 D3 tFMD tWDD D0 tFMD / tWDD A D63-D0 tCSD tRWD tRWD tWED1 tRDYH tBSD tDACD tDACD tBSD tBSD tRDYS tRDYH tRDYS tRDYH tWED1 tRWD tCSD tCSD tCSD tRWD tWED1 RD/ tWED1 tRDYS tBSD tDACD tDACD DACKn (DA) (1) 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address (2) 1st data bus cycle information D63-D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait Control) Rev. 6.0, 07/02, page 921 of 986 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high T1 CKIO T2 T1 Tw T2 T1 Tw Twe T2 tAD tAD tAD tAD tCSD tRWD tRSD tRDS tWED1 tWEDF tWED1 tWED1 tRDH tWEDF tRSD tRSD tRSD tRDS tRWD tCSD tAD tCSD tRWD tRSD tAD tCSD tRWD tRSD tRDS tWED1 tWEDF tBSD tBSD tBSD tRDYS tRDYH tDACD tDACD tDACD tDACD tDACD DACKn (SA: IO memory) A25-A0 tCSD tRWD RD/ tCSD tRWD tRSD tRDH tWED1 Rev. 6.0, 07/02, page 922 of 986 tRSD tRDH tWED1 tBSD tRSD D63-D0 (read) tBSD tBSD tRDYS tRDYH tRDYH tDACD tDACD tRDYS tDACD tDACD tDACD DACKn (DA) Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait) tDACD tDACD tDACD tDACD (1) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high (2) (3) tDACD TS1 CKIO T1 T2 TH1 tAD A25-A0 tAD tCSD tCSD tRWD RD/ tRWD tRSD tRDS tRDH tWED1 tRSD tRSD D63-D0 (read) tWED1 tWEDF tBSD tBSD tDACD DACKn (SA: IO memory) tDACD tDACD DACKn (DA) tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1) Rev. 6.0, 07/02, page 923 of 986 22.3.4 Peripheral Module Signal Timing Table 22.36 Peripheral Module Signal Timing (1) HD6417750 RBP240 *2 Module TMU, RTC Item Timer clock pulse width (high) Timer clock pulse width (low) Timer clock rise time Timer clock fall time Oscillation settling time SCI Input clock cycle (asynchronous) Input clock cycle (synchronous) Input clock pulse width Input clock rise time Input clock fall time Transfer data delay time Symbol tTCLKWH Min 4 Max -- Min 4 HD6417750 RBP200 *2 Max -- Min 4 HD6417750 RF240 *2 Max -- Min 4 HD6417750 RF200 *2 Max -- Unit Pcyc* 1 Figure 22.61 tTCLKWL 4 -- 4 -- 4 -- 4 -- Pcyc* 1 22.61 tTCLKr tTCLKf tROSC tScyc -- -- -- 4 0.8 0.8 3 -- -- -- -- 4 0.8 0.8 3 -- -- -- -- 4 0.8 0.8 3 -- -- -- -- 4 0.8 0.8 3 -- 1 Pcyc* 22.61 22.61 22.62 1 Pcyc* s Pcyc* 1 22.63 tScyc 6 -- 6 -- 6 -- 6 -- Pcyc* 1 22.63 tSCKW tSCKr tSCKf tTXD 0.4 -- -- 1.5 16 0.6 0.8 0.8 5.3 -- 0.4 -- -- 1.5 16 0.6 0.8 0.8 6 -- 0.4 -- -- 1.5 16 0.6 0.8 0.8 6 -- 0.4 -- -- 1.5 16 0.6 0.8 0.8 6 -- tScyc 1 Pcyc* 22.63 22.63 22.63 22.64 22.64 1 Pcyc* ns ns Receive data tRXS setup time (synchronous) Receive data tRXH hold time (synchronous) 16 -- 16 -- 16 -- 16 -- ns 22.64 Rev. 6.0, 07/02, page 924 of 986 HD6417750 RBP240 *2 Module I/O ports Item Output data delay time Input data setup time Input data hold time DMAC '5(4Q setup time '5(4Q hold time DRAKn delay time INTC NMI pulse width (high) Symbol tPORTD tPORTS tPORTH tDRQS tDRQH tDRAKD tNMIH Min 1.5 2 1.5 2 1.5 1.5 5 Max 5.3 -- -- -- -- 5.3 -- HD6417750 RBP200 *2 Min 1.5 2.5 1.5 2.5 1.5 1.5 5 Max 6 -- -- -- -- 6 -- HD6417750 RF240 *2 Min 1.5 3.5 1.5 3.5 1.5 1.5 5 Max 6 -- -- -- -- 6 -- HD6417750 RF200 *2 Min 1.5 3.5 1.5 3.5 1.5 1.5 5 Max 6 -- -- -- -- 6 -- Unit ns ns ns ns ns ns tcyc Figure 22.65 22.65 22.65 22.66 22.66 22.66 22.71 Normal or sleep mode Standby mode Normal or sleep mode Standby mode 30 NMI pulse width (low) tNMIL 5 -- -- 30 5 -- -- 30 5 -- -- 30 5 -- -- ns tcyc 22.71 22.71 30 H-UDI Input clock cycle Input clock pulse width (high) Input clock pulse width (low) Input clock rise time Input clock fall time $6(%5. setup time $6(%5. hold time TDI/TMS setup time TDI/TMS hold time TDO delay time ASE-PINBRK pulse width tTCKcyc tTCKH 50 15 -- -- -- 30 50 15 -- -- -- 30 50 15 -- -- -- 30 50 15 -- -- -- ns ns ns 22.71 22.67 22.67 tTCKL 15 -- 15 -- 15 -- 15 -- ns 22.67 tTCKr tTCKf tASEBRKS tASEBRKH tTDIS tTDIH tTDO tPINBRK -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- ns ns tcyc tcyc ns ns ns Pcyc* 1 22.67 22.67 22.68 22.68 22.69 22.69 22.69 22.70 Notes: *1 Pcyc: P clock cycles *2 VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on Rev. 6.0, 07/02, page 925 of 986 Table 22.36 Peripheral Module Signal Timing (2) HD6417750 SF167 HD6417750 SVF133 HD6417750 SVBT133 *2 Module TMU, RTC Item Timer clock pulse width (high) Timer clock pulse width (low) Timer clock rise time Timer clock fall time Oscillation settling time SCI Input clock cycle (asynchronous) Input clock cycle (synchronous) Input clock pulse width Input clock rise time Input clock fall time Transfer data delay time Symbol tTCLKWH Min 4 Max -- Min 4 HD6417750 SF167I HD6417750 SF200 *3 Max -- Min 4 HD6417750 SBP200 *4 Max -- Unit 1 Pcyc* Figure 22.61 tTCLKWL 4 -- 4 -- 4 -- Pcyc* 1 22.61 tTCLKr tTCLKf tROSC tScyc -- -- -- 4 0.8 0.8 3 -- -- -- -- 4 0.8 0.8 3 -- -- -- -- 4 0.8 0.8 3 -- 1 Pcyc* 22.61 22.61 22.62 1 Pcyc* s Pcyc* 1 22.63 tScyc 6 -- 6 -- 6 -- Pcyc* 1 22.63 tSCKW tSCKr tSCKf tTXD 0.4 -- -- 1.5 16 0.6 0.8 0.8 10 -- 0.4 -- -- 1.5 16 0.6 0.8 0.8 8 -- 0.4 -- -- 1.5 16 0.6 0.8 0.8 6 -- tScyc 1 Pcyc* 22.63 22.63 22.63 22.64 22.64 1 Pcyc* ns ns Receive data tRXS setup time (synchronous) Receive data tRXH hold time (synchronous) I/O ports Output data delay time Input data setup time Input data hold time tPORTD tPORTS tPORTH 16 -- 16 -- 16 -- ns 22.64 1.5 3.5 1.5 10 -- -- 1.5 3.5 1.5 8 -- -- 1.5 3 1.5 6 -- -- ns ns ns 22.65 22.65 22.65 Rev. 6.0, 07/02, page 926 of 986 HD6417750 SF167 HD6417750 SVF133 HD6417750 SVBT133 *2 Module DMAC Item '5(4Q setup time '5(4Q hold time DRAKn delay time INTC NMI pulse width (high) NMI pulse width (low) H-UDI Input clock cycle Input clock pulse width (high) Input clock pulse width (low) Input clock rise time Input clock fall time $6(%5. setup time $6(%5. hold time TDI/TMS setup time TDI/TMS hold time TDO delay time ASE-PINBRK pulse width Symbol tDRQS tDRQH tDRAKD tNMIH Min 3.5 1.5 1.5 5 30 tNMIL 5 30 tTCKcyc tTCKH 50 15 Max -- -- 10 -- -- -- -- -- -- Min 3.5 1.5 1.5 5 30 5 30 50 15 HD6417750 SF167I HD6417750 SF200 *3 Max -- -- 8 -- -- -- -- -- -- Min 3 1.5 1.5 5 30 5 30 50 15 HD6417750 SBP200 *4 Max -- -- 6 -- -- -- -- -- -- Unit ns ns ns tcyc ns tcyc ns ns ns Figure 22.66 22.66 22.66 22.71 22.71 22.71 22.71 22.67 22.67 Normal or sleep mode Standby mode Normal or sleep mode Standby mode tTCKL 15 -- 15 -- 15 -- ns 22.67 tTCKr tTCKf tASEBRKS tASEBRKH tTDIS tTDIH tTDO tPINBRK -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- ns ns tcyc tcyc ns ns ns Pcyc* 1 22.67 22.67 22.68 22.68 22.69 22.69 22.69 22.70 Notes: *1 Pcyc: P clock cycles *2 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on *3 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on (HD6417750SF167, HD6417750SF200) VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -40 to +85C, CL = 30 pF, PLL2 on (HD6417750SF167I) *4 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on Rev. 6.0, 07/02, page 927 of 986 Table 22.36 Peripheral Module Signal Timing (3) HD6417750 F167 HD6417750 VF128 *2 Module TMU, RTC Item Timer clock pulse width (high) Timer clock pulse width (low) Timer clock rise time Timer clock fall time Oscillation settling time SCI Input clock cycle (asynchronous) Input clock cycle (synchronous) Input clock pulse width Input clock rise time Input clock fall time Transfer data delay time Symbol tTCLKWH Min 4 Max -- Min 4 HD6417750 F167I *3 Max -- Min 4 HD6417750 BP200M *4 Max -- Unit Pcyc* 1 Figure 22.61 tTCLKWL 4 -- 4 -- 4 -- Pcyc* 1 22.61 tTCLKr tTCLKf tROSC tScyc -- -- -- 4 0.8 0.8 3 -- -- -- -- 4 0.8 0.8 3 -- -- -- -- 4 0.8 0.8 3 -- 1 Pcyc* 22.61 22.61 22.62 1 Pcyc* s Pcyc* 1 22.63 tScyc 6 -- 6 -- 6 -- Pcyc* 1 22.63 tSCKW tSCKr tSCKf tTXD 0.4 -- -- 1.3 16 0.6 0.8 0.8 10 -- 0.4 -- -- 1.3 16 0.6 0.8 0.8 8 -- 0.4 -- -- 1.2 16 0.6 0.8 0.8 6 -- tScyc 1 Pcyc* 22.63 22.63 22.63 22.64 22.64 1 Pcyc* ns ns Receive data tRXS setup time (synchronous) Receive data tRXH hold time (synchronous) I/O ports Output data delay time Input data setup time Input data hold time tPORTD tPORTS tPORTH 16 -- 16 -- 16 -- ns 22.64 0.5 3.5 1.5 10 -- -- 0.5 3.5 1.5 8 -- -- 0.5 3 1.5 6 -- -- ns ns ns 22.65 22.65 22.65 Rev. 6.0, 07/02, page 928 of 986 HD6417750 F167 HD6417750 VF128 *2 Module DMAC Item '5(4Q setup time '5(4Q hold time DRAKn delay time INTC NMI pulse width (high) NMI pulse width (low) H-UDI Input clock cycle Input clock pulse width (high) Input clock pulse width (low) Input clock rise time Input clock fall time $6(%5. setup time $6(%5. hold time TDI/TMS setup time TDI/TMS hold time TDO delay time ASE-PINBRK pulse width Symbol tDRQS tDRQH tDRAKD tNMIH Min 3.5 1.5 1.0 5 30 tNMIL 5 30 tTCKcyc tTCKH 50 15 Max -- -- 10 -- -- -- -- -- -- Min 3.5 1.5 1.0 5 30 5 30 50 15 HD6417750 F167I *3 Max -- -- 8 -- -- -- -- -- -- Min 3 1.5 1.0 5 30 5 30 50 15 HD6417750 BP200M *4 Max -- -- 6 -- -- -- -- -- -- Unit ns ns ns tcyc ns tcyc ns ns ns Figure 22.66 22.66 22.66 22.71 22.71 22.71 22.71 22.67 22.67 Normal or sleep mode Standby mode Normal or sleep mode Standby mode tTCKL 15 -- 15 -- 15 -- ns 22.67 tTCKr tTCKf tASEBRKS tASEBRKH tTDIS tTDIH tTDO tPINBRK -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- -- -- 10 10 15 15 0 2 10 10 -- -- -- -- 10 -- ns ns tcyc tcyc ns ns ns Pcyc* 1 22.67 22.67 22.68 22.68 22.69 22.69 22.69 22.70 Notes: *1 Pcyc: P clock cycles *2 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on *3 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on (HD6417750F167) VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -40 to +85C, CL = 30 pF, PLL2 on (HD6417750F167I) *4 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = -20 to +75C, CL = 30 pF, PLL2 on Rev. 6.0, 07/02, page 929 of 986 TCLK tTCLKWH tTCLKWL tTCLKf tTCLKr Figure 22.61 TCLK Input Timing Stable oscillation RTC internal clock VDD-RTC VDD-RTC min tROSC Figure 22.62 RTC Oscillation Settling Time at Power-On tSCKW SCK, SCK2 tScyc tSCKf tSCKr Figure 22.63 SCK Input Clock Timing Rev. 6.0, 07/02, page 930 of 986 tScyc SCK tTXD TXD tTXD RXD tRXS tRXH Figure 22.64 SCI I/O Synchronous Mode Clock Timing CKIO Ports 19-0 (read) tPORTS tPORTH Ports 19-0 (write) tPORTD tPORTD Figure 22.65 I/O Port Input/Output Timing CKIO tDRQH tDRQS DRAKn tDRQH tDRQS tDRAKD Figure 22.66(a) '5(4 '5(4/DRAK Timing Rev. 6.0, 07/02, page 931 of 986 CKIO tDBQS DBREQ tDBQH tBAVD tBAVD BAVL tTRS TR tTRH D63 to D0 (READ) tDTRS (2) tDTRH (1) (1): [2CKIO cycle - tDTRS] (= 18 ns: 100 MHz) (2): DTR = 1CKIO cycle (= 10 ns: 100 MHz) (tDTRS + tDTRH) < DTR < 10 ns Figure 22.66(b) '%5(4 75 Input Timing and %$9/ Output Timing '%5(4/75 tTCKcyc tTCKH tTCKL VIH 1/2VDDQ VIH VIL tTCKf VIL VIH 1/2VDDQ tTCKr Note: When clock is input from TCK pin Figure 22.67 TCK Input Timing (Low) SCK2/ (High) tASEBRKS tASEBRKH tASEBRKS tASEBRKH / BRKACK Figure 22.68 5(6(7 Hold Timing Rev. 6.0, 07/02, page 932 of 986 TCK tTCKcyc TDI TMS tTDIS tTDIH TDO tTDO Figure 22.69 H-UDI Data Transfer Timing tPINBRK Figure 22.70 Pin Break Timing tNMIH tNMIL NMI Figure 22.71 NMI Input Timing Rev. 6.0, 07/02, page 933 of 986 22.3.5 AC Characteristic Test Conditions The AC characteristic test conditions are as follows: * Input/output signal reference level: 1.5 V (VDDQ = 3.3 0.3 V) * Input pulse level: VSSQ-3.0 V (VSSQ-VDDQ for 5(6(7, 7567, NMI, and $6(%5./BRKACK) * Input rise/fall time: 1 ns The output load circuit is shown in figure 22.72. IOL LSI output pin CL DUT output VREF IOH Notes: 1. CL is the total value, including the capacitance of the test jig, etc. The capacitance of each pin is set to 30 pF. 2. IOL and IOH values are as shown in table 22.16, Permissible Output Currents. Figure 22.72 Output Load Circuit Rev. 6.0, 07/02, page 934 of 986 22.3.6 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF) is connected to the SH7750 Series' pins is shown below. The graph shown in figure 22.73 should be taken into consideration if the stipulated capacitance is exceeded when connecting an external device. The graph will not be linear if the connected load capacitance exceeds the range shown in figure 22.73. +4.0 ns +3.0 ns Delay Time +2.0 ns +1.0 ns +0.0 ns +0 pF +25 pF Load Capacitance +50 pF Figure 22.73 Load Capacitance vs. Delay Time Rev. 6.0, 07/02, page 935 of 986 Rev. 6.0, 07/02, page 936 of 986 Appendix A Address List Table A.1 Address List Area 7 1 P4 Address Address* Power-On Size Reset Undefined Undefined Undefined Undefined Manual Reset Undefined Undefined Undefined Held Synchronization Sleep Standby Clock Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk Module Register CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN PTEH PTEL TTB TEA MMUCR BASRA BASRB CCR TRA EXPEVT INTEVT PTEA QACR0 QACR1 H'FF00 0000 H'1F00 0000 32 H'FF00 0004 H'1F00 0004 32 H'FF00 0008 H'1F00 0008 32 H'FF00 000C H'1F00 000C 32 H'FF00 0010 H'1F00 0010 32 H'FF00 0014 H'1F00 0014 8 H'FF00 0018 H'1F00 0018 8 H'FF00 001C H'1F00 001C 32 H'FF00 0020 H'1F00 0020 32 H'FF00 0024 H'1F00 0024 32 H'FF00 0028 H'1F00 0028 32 H'FF00 0034 H'1F00 0034 32 H'FF00 0038 H'1F00 0038 32 H'FF00 003C H'1F00 003C 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Held Held Held Held H'0000 0000 H'0000 0000 Held Undefined Undefined Held H'0000 0000 H'0000 0020 Held Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held Held UBC UBC UBC UBC UBC UBC UBC UBC UBC BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR H'FF20 0000 H'1F20 0000 32 H'FF20 0004 H'1F20 0004 8 H'FF20 0008 H'1F20 0008 16 H'FF20 000C H'1F20 000C 32 H'FF20 0010 H'1F20 0010 8 H'FF20 0014 H'1F20 0014 16 H'FF20 0018 H'1F20 0018 32 H'FF20 001C H'1F20 001C 32 H'FF20 0020 H'1F20 0020 16 Undefined Undefined H'0000 Undefined Undefined H'0000 Undefined Undefined 2 H'0000* Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk Iclk BSC BSC BSC BSC BSC BSC BCR1 BCR2 5 BCR3* 5 BCR4* H'FF80 0000 H'1F80 0000 32 H'FF80 0004 H'1F80 0004 16 H'FF80 0050 H'1F80 0050 16 H'FE0A00F0 H'1E0A00F0 32 H'FF80 0008 H'1F80 0008 32 H'FF80 000C H'1F80 000C 32 H'0000 0000* Held 2 H'3FFC* 2 Held Held Held Held Held Held Held Held Held Held Held Held Bclk Bclk Bclk Bclk Bclk Bclk Held Held H'0000 H'0000 0000 Held H'7777 7777 Held H'FFFE EFFF Held WCR1 WCR2 Rev. 6.0, 07/02, page 937 of 986 Table A.1 Address List (cont) Area 7 1 P4 Address Address* Power-On Size Reset Manual Reset Synchronization Sleep Standby Clock Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Module Register BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC WCR3 MCR PCR RTCSR RTCNT RTCOR RFCR PCTRA PDTRA PCTRB PDTRB GPIOIC SDMR2 SDMR3 H'FF80 0010 H'1F80 0010 32 H'FF80 0014 H'1F80 0014 32 H'FF80 0018 H'1F80 0018 16 H'FF80 001C H'1F80 001C 16 H'FF80 0020 H'1F80 0020 16 H'FF80 0024 H'1F80 0024 16 H'FF80 0028 H'1F80 0028 16 H'FF80 002C H'1F80 002C 32 H'FF80 0030 H'1F80 0030 16 H'FF80 0040 H'1F80 0040 32 H'FF80 0044 H'1F80 0044 16 H'FF80 0048 H'1F80 0048 16 H'FF90 xxxx H'1F90 xxxx H'FF94 xxxx H'1F94 xxxx 8 8 H'0777 7777 Held H'0000 0000 Held H'0000 H'0000 H'0000 H'0000 H'0000 Held Held Held Held Held H'0000 0000 Held Undefined Held H'0000 0000 Held Undefined Held H'0000 0000 Held Write-only DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC SAR0 DAR0 H'FFA0 0000 H'1FA0 0000 32 H'FFA0 0004 H'1FA0 0004 32 Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk DMATCR0 H'FFA0 0008 H'1FA0 0008 32 CHCR0 SAR1 DAR1 H'FFA0 000C H'1FA0 000C 32 H'FFA0 0010 H'1FA0 0010 32 H'FFA0 0014 H'1FA0 0014 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DMATCR1 H'FFA0 0018 H'1FA0 0018 32 CHCR1 SAR2 DAR2 H'FFA0 001C H'1FA0 001C 32 H'FFA0 0020 H'1FA0 0020 32 H'FFA0 0024 H'1FA0 0024 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DMATCR2 H'FFA0 0028 H'1FA0 0028 32 CHCR2 SAR3 DAR3 H'FFA0 002C H'1FA0 002C 32 H'FFA0 0030 H'1FA0 0030 32 H'FFA0 0034 H'1FA0 0034 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DMATCR3 H'FFA0 0038 H'1FA0 0038 32 CHCR3 DMAOR H'FFA0 003C H'1FA0 003C 32 H'FFA0 0040 H'1FA0 0040 32 H'0000 0000 H'0000 0000 Held H'0000 0000 H'0000 0000 Held Rev. 6.0, 07/02, page 938 of 986 Table A.1 Address List (cont) Area 7 1 P4 Address Address* Power-On Size Reset Undefined Undefined Undefined Manual Reset Undefined Undefined Undefined Synchronization Sleep Standby Clock Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Bclk Module Register DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC 5 SAR4* H'FFA0 0050 H'1FA0 0050 32 H'FFA0 0054 H'1FA0 0054 32 DAR4* 5 5 DMATCR4* H'FFA0 0058 H'1FA0 0058 32 5 CHCR4* 5 SAR5* 5 DAR5* 5 H'FFA0 005C H'1FA0 005C 32 H'FFA0 0060 H'1FA0 0060 32 H'FFA0 0064 H'1FA0 0064 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DMATCR5* H'FFA0 0068 H'1FA0 0068 32 CHCR5* 5 SAR6* 5 DAR6* 5 H'FFA0 006C H'1FA0 006C 32 H'FFA0 0070 H'1FA0 0070 32 H'FFA0 0074 H'1FA0 0074 32 5 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DMATCR6* H'FFA0 0078 H'1FA0 0078 32 CHCR6* 5 SAR7* 5 H'FFA0 007C H'1FA0 007C 32 H'FFA0 0080 H'1FA0 0080 32 H'FFA0 0084 H'1FA0 0084 32 5 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DAR7* 5 DMATCR7* H'FFA0 0088 H'1FA0 0088 32 5 CHCR7* H'FFA0 008C H'1FA0 008C 32 H'0000 0000 H'0000 0000 Held CPG 6 CPG* 6 CPG* FRQCR STBCR WTCNT WTCSR STBCR2 H'FFC0 0000 H'1FC0 0000 16 H'FFC0 0004 H'1FC0 0004 8 3 *2 H'00 Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pclk Pclk Pclk Pclk Pclk H'FFC0 0008 H'1FC0 0008 8/16* H'00 H'FFC0 000C H'1FC0 000C 8/16* H'00 H'FFC0 0010 H'1FC0 0010 8 H'00 3 CPG* 6 6 CPG* RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC R64CNT H'FFC8 0000 H'1FC8 0000 8 Held Held Held Held Held Held Held Held 2 Held * Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk RSECCNT H'FFC8 0004 H'1FC8 0004 8 RMINCNT H'FFC8 0008 H'1FC8 0008 8 RHRCNT H'FFC8 000C H'1FC8 000C 8 RWKCNT H'FFC8 0010 H'1FC8 0010 8 RDAYCNT H'FFC8 0014 H'1FC8 0014 8 RMONCNT H'FFC8 0018 H'1FC8 0018 8 RYRCNT RSECAR RMINAR H'FFC8 001C H'1FC8 001C 16 H'FFC8 0020 H'1FC8 0020 8 H'FFC8 0024 H'1FC8 0024 8 Held * 2 Rev. 6.0, 07/02, page 939 of 986 Table A.1 Address List (cont) Area 7 1 P4 Address Address* Power-On Size Reset 2 Held * Module Register RTC RTC RTC RTC RTC RTC RTC RTC RHRAR RWKAR RDAYAR Manual Reset Held Held Held Held H'00* 2 Synchronization Sleep Standby Clock Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk H'FFC8 0028 H'1FC8 0028 8 H'FFC8 002C H'1FC8 002C 8 H'FFC8 0030 H'1FC8 0030 8 Held * 2 2 Held * RMONAR H'FFC8 0034 H'1FC8 0034 8 RCR1 RCR2 5 RCR3* Held * H'00* 2 2 H'FFC8 0038 H'1FC8 0038 8 H'FFC8 003C H'1FC8 003C 8 H'FFC8 0050 H'1FC8 0050 8 2 H'09* 2 H'00* H'00 Undefined Held Held 5 RYRAR* H'FFC8 0054 H'1FC8 0054 16 INTC INTC INTC INTC INTC INTC INTC INTC INTC ICR IPRA IPRB IPRC 4 IPRD* H'FFD0 0000 H'1FD0 0000 16 H'FFD0 0004 H'1FD0 0004 16 H'FFD0 0008 H'1FD0 0008 16 H'FFD0 000C H'1FD0 000C 16 H'FFD00010 H'1F000010 16 H'0000* H'0000 H'0000 H'0000 H'DA74 2 2 H'0000* Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk H'0000 H'0000 H'0000 H'DA74 INTPRI00 H'FE08 0000 H'1E08 0000 32 *5 INTREQ00 H'FE08 0020 H'1E08 0020 32 *5 INTMSK00 H'FE08 0040 H'1E08 0040 32 *5 INTMSKCL H'FE08 0060 H'1E08 0060 32 5 R00* H'0000 0000 Held H'0000 0000 Held H'0000 0300 Held Write-only 6 CPG* CLKSTP00 H'FE0A 0000 H'1E0A 0000 32 *5 CLKSTPC H'FE0A 0008 H'1E0A 0008 32 5 LR00* H'0000 0000 Held Write-only Held Held Pclk Pclk 6 CPG* TMU TMU TMU TMU TMU TMU TMU 5 TSTR2* H'FE10 0004 H'1E10 0004 8 H'FE10 0008 H'1E10 0008 32 H'FE10 000C H'1E10 000C 32 H'FE10 0010 H'1E10 0010 16 H'00 Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pclk Pclk Pclk Pclk Pclk Pclk Pclk TCOR3* 5 H'FFFF FFFF Held H'FFFF FFFF Held H'0000 Held 5 TCNT3* 5 TCR3* TCOR4* TCNT4* 5 TCR4* 5 H'FE10 0014 H'1E10 0014 32 H'FE10 0018 H'1E10 0018 32 H'FE10 001C H'1E10 001C 16 H'FFFF FFFF Held H'FFFF FFFF Held H'0000 Held 5 Rev. 6.0, 07/02, page 940 of 986 Table A.1 Address List (cont) Area 7 1 P4 Address Address* Power-On Size Reset H'00 H'00 Manual Reset H'00 H'00 Synchronization Sleep Standby Clock Held Held Held H'00* Held Held Held Held Held Held Held Held Held Held 2 Module Register TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TOCR TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 H'FFD8 0000 H'1FD8 0000 8 H'FFD8 0004 H'1FD8 0004 8 H'FFD8 0008 H'1FD8 0008 32 H'FFD8 000C H'1FD8 000C 32 H'FFD8 0010 H'1FD8 0010 16 H'FFD8 0014 H'1FD8 0014 32 H'FFD8 0018 H'1FD8 0018 32 H'FFD8 001C H'1FD8 001C 16 H'FFD8 0020 H'1FD8 0020 32 H'FFD8 0024 H'1FD8 0024 32 H'FFD8 0028 H'1FD8 0028 16 H'FFD8 002C H'1FD8 002C 32 Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk H'FFFF FFFF H'FFFF FFFF Held H'FFFF FFFF H'FFFF FFFF Held H'0000 H'0000 Held H'FFFF FFFF H'FFFF FFFF Held H'FFFF FFFF H'FFFF FFFF Held H'0000 H'0000 Held H'FFFF FFFF H'FFFF FFFF Held H'FFFF FFFF H'FFFF FFFF Held H'0000 Held H'0000 Held Held Held SCI SCI SCI SCI SCI SCI SCI SCI SCSMR1 SCBRR1 SCSCR1 SCTDR1 SCSSR1 SCRDR1 H'FFE0 0000 H'1FE0 0000 8 H'FFE0 0004 H'1FE0 0004 8 H'FFE0 0008 H'1FE0 0008 8 H'FFE0 000C H'1FE0 000C 8 H'FFE0 0010 H'1FE0 0010 8 H'FFE0 0014 H'1FE0 0014 8 H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'00* 2 H'00 H'FF H'00 H'FF H'84 H'00 H'00 2 H'00* Held Held Held Held Held Held Held Held H'00 H'FF H'00 H'FF H'84 H'00 H'00 2 H'00* Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk SCSCMR1 H'FFE0 0018 H'1FE0 0018 8 SCSPTR1 H'FFE0 001C H'1FE0 001C 8 SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCSMR2 SCBRR2 SCSCR2 H'FFE8 0000 H'1FE8 0000 16 H'FFE8 0004 H'1FE8 0004 8 H'FFE8 0008 H'1FE8 0008 16 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000* H'0000 2 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000* H'0000 2 Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk Pclk SCFTDR2 H'FFE8 000C H'1FE8 000C 8 SCFSR2 H'FFE8 0010 H'1FE8 0010 16 SCFRDR2 H'FFE8 0014 H'1FE8 0014 8 SCFCR2 SCFDR2 H'FFE8 0018 H'1FE8 0018 16 H'FFE8 001C H'1FE8 001C 16 SCSPTR2 H'FFE8 0020 H'1FE8 0020 16 SCLSR2 H'FFE8 0024 H'1FE8 0024 16 Rev. 6.0, 07/02, page 941 of 986 Table A.1 Address List (cont) Area 7 1 P4 Address Address* Power-On Size Reset H'FFFF* 2 Module Register H-UDI H-UDI H-UDI SDIR SDDR 5 SDINT* Manual Reset Held Held Held Synchronization Sleep Standby Clock Held Held Held Held Held Held Pclk Pclk Pclk H'FFF0 0000 H'1FF0 0000 16 H'FFF0 0008 H'1FF0 0008 32 H'FFF0 0014 H'1FF0 0014 16 Undefined H'0000 Notes: *1 With control registers, the above addresses in the physical page number field can be accessed by means of a TLB setting. When these addresses are referenced directly without using the TLB, operations are limited. *2 Includes undefined bits. See the descriptions of the individual modules. *3 Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte-size access when reading. *4 SH7750S, SH7750R only *5 SH7750R only *6 Includes power-down states Rev. 6.0, 07/02, page 942 of 986 Appendix B Package Dimensions Unit: mm 27.0 0.20 (x 4) A B 2.1 Hitachi Code JEDEC JEITA Mass (reference value) 0.35 C 0.20 C C 0.6 0.1 0.635 W Y 1.27 A 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 256 x 0.75 0.15 0.30 M C A B 0.10 M C Details of the part A 1.27 V U T R P N M L K J H G F E D C B A 0.635 27.0 BP-256 Conforms -- 3.0 g Figure B.1 Package Dimensions (256-Pin BGA) (SH7750 and SH7750S) Rev. 6.0, 07/02, page 943 of 986 Unit: mm 27.0 0.20 (x 4) A B 2.1 Hitachi Code JEDEC JEITA Mass (reference value) 0.35 C 0.20 C C 0.6 0.1 0.635 W Y 1.27 A 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 256 x 0.75 0.15 0.30 M C A B 0.10 M C Details of the part A 1.27 V U T R P N M L K J H G F E D C B A 0.635 27.0 BP-256A Conforms -- 3.0 g Figure B.2 Package Dimensions (256-Pin BGA) (SH7750R Only) Rev. 6.0, 07/02, page 944 of 986 30.6 0.2 28 156 157 105 104 Unit: mm 30.6 0.2 208 1 *0.22 0.05 0.20 0.04 52 0.10 M 3.56 Max 53 0.5 *0.17 0.05 0.15 0.04 3.20 1.25 1.3 0 - 8 0.5 0.1 0.10 0.15 +0.10 -0.15 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC JEITA Mass (reference value) FP-208E -- Conforms 5.3 g Figure B.3 Package Dimensions (208-Pin QFP) Rev. 6.0, 07/02, page 945 of 986 Unit: mm 0.20 C B 15.00 0.80 0.20 C A 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1 A C E B D F H K M P T B 15.00 G J L N R U A 1.10 0.80 4x 0.15 1.10 264 x 0.50 0.05 0.08 M C A B 0.2 C C 0.40 0.05 1.40Max 0.10 C Hitachi Code JEDEC JEITA Mass (reference value) BP-264 - - 0.6 g Figure B.4 Package Dimensions (264-Pin CSP) Rev. 6.0, 07/02, page 946 of 986 Appendix C Mode Pin Settings The MD8-MD0 pin values are input in the event of a power-on reset via the 5(6(7 or SCK2/05(6(7 pin. (1) Clock Modes * Clock Operating Modes (SH7750, SH7750S) External Pin Combination Clock Operating Mode 0 1 2 3 4 5 1 0 1 1/2 Frequency Divider Off Off On Off On Off CPU Clock 6 6 3 6 3 6 Frequency (vs. Input Clock) Bus Clock 3/2 1 1 2 3/2 3 Peripheral Module Clock 3/2 1 1/2 1 3/4 3/2 FRQCR Initial Value H'0E1A H'0E23 H'0E13 H'0E13 H'0E0A H'0E0A MD2 0 MD1 0 MD0 0 1 0 1 0 1 PLL1 On On On On On On PLL2 On On On On On On Notes: 1. Turning on/off of the 1/2 frequency divider is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. * Clock Operating Modes (SH7750R) Clock Operating Mode 0 1 2 3 4 5 6 1 1 0 1 External Pin Combination MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 PLL1 On (x12) On (x12) On (x6) On (x12) On (x6) On (x12) Off (x6) PLL2 On On On On On On Off CPU Clock 12 12 6 12 6 12 1 Frequency (vs. Input Clock) Bus Clock 3 3/2 2 4 3 6 1/2 Peripheral Module Clock 3 3/2 1 2 3/2 3 1/2 FRQCR Initial Value H'0E1A H'0E2C H'0E13 H'0E13 H'0E0A H'0E0A H'0808 Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. Rev. 6.0, 07/02, page 947 of 986 (2) Area 0 Bus Width Pin Value MD6 0 MD4 0 MD3 0 1 1 0 1 1 0 0 1 1 0 1 Bus Width 64 bits 8 bits 16 bits 32 bits 64 bits 8 bits 16 bits 32 bits Memory Type MPX interface Reserved (setting prohibited) Reserved MPX interface SRAM interface SRAM interface SRAM interface SRAM interface (3) Endian Pin Value MD5 0 1 Endian Big endian Little endian (4) Master/Slave Pin Value MD7 0 1 Master/Slave Slave Master (5) Clock Input Pin Value MD8 0 1 Clock Input External input clock Crystal resonator Rev. 6.0, 07/02, page 948 of 986 Appendix D &.,25(1% Pin Configuration SH7750 Series rd_pullup_control rd_dt_ rd_hiz_control VDDQ / / VDDQ VDDQ rdwr_pullup_control rdwr_dt_ rdwr_hiz_control VDDQ RD/ RD/ Bus clock PLL2 ckio_hiz_control CKIO CKIO2 VDDQ VSSQ Figure D.1 &.,25(1% Pin Configuration Rev. 6.0, 07/02, page 949 of 986 &.,25(1% 0 1 Description 5'5, RD/:55, and CKIO2 have the same pin states as 5', RD/:5, and CKIO, respectively 5'5, RD/:55, and CKIO2 are in the high-impedance state Note: CKIO is fed back to PLL2 to coordinate the external clock and internal clock phases. However, CKIO2 is not fed back. Rev. 6.0, 07/02, page 950 of 986 Appendix E Pin Functions E.1 Pin States Pin States in Reset, Power-Down State, and Bus-Released State Reset (Power-On) Signal Name D0-D7 D8-D15 D16-D23 D24-D31 D32-D51 I/O I/O I/O I/O I/O I/O Master Slave 15 Z* 15 Z* 15 Z* 15 Z* Table E.1 Reset (Manual) Master Slave Z* 15 Bus Standby Released Z* 15 Hardware Standby Notes Z Z Z Z Z Output state held when used as port Z* 15 Z* 15 15 Z* 15 Z* 15 Z* 15 Z* Z* Z* Z* 15 Z* Z* Z* 15 Z* Z* 15 Z* Z* 15 15 Z* Z* 15 15 Z* Z* 15 15 15 15 15 15 15 15 15 ZK * ZK * Z* K 15 Z* K 15 D52-D55 D56-D63 A0, A1, A18-A25 A2-A17 5(6(7 %$&./%65(4 %5(4/%6$&. %6 CKE &69-&63 5$6 5'/&$66 RD/:5 5'< :(:/&$6:/DQM7 :(9/&$69/DQM6 :(8/&$68/DQM5 :(7/&$67/DQM4 :(6/&$66/DQM3 I/O I/O O O I O I O O O O O O I O O O O O Z* Z* Z* Z* I H I* H H H H H H 15 Z* Z* Z* Z* I H 15 Z* Z* 15 Z* Z* 17 15 Z* Z* 15 Z* Z* 7 15 Z Z Z Z I Z 15 15 15 15 15 15 16 16 Z* O* Z* O* I H 14 14 Z* Z* I H 14 Z* O* Z* O* I H 14 14 Z* Z* I O 14 16 16 9 14 7 14 16 I* 16 I* H 13 I* 13 I* 13 I* 7 13 I Z Z Z 5 Z* H Z* Z* Z* Z* 16 Z* 6 14 Z* H* L Z* H* 14 14 14 Z* 14 O* 16 O* Z* 6 O* 7 6 H O* O* H 13 I* 6 O* 6 O* 6 O* 6 O* 6 14 Z* 14 16 Z* Z* Z* 14 Z* O* Z* O* Z* H* 13 I* 14 14 5 Z* O* Z* O* Z* 14 14 14 Z Z Z I Z Z Z Z Z 16 6 14 5 5 16 14 7 16 PI* 16 PI* 16 Z* 16 Z* 16 Z* 13 I* 14 Z* 14 Z* 14 Z* 13 I* 14 5 Z* O* 14 5 Z* O* 14 5 Z* O* 14 5 Z* O* H H H H H 14 5 Z* O* 14 5 Z* O* 14 5 Z* O* 14 5 Z* O* Z* Z* 16 Z* Z* 14 16 O* 6 14 Z* O* 14 5 Z* O* 14 5 Rev. 6.0, 07/02, page 951 of 986 Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State (cont) Reset (Power-On) Reset (Manual) Master Slave 6 O* Signal Name :(5/&$65/DQM2 :(4/&$64/DQM1 :(3/&$63/DQM0 DACK1-DACK0 MD7/TXD MD6/,2,649 MD5/5$65 MD4/&(5% MD3/&(5$ CKIO STATUS1- STATUS0 ,5/6-,5/3 NMI '5(44-'5(43 DRAK1-DRAK0 MD0/SCK RXD SCK2/05(6(7 MD1/TXD2 MD2/RXD2 &765 MD8/5765 TCLK TDO TMS TCK TDI 7567 CKIO2* 10 I/O O O O O I/O I Master Slave H H H L I* I* 16 Bus Standby Released 14 5 Z* O* 14 5 Z* O* Hardware Standby Notes Z Z Z Z Z I Z Z Z Z Z* 18 Z* Z* Z* L I* I* I* 16 Z* Z* Z* L 14 16 O* O* L 6 14 Z* O* Z* O* Z* O* 12 14 14 5 Z* O* Z* O* O* 12 14 14 5 16 6 14 5 5 8 DMAC SCI PCMCIA (I/O) DRAM2 PCMCIA PCMCIA 16 Z* I* 12 Z* I* 12 Z* O* I* 13 12 8 Z* O I* 13 12 16 16 13 13 1 16 I/O* I* 2 16 I/O* I* 3 16 I/O* I* 16 13 6 13 Z* O* Z* 13 Z* H 13 Z* H 11 ZO* 13 Z* 13 Z* 11 ZO* 13 5 Z* O* 13 7 Z* H* 13 7 Z* H* 11 ZO* 13 5 Z* O* 13 Z* 13 Z* 11 ZO* 16 I* 16 I* O O I I I O I/O I I I/O I I/O I/O I/O O I I I I O O O 16 PI* O O 16 PI* O I* I* I* L 16 13 O I* I* I* L 12 13 O I* I* I* 13 O I* I* I* 8 13 I I I Z Z I I Z I Z Z Z Z INTC INTC DMAC DMAC SCI SCI SCIF SCIF SCIF SCIF SCIF TMU H-UDI H-UDI H-UDI H-UDI H-UDI PI* PI* L I* 16 16 PI* PI* L I* 16 13 13 13 13 16 16 12 12 12 12 Z* O* 12 12 12 O* 8 12 I* 16 I* I* I* I* Z* O* I* O I* I* 12 12 12 PI* PI* 16 I* 16 I* 16 PI* PI* 16 I* 16 I* I* I* 12 12 I* I* 12 16 16 12 12 12 12 12 Z* 12 I* 12 I* 12 I* 12 Z* 12 I* 12 I* 12 I* 12 8 Z* O* 12 I* 12 Z* O 12 I* 16 PI* 16 I* 16 PI* 16 PI* 16 I* 16 PI* 12 12 8 12 I* Z* O* I* O 12 12 8 12 I* Z* O* I* O I* O 12 I* O 12 I* O O 12 I* O O 12 O PI* PI* PI* PI* O 16 O PI* PI* PI* PI* O 16 I* I* I* I* 16 I* I* I* I* 11 16 I* I* I* I* 11 16 I* I* I* I* 11 16 I I I I 11 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ZO* ZO* ZO* ZO* Z Rev. 6.0, 07/02, page 952 of 986 Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State (cont) Reset (Power-On) Reset (Manual) Master Slave 6 O* Signal Name 5'5* 10 I/O O Master Slave H H I I Z* Z* I I 16 Bus Standby Released 14 5 Z* O* 14 5 Z* O* Hardware Standby Notes Z Z I I Z* Z* I I 14 RD/:55* 10 O I I 16 H I I 14 Z* H* I I 14 7 Z* I I 14 &.,25(1% CA Notes: I: O: H: L: Z: K: Input Output High-level output Low-level output High-impedance Output state held Output when area 2 DRAM is used. Output when area 5 PCMCIA is used. Output when area 6 PCMCIA is used. Depends on refresh and DMAC operations. Z (I) or O (refresh), depending on register setting (BCR1.HIZCNT). Depends on refresh operation. Z (I) or H (state held), depending on register setting (BCR1.HIZMEM). Z or O, depending on register setting (STBCR.PHZ). Output when refreshing is set. Operation in respective state when &.,25(1% = 0; Z when &.,25(1% = 1. Z or O, depending on register setting (FRQCR.CKOEN). Pulled up or not pulled up, depending on register setting (STBCR.PPU). Pulled up or not pulled up, depending on register setting (BCR1.IPUP). Pulled up or not pulled up, depending on register setting (BCR1.OPUP). Not pulled up. Pulled up with a built-in pull-up resistance. However, cannot be used for MD pin pullup in a power-on reset. Pull up or down outside the SH-4. *17 Output when refreshing is set (SH7750R only). *18 Z or O, depending on register setting (STBCR2.STHZ) (SH7750R only). *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 *14 *15 *16 Rev. 6.0, 07/02, page 953 of 986 E.2 Handling of Unused Pins * When RTC is not used EXTAL2: Pull up to 3.3 V Leave unconnected XTAL2: VDD-RTC: Power supply (3.3 V) VSS-RTC: Power supply (0 V) * When PLL1 is not used VDD-PLL1: Power supply (3.3 V) VSS-PLL1: Power supply (0 V) * When PLL2 is not used VDD-PLL2: Power supply (3.3 V) VSS-PLL2: Power supply (0 V) * When on-chip crystal oscillator is not used Leave unconnected XTAL: VDD-CPG: Power supply (3.3 V) VSS-CPG: Power supply (0 V) Rev. 6.0, 07/02, page 954 of 986 Appendix F Synchronous DRAM Address Multiplexing Tables (1) BUS 64 AMX 0 (16M: 512k x 16b x 2) x 4 * AMXEXT 0 16M, column-addr-8bit Synchronous DRAM Address Pins A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8MB Function BANK selects bank address Address precharge setting Address SH7750 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A22 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Rev. 6.0, 07/02, page 955 of 986 (2) BUS 32 AMX 0 (16M: 512k x 16b x 2) x 2 * AMXEXT 0 16M, column-addr-8bit Synchronous DRAM Address Pins 4MB Function SH7750 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A21 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev. 6.0, 07/02, page 956 of 986 (3) BUS 64 AMX 0 (16M: 512k x 16b x 2) x 4 * AMXEXT 1 16M, column-addr-8bit Synchronous DRAM Address Pins A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8MB Function BANK selects bank address Address precharge setting Address SH7750 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A22 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A21 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Rev. 6.0, 07/02, page 957 of 986 (4) BUS 32 AMX 0 (16M: 512k x 16b x 2) x 2 * AMXEXT 1 16M, column-addr-8bit Synchronous DRAM Address Pins 4MB Function SH7750 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A21 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A20 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev. 6.0, 07/02, page 958 of 986 (5) BUS 64 AMX 1 (16M: 1M x 8b x 2) x 8 * AMXEXT 0 16M, column-addr-9bit Synchronous DRAM Address Pins A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16MB Function BANK selects bank address Address precharge setting Address SH7750 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Not used CAS Cycle A23 H/L 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 Rev. 6.0, 07/02, page 959 of 986 (6) BUS 32 AMX 1 (16M: 1M x 8b x 2) x 4 * AMXEXT 0 16M, column-addr-9bit Synchronous DRAM Address Pins 8MB Function SH7750 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A22 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev. 6.0, 07/02, page 960 of 986 (7) BUS 64 AMX 1 (16M: 1M x 8b x 2) x 8 * AMXEXT 1 16M, column-addr-9bit Synchronous DRAM Address Pins A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16MB Function BANK selects bank address Address precharge setting Address SH7750 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A23 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Not used CAS Cycle A22 H/L 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 Rev. 6.0, 07/02, page 961 of 986 (8) BUS 32 AMX 1 (16M: 1M x 8b x 2) x 4 * AMXEXT 1 16M, column-addr-9bit Synchronous DRAM Address Pins 8MB Function SH7750 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A22 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A21 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev. 6.0, 07/02, page 962 of 986 (9) BUS 64 AMX 2 (64M: 1M x 16b x 4) x 4 * 64M, column-addr-8bit 32MB Function BANK selects bank address SH7750 Series Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A24 A23 0 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Address precharge setting Rev. 6.0, 07/02, page 963 of 986 (10) BUS 32 AMX 2 (64M: 1M x 16b x 4) x 2 * 64M, column-addr-8bit 16MB Function SH7750 Series Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A23 A22 0 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev. 6.0, 07/02, page 964 of 986 (11) BUS 64 AMX 3 (64M: 2M x 8b x 4) x 8 * (128M: 2M x 16b x 4) x 4 64M, column-addr-9bit 64MB Function BANK selects bank address SH7750 Series Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Not used CAS Cycle A25 A24 0 H/L 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Address precharge setting Rev. 6.0, 07/02, page 965 of 986 (12) BUS 32 AMX 3 (64M: 2M x 8b x 4) x 4 * (128M: 2M x 16b x 4) x 2 64M, column-addr-9bit 32MB Function SH7750 Series Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A24 A23 0 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev. 6.0, 07/02, page 966 of 986 (13) BUS 64 AMX 4 (64M: 512k x 32b x 4) x 2 * 64M, column-addr-8bit 16MB Function BANK selects bank address SH7750 Series Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A23 A22 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Rev. 6.0, 07/02, page 967 of 986 (14) BUS 32 AMX 4 (64M: 512k x 32b x 4) x 1 * 64M, column-addr-8bit 8MB Function SH7750 Series Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A22 A21 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev. 6.0, 07/02, page 968 of 986 (15) BUS 64 AMX 5 (64M: 1M x 32b x 2) x 2 * 64M, column-addr-8bit 16MB Function BANK selects bank address SH7750 Series Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A23 0 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Rev. 6.0, 07/02, page 969 of 986 (16) BUS 32 AMX 5 (64M: 1M x 32b x 2) x 1 * 64M, column-addr-8bit 8MB Function SH7750 Series Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A22 0 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev. 6.0, 07/02, page 970 of 986 (17) BUS 64 (128M: 4M x 8b x 4) x 8 (SH7750R only) AMX 6 128M, column-addr-10bit 128MB AMXEXT0 SH7750 Series Address Pins RAS Cycle CAS Cycle A26 A25 0 H/L A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Function BANK selects bank address A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 Not used Not used Not used Rev. 6.0, 07/02, page 971 of 986 (18) BUS 64 (256M: 4M x 16b x 4) x 4 (SH7750R only) * AMX 6 256M, column-addr-9bit 128MB AMXEXT1 SH7750 Series Address Pins RAS Cycle CAS Cycle A26 A25 0 0 H/L 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Function BANK selects bank address A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Not used Rev. 6.0, 07/02, page 972 of 986 (19) BUS 32 (128M: 4M x 8b x 4) x 4 (SH7750S and SH7750R only) * AMX 6 column-addr-10bit 64MB AMXEXT 0 SH7750 Series Address Pins RAS Cycle CAS Cycle A25 A24 0 H/L A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Function BANK selects bank address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Rev. 6.0, 07/02, page 973 of 986 (20) BUS 32 (256M: 4M x 16b x 4) x 2 (SH7750S and SH7750R only) * AMX 6 256M, column-addr-9bit 64MB AMXEXT 1 SH7750 Series Address Pins RAS Cycle CAS Cycle A25 A24 0 0 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 Synchronous DRAM Address Pins A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Function BANK selects bank address A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Rev. 6.0, 07/02, page 974 of 986 (21) BUS 64 AMX 7 (16M: 256k x 32b x 2) x 2 * 16M, column-addr-8bit 4MB Function BANK selects bank address Address precharge setting Address SH7750 Series Address Pins RAS Cycle A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A21 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Rev. 6.0, 07/02, page 975 of 986 (22) BUS 32 AMX 7 (16M: 256k x 32b x 2) x 1 * 16M, column-addr-8bit 2MB Function SH7750 Series Address Pins RAS Cycle A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A20 H/L 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Note: * Example of a synchronous DRAM configuration Rev. 6.0, 07/02, page 976 of 986 Appendix G Prefetching of Instructions and its Side Effects The SH7750 series incorporates an on-chip buffer for holding instructions that have been read ahead of their execution (prefetching of instructions). Therefore, do not allocate programs to memory in such a way that instructions are in the last 20 bytes of any memory space. If a program is allocated in such a way, the prefetching of instructions may lead to a bus access for reading an instruction from beyond the memory space. The following shows a case in which such bus access is a problem. . . . . . . ADD R1,R4 JMP @R2 NOP NOP PC (Program counter) Address H'03FFFFF8 H'03FFFFFA H'03FFFFFC H'03FFFFFE H'04000000 H'04000002 Area 0 Area 1 Address of instruction for prefetching Figure G.1 Instruction Prefetch Figure G.1 depicts a case in which the instruction (ADD) indicated by the program counter and the instruction at the address H'04000002 are fetched simultaneously. The program is assumed to branch to a region other than area 1 after the subsequent JMP instruction and delay slot instruction have been executed. In this case, a bus access to area 1 (instruction prefetch), which is not visible in the program flow, may occur. 1. Side effects of the prefetching of instructions a. An external bus access caused by an instruction prefetch may cause malfunctions in external devices, such as FIFOs, that are connected to the region accessed. b. If no device responds to an external bus request that is triggered by an instruction prefetch, execution may hang. 2. Methods of preventing the invalid prefetching of instructions a. Use an MMU. b. Do not allocate programs so that they run into the last 20-byte region of any memory space. Rev. 6.0, 07/02, page 977 of 986 Appendix H Power-On and Power-Off Procedures * Power-on 1 Supply the internal power after supplying power to the I/O, PLL, RTC, and CPG.* Supply power to VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG simultaneously. At power-on, the 5(6(7 signal is low. Normally, supply power to the I/O, RTC, and CPG before (or at the same time as) entering the signal lines (5(6(7, SCK2, MD0 to MD10, and external clock). If the signal lines are entered first, the LSI may be damaged. Input high level to SCK2 (05(6(7) in compliance with the voltage level of the I/O, PLL, RTC, CPG power supply voltage. * Power-off When turning off the power, there are no restrictions for the timing of 5(6(7 and SCK2. 1 Turn off the I/O, PLL, RTC, CPG power supply voltage after (or at the same time as)* turning off the internal power supply voltage. Note however that the internal power supply voltage may exceed the I/O, PLL, RTC, CPG power supply voltage by a maximum of 0.3 V only when the system is being turned off. The power supply level must be lowered in compliance with the I/O, PLL, RTC, CPG power supply voltage. Note: *1 10 ms or less for the HD6417750R. * The ratings and procedures for power-on and power-off are given below. VSSQ = VSS-PLL1 = VSS-PLL2 = VSS-RTC = VSS-CPG = 0 V The LSI may be damaged if -0.3 V < Vin < VDDQ + 0.3 V -0.3 V < VDD < VDDQ + 0.3 V are not satisfied when VDDQ = VDD-RTC = VDD-CPG. Power-on 2.0 V VDD 1.2 V GND ton 0 ton < 10 ms* Note: * HD6417750R only toff 0 toff < 10 ms* VDDQ Power-off Figure H.1 Power-On and Power-Off Procedures Rev. 6.0, 07/02, page 978 of 986 Appendix I Product Code Lineup Table I.1 SH7750 Series Product Code Lineup Voltage 1.95 V 1.8 V Operating Frequency 200 MHz 167 MHz Operating Temperature -20 to 75C -20 to 75C -40 to 85C 1.5 V SH7750S 1.95 V 128 MHz 200 MHz -20 to 75C -20 to 75C -20 to 75C 1.8 V 167 MHz -20 to 75C -40 to 85C 1.5 V 133 MHz -20 to 75C -30 to 70C SH7750R 1.5 V 240 MHz -20 to 75C -20 to 75C 1.5 V 200 MHz -20 to 75C -20 to 75C Mark Code HD6417750BP200M HD6417750F167 HD6417750F167I HD6417750VF128 HD6417750SBP200 HD6417750SF200 HD6417750SF167 HD6417750SF167I HD6417750SVF133 HD6417750SVBT133 HD6417750RBP240 HD6417750RF240 HD6417750RBP200 HD6417750RF200 CSP-264 BGA-256 QFP-208 BGA-256 QFP-208 BGA-256 QFP-208 QFP-208 Package BGA-256 QFP-208 Abbreviation SH7750 Rev. 6.0, 07/02, page 979 of 986 Rev. 6.0, 07/02, page 980 of 986 Index A Address Space ...........................................64 B Big endian .................................................53 Bus Arbitration........................................480 Bus State Controller ................................311 Address Multiplexing..........................399 Areas ...........................................319, 382 Burst Access........................................402 Burst ROM Interface...........................441 Byte Control SRAM Interface.............473 DRAM Interface .................................395 EDO Mode ..........................................403 Endian .................................................370 I/O card interface ........................322, 444 IC memory card interface............322, 444 Master Mode .......................................483 MPX Interface.....................................455 Partial-Sharing Master Mode ..............485 PCMCIA Interface ..............................444 PCMCIA Support................................322 RAS Down Mode................................404 Refresh Timing ...................................409 Refreshing ...........................................431 Slave Mode .........................................484 SRAM Interface ..................................387 Synchronous DRAM Interface............413 Wait State Control...............................401 Waits between Access Cycles .............478 C Caches .......................................................95 Address Array ............. 112, 114, 117, 119 cache fill..............................................108 Data Array................... 113, 115, 118, 120 IC Index Mode ....................................111 Instruction Cache ..........................95, 108 OC Index Mode...................................107 Operand Cache ................................95, 99 prefetch................................................122 Prefetch Operation...............................108 RAM Mode .........................................106 Store Queues .......................................122 Tag...............................................102, 110 U bit.....................................................102 V bit.............................................102, 110 Write-Back Buffer ...............................105 Write-Through Buffer .........................105 Clock Oscillation Circuits .......................247 Bus Clock Division Ratio ....................258 Changing the Frequency......................257 Clock Operating Modes.......................253 PLL Circuit..........................................257 clock pulse generator...............................247 Control Registers.................................42, 49 DBR.......................................................50 Debug base register ...............................50 GBR.......................................................50 Global base register ...............................50 Saved general register 15 ......................50 Saved program counter..........................50 Saved status register ..............................50 SGR .......................................................50 SPC........................................................50 SR ..........................................................49 SSR........................................................50 Status register ........................................49 VBR.......................................................50 Vector base register ...............................50 D Data Format...............................................53 Direct Memory Access Controller...........489 Address Modes ....................................519 Burst Mode..........................................523 Bus Modes...........................................522 Channel Priorities ................................515 Cycle Steal Mode ................................522 Rev. 6.0, 07/02, page 981 of 986 DMA Transfer.....................................518 DMA Transfer Requests .....................512 Dual Address Mode ............................520 Ending DMA Transfer ........................541 Fixed Mode .........................................515 On-Demand Data Transfer Mode........545 Round Robin Mode.............................515 Single Address Mode ..........................519 E effective address......................................175 Exceptions...............................................127 Address Error ..............................146, 147 Exception Types..................................130 FPU exception.............................154, 169 General Exceptions .............................141 General FPU Disable Exception .........151 General illegal instruction ...................169 General Illegal Instruction Exception .149 Initial Page Write Exception ...............143 Instruction TLB Protection Violation Exception ........................................145 Slot FPU Disable Exception................152 slot illegal instruction exception .........169 Slot Illegal Instruction Exception........150 TLB Miss Exception ...................141, 142 TLB Multiple-Hit Exception.......139, 140 TLB Protection Violation Exception...144 Unconditional Trap .............................148 User Breakpoint Trap..........................153 External Memory Space Map..................320 F Floating-Point Registers.............. 43, 47, 165 Floating-Point Unit .................................161 Denormalized Numbers ......................164 Floating-Point Format .........................161 Geometric Operation Instructions .......170 NaN .............................................163, 164 Non-Numbers......................................163 Pair Single-Precision Data Transfer ....172 G General Registers ................................42, 45 Graphics Support Functions ....................170 H Hitachi User Debug Interface..................799 TAP Control ........................................810 I I/O Ports ..................................................731 Instruction Set .................................173, 179 Arithmetic Operation Instructions .......182 Branch instructions......................186, 214 Data transfer instructions.....................211 Double-precision floating-point instructions ......................................217 Fixed-point arithmetic instructions......212 Fixed-Point Transfer Instructions........180 Floating-Point Control Instructions .....190 Floating-Point Double-Precision Instructions ......................................190 Floating-Point Graphics Acceleration Instructions ......................................191 Floating-Point Single-Precision Instructions ......................................189 FPU system control instructions..........218 Graphics acceleration instructions.......218 Logic Operation Instructions...............184 Shift instructions..........................185, 214 Single-precision floating-point instructions ......................................216 System control instructions .........187, 215 Interrupt Controller .................................751 Interrupt Priority..................................759 On-Chip Peripheral Module Interrupts757 Interrupts .................................................155 ATI ......................................................289 BRI ......................................................697 ERI ......................................651, 697, 724 IRL Interrupts..............................156, 755 NMI .....................................................155 NMI Interrupt ......................................754 Peripheral Module Interrupts...............157 Rev. 6.0, 07/02, page 982 of 986 PRI ......................................................289 RXI...................................... 651, 697, 724 TEI ......................................................651 TICPI...................................................309 TUNI ...................................................309 TXI...................................... 651, 697, 724 L Little endian ..............................................53 M Memory Management Unit .......................57 Address Array .................................88, 90 Address Space Identifier .......................70 Address Translation ..............................69 Address Translation Method .................75 ASID .....................................................70 Avoiding Synonym Problems ...............80 Data Array.......................................89, 92 External memory space ...................64, 67 ITLB......................................................75 LDTLB..................................................78 MMU Exceptions..................................81 MMU Functions....................................78 Physical address space ....................58, 64 time sharing system...............................57 TLB .................................................57, 71 UTLB ....................................................71 Virtual address space.......................58, 68 virtual memory system..........................57 P Pipelining ................................................193 Execution Cycles.........................204, 211 Parallel-Executability..........................200 Pipeline Stalling ..................................204 Power-Down Modes ...............................221 Clock Pause Function..........................232 Deep Sleep Mode ................................230 Exit from Standby Mode.....................232 Hardware Standby Mode.....................235 High Impedance Control .....................226 Module Standby Function ...................233 Pull-Up Control ...................................226 Sleep Mode..........................................230 Programming Model .................................41 Banks.....................................................42 Data Formats .........................................41 Privileged Mode ....................................42 R Realtime Clock ........................................267 Alarm Function ...................................288 Crystal Oscillator Circuit.....................289 CUI ......................................................289 Time Setting ........................................285 Registers BAMRA ..............................................778 BAMRB ..............................................781 BARA..................................................777 BARB ..................................................781 BASRA................................................778 BASRB................................................781 BBRA ..................................................779 BBRB ..................................................783 BCR1...................................................326 BCR2...................................................335 BDRB ..................................................781 BRCR ..................................................783 CCR.......................................................97 CHCR ..................................................499 DAR ....................................................497 DMAOR ..............................................507 DMATCR............................................498 EXPEVT..............................................128 FPSCR.................................................167 FPUL ...................................................168 FRQCR................................................254 GPIOIC................................................745 ICR ......................................................762 INTEVT ..............................................128 IPR.......................................................761 MCR ....................................................352 MMUCR................................................61 PCR .....................................................359 PCTRA ................................................742 Rev. 6.0, 07/02, page 983 of 986 PCTRB ................................................744 PDTRA................................................743 PDTRB................................................745 PTEH.....................................................61 QACR0 .................................................97 R64CNT ..............................................271 RCR1...................................................279 RCR2...................................................281 RDAYAR............................................278 RDAYCNT .........................................274 RFCR ..................................................369 RHRAR...............................................277 RHRCNT ............................................272 RMINAR.............................................276 RMINCNT ..........................................272 RMONAR ...........................................279 RMONCNT.........................................274 RSECAR .............................................276 RSECCNT...........................................271 RTCNT................................................367 RTCOR ...............................................368 RTCSR ................................................364 RWKAR..............................................277 RWKCNT ...........................................273 RYRCNT ............................................275 SAR.....................................................496 SCBRR1..............................................613 SCBRR2..............................................674 SCFCR2 ..............................................675 SCFDR2 ..............................................678 SCFRDR2 ...........................................662 SCFSR2...............................................668 SCFTDR2............................................663 SCLSR2 ..............................................684 SCRDR1..............................................597 SCRSR1 ..............................................597 SCRSR2 ..............................................661 SCSCMR1...........................................706 SCSCR1 ......................................601, 708 SCSCR2 ..............................................665 SCSMR1 .....................................599, 707 SCSMR2 .............................................663 SCSPTR1 ....................................609, 746 Rev. 6.0, 07/02, page 984 of 986 SCSPTR2 ....................................679, 748 SCSSR1 .......................................605, 709 SCTDR1 ..............................................598 SCTSR1...............................................598 SCTSR2...............................................662 SDBPR ................................................805 SDDR ..................................................805 SDIR....................................................803 SDMR..................................................362 STBCR ................................................224 STBCR2 ..............................................227 TCNT ..................................................298 TCOR ..................................................298 TCPR2 .................................................303 TCR .....................................................299 TEA .......................................................61 TOCR ..................................................295 TRA.....................................................128 TSTR ...................................................296 TTB .......................................................61 WCR1..................................................340 WCR2..................................................343 WCR3..................................................351 WTCNT...............................................260 WTCSR ...............................................261 Resets ......................................................136 H-UDI Reset................................138, 811 Manual Reset.......................................137 Power-On Reset...................................136 Rounding .................................................168 S Serial Communication Interface..............593 Asynchronous mode ....................621, 623 Bit Rate................................................613 Break ...................................................652 Framing error...............................632, 652 Multiprocessor Communication Function .........................................................634 Overrun error...............................632, 652 Parity error...................................632, 652 Synchronous mode ......................621, 642 Serial Communication Interface with FIFO ............................................................657 Asynchronous Mode ...........................685 Break ...................................................698 Smart Card Interface ...............................703 bit rate .................................................715 System Registers .................................42, 50 Floating-point status/control register ....51 FPSCR...................................................51 MACH...................................................50 MACL ...................................................50 Multiply-and-accumulate register high .50 Multiply-and-accumulate register low ..50 PC..........................................................50 PR..........................................................50 Procedure register .................................50 Program counter....................................50 T Timer Unit ...............................................291 Auto-Reload Count Operation.............305 Input Capture Function........................307 TCNT Count Timing ...........................306 U User Break Controller .............................773 Instruction Access Cycle Break...........788 Operand Access Cycle Break ..............789 User Break Debug Support Function...793 User Break Operation Sequence..........787 W Watchdog Timer..............................247, 259 Interval Timer Mode ...........................265 Watchdog Timer Mode .......................264 Rev. 6.0, 07/02, page 985 of 986 Rev. 6.0, 07/02, page 986 of 986 SH7750 Series Hardware Manual Publication Date: 1st Edition, June 1998 6th Edition, July 2002 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. |
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